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From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: acme@redhat.com, linux@yadro.com, anup@brainfault.org,
	n.shubin@yadro.com, aou@eecs.berkeley.edu,
	alexander.shishkin@linux.intel.com, mingo@redhat.com,
	jolsa@kernel.org, linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	linux-riscv@lists.infradead.org, mark.rutland@arm.com,
	namhyung@kernel.org, Paul Walmsley <paul.walmsley@sifive.com>,
	peterz@infradead.org, Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v6 0/3] RISC-V: Create unique identification for SoC PMU
Date: Mon, 17 Oct 2022 09:24:59 -0300	[thread overview]
Message-ID: <Y01Jm6PHA1m7B1Vl@kernel.org> (raw)
In-Reply-To: <20221017091948.1961294e@redslave.neermore.group>

Em Mon, Oct 17, 2022 at 09:19:48AM +0300, Nikita Shubin escreveu:
> On Mon, 03 Oct 2022 19:54:40 -0700 (PDT)
> Palmer Dabbelt <palmer@dabbelt.com> wrote:
> > On Mon, 15 Aug 2022 06:22:37 PDT (-0700), nikita.shubin@maquefel.me wrote:
> > > From: Nikita Shubin <n.shubin@yadro.com>

> > > This series aims to provide matching vendor SoC with corresponded
> > > JSON bindings.
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
 
> > not sure if you're looking for this via the RISC-V tree, it looks
> > like usually these get merged via a perf tree?  That's OK with me,
> > but I'm also OK taking them through the RISC-V tree.  Note that
> > cpuinfo dependency seems to be triggering kasan failures, so we'll at
> > least need to sort that out.

> As i remember correctly you were willing to take these patches into 6.0
> =).

> Well they are acked by Palmer and [2] series, which my series depends
> on, also have been accepted.

> I can resend if it helps you.

I picked it from this Message-ID with b4, applied cleanly, but yesterday
the merge window closed for v6.1, I applied it to my perf/core branch,
for v6.2.

Thanks,

- Arnaldo

WARNING: multiple messages have this Message-ID (diff)
From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: acme@redhat.com, linux@yadro.com, anup@brainfault.org,
	n.shubin@yadro.com, aou@eecs.berkeley.edu,
	alexander.shishkin@linux.intel.com, mingo@redhat.com,
	jolsa@kernel.org, linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	linux-riscv@lists.infradead.org, mark.rutland@arm.com,
	namhyung@kernel.org, Paul Walmsley <paul.walmsley@sifive.com>,
	peterz@infradead.org, Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v6 0/3] RISC-V: Create unique identification for SoC PMU
Date: Mon, 17 Oct 2022 09:24:59 -0300	[thread overview]
Message-ID: <Y01Jm6PHA1m7B1Vl@kernel.org> (raw)
In-Reply-To: <20221017091948.1961294e@redslave.neermore.group>

Em Mon, Oct 17, 2022 at 09:19:48AM +0300, Nikita Shubin escreveu:
> On Mon, 03 Oct 2022 19:54:40 -0700 (PDT)
> Palmer Dabbelt <palmer@dabbelt.com> wrote:
> > On Mon, 15 Aug 2022 06:22:37 PDT (-0700), nikita.shubin@maquefel.me wrote:
> > > From: Nikita Shubin <n.shubin@yadro.com>

> > > This series aims to provide matching vendor SoC with corresponded
> > > JSON bindings.
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
 
> > not sure if you're looking for this via the RISC-V tree, it looks
> > like usually these get merged via a perf tree?  That's OK with me,
> > but I'm also OK taking them through the RISC-V tree.  Note that
> > cpuinfo dependency seems to be triggering kasan failures, so we'll at
> > least need to sort that out.

> As i remember correctly you were willing to take these patches into 6.0
> =).

> Well they are acked by Palmer and [2] series, which my series depends
> on, also have been accepted.

> I can resend if it helps you.

I picked it from this Message-ID with b4, applied cleanly, but yesterday
the merge window closed for v6.1, I applied it to my perf/core branch,
for v6.2.

Thanks,

- Arnaldo

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-10-17 12:25 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-15 13:22 [PATCH v6 0/3] RISC-V: Create unique identification for SoC PMU Nikita Shubin
2022-08-15 13:22 ` Nikita Shubin
2022-08-15 13:22 ` [PATCH v6 1/3] perf tools riscv: Add support for get_cpuid_str function Nikita Shubin
2022-08-15 13:22   ` Nikita Shubin
2022-08-15 13:22 ` [PATCH v6 2/3] perf arch events: riscv sbi firmware std event files Nikita Shubin
2022-08-15 13:22   ` Nikita Shubin
2022-08-15 13:22 ` [PATCH v6 3/3] perf vendor events riscv: add Sifive U74 JSON file Nikita Shubin
2022-08-15 13:22   ` Nikita Shubin
2022-10-04  2:54 ` [PATCH v6 0/3] RISC-V: Create unique identification for SoC PMU Palmer Dabbelt
2022-10-04  2:54   ` Palmer Dabbelt
2022-10-17  6:19   ` Nikita Shubin
2022-10-17  6:19     ` Nikita Shubin
2022-10-17 12:24     ` Arnaldo Carvalho de Melo [this message]
2022-10-17 12:24       ` Arnaldo Carvalho de Melo

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