* [PATCH 0/2] phy: ti: phy-j721e-wiz: add j784s4 support @ 2022-10-15 20:11 ` Matt Ranostay 0 siblings, 0 replies; 10+ messages in thread From: Matt Ranostay @ 2022-10-15 20:11 UTC (permalink / raw) To: vkoul, robh+dt, krzysztof.kozlowski+dt, vigneshr Cc: linux-phy, devicetree, Matt Ranostay WIZ modules for J784S4 platform have two input muxes which requires additional mux sections options. Matt Ranostay (2): dt-bindings: phy-j721e-wiz: add j784s4 compatible string phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module support .../bindings/phy/ti,phy-j721e-wiz.yaml | 1 + drivers/phy/ti/phy-j721e-wiz.c | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) -- 2.38.0.rc0.52.gdda7228a83 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2] phy: ti: phy-j721e-wiz: add j784s4 support @ 2022-10-15 20:11 ` Matt Ranostay 0 siblings, 0 replies; 10+ messages in thread From: Matt Ranostay @ 2022-10-15 20:11 UTC (permalink / raw) To: vkoul, robh+dt, krzysztof.kozlowski+dt, vigneshr Cc: linux-phy, devicetree, Matt Ranostay WIZ modules for J784S4 platform have two input muxes which requires additional mux sections options. Matt Ranostay (2): dt-bindings: phy-j721e-wiz: add j784s4 compatible string phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module support .../bindings/phy/ti,phy-j721e-wiz.yaml | 1 + drivers/phy/ti/phy-j721e-wiz.c | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) -- 2.38.0.rc0.52.gdda7228a83 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/2] dt-bindings: phy-j721e-wiz: add j784s4 compatible string 2022-10-15 20:11 ` Matt Ranostay @ 2022-10-15 20:11 ` Matt Ranostay -1 siblings, 0 replies; 10+ messages in thread From: Matt Ranostay @ 2022-10-15 20:11 UTC (permalink / raw) To: vkoul, robh+dt, krzysztof.kozlowski+dt, vigneshr Cc: linux-phy, devicetree, Matt Ranostay Add ti,j784s4-wiz-10g compatible string to binding documentation. Signed-off-by: Matt Ranostay <mranostay@ti.com> --- Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 2225925b6dad..a9e38739c010 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -17,6 +17,7 @@ properties: - ti,j721e-wiz-10g - ti,am64-wiz-10g - ti,j7200-wiz-10g + - ti,j784s4-wiz-10g power-domains: maxItems: 1 -- 2.38.0.rc0.52.gdda7228a83 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/2] dt-bindings: phy-j721e-wiz: add j784s4 compatible string @ 2022-10-15 20:11 ` Matt Ranostay 0 siblings, 0 replies; 10+ messages in thread From: Matt Ranostay @ 2022-10-15 20:11 UTC (permalink / raw) To: vkoul, robh+dt, krzysztof.kozlowski+dt, vigneshr Cc: linux-phy, devicetree, Matt Ranostay Add ti,j784s4-wiz-10g compatible string to binding documentation. Signed-off-by: Matt Ranostay <mranostay@ti.com> --- Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 2225925b6dad..a9e38739c010 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -17,6 +17,7 @@ properties: - ti,j721e-wiz-10g - ti,am64-wiz-10g - ti,j7200-wiz-10g + - ti,j784s4-wiz-10g power-domains: maxItems: 1 -- 2.38.0.rc0.52.gdda7228a83 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] dt-bindings: phy-j721e-wiz: add j784s4 compatible string 2022-10-15 20:11 ` Matt Ranostay @ 2022-10-16 15:04 ` Krzysztof Kozlowski -1 siblings, 0 replies; 10+ messages in thread From: Krzysztof Kozlowski @ 2022-10-16 15:04 UTC (permalink / raw) To: Matt Ranostay, vkoul, robh+dt, krzysztof.kozlowski+dt, vigneshr Cc: linux-phy, devicetree On 15/10/2022 16:11, Matt Ranostay wrote: > Add ti,j784s4-wiz-10g compatible string to binding documentation. > > Signed-off-by: Matt Ranostay <mranostay@ti.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] dt-bindings: phy-j721e-wiz: add j784s4 compatible string @ 2022-10-16 15:04 ` Krzysztof Kozlowski 0 siblings, 0 replies; 10+ messages in thread From: Krzysztof Kozlowski @ 2022-10-16 15:04 UTC (permalink / raw) To: Matt Ranostay, vkoul, robh+dt, krzysztof.kozlowski+dt, vigneshr Cc: linux-phy, devicetree On 15/10/2022 16:11, Matt Ranostay wrote: > Add ti,j784s4-wiz-10g compatible string to binding documentation. > > Signed-off-by: Matt Ranostay <mranostay@ti.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/2] phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module support 2022-10-15 20:11 ` Matt Ranostay @ 2022-10-15 20:11 ` Matt Ranostay -1 siblings, 0 replies; 10+ messages in thread From: Matt Ranostay @ 2022-10-15 20:11 UTC (permalink / raw) To: vkoul, robh+dt, krzysztof.kozlowski+dt, vigneshr Cc: linux-phy, devicetree, Matt Ranostay, Roger Quadros Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Acked-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com> --- drivers/phy/ti/phy-j721e-wiz.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 41725c6bcdf6..141b51af4427 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -81,14 +81,20 @@ static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); static const struct reg_field pll1_refclk_mux_sel = REG_FIELD(WIZ_SERDES_RST, 29, 29); +static const struct reg_field pll1_refclk_mux_sel_2 = + REG_FIELD(WIZ_SERDES_RST, 22, 23); static const struct reg_field pll0_refclk_mux_sel = REG_FIELD(WIZ_SERDES_RST, 28, 28); +static const struct reg_field pll0_refclk_mux_sel_2 = + REG_FIELD(WIZ_SERDES_RST, 28, 29); static const struct reg_field refclk_dig_sel_16g = REG_FIELD(WIZ_SERDES_RST, 24, 25); static const struct reg_field refclk_dig_sel_10g = REG_FIELD(WIZ_SERDES_RST, 24, 24); static const struct reg_field pma_cmn_refclk_int_mode = REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); +static const struct reg_field pma_cmn_refclk1_int_mode = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21); static const struct reg_field pma_cmn_refclk_mode = REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); static const struct reg_field pma_cmn_refclk_dig_div = @@ -315,6 +321,7 @@ enum wiz_type { J721E_WIZ_10G, /* Also for J7200 SR1.0 */ AM64_WIZ_10G, J7200_WIZ_10G, /* J7200 SR2.0 */ + J784S4_WIZ_10G, }; struct wiz_data { @@ -992,6 +999,7 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) switch (wiz->type) { case AM64_WIZ_10G: case J7200_WIZ_10G: + case J784S4_WIZ_10G: of_clk_del_provider(dev->of_node); return; default: @@ -1123,6 +1131,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) switch (wiz->type) { case AM64_WIZ_10G: case J7200_WIZ_10G: + case J784S4_WIZ_10G: ret = wiz_clock_register(wiz); if (ret) dev_err(dev, "Failed to register wiz clocks\n"); @@ -1299,6 +1308,16 @@ static struct wiz_data j7200_pg2_10g_data = { .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, }; +static struct wiz_data j784s4_10g_data = { + .type = J784S4_WIZ_10G, + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2, + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2, + .refclk_dig_sel = &refclk_dig_sel_16g, + .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode, + .clk_mux_sel = clk_mux_sel_10g_2_refclk, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, +}; + static const struct of_device_id wiz_id_table[] = { { .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, @@ -1312,6 +1331,9 @@ static const struct of_device_id wiz_id_table[] = { { .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, }, + { + .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data, + }, {} }; MODULE_DEVICE_TABLE(of, wiz_id_table); -- 2.38.0.rc0.52.gdda7228a83 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module support @ 2022-10-15 20:11 ` Matt Ranostay 0 siblings, 0 replies; 10+ messages in thread From: Matt Ranostay @ 2022-10-15 20:11 UTC (permalink / raw) To: vkoul, robh+dt, krzysztof.kozlowski+dt, vigneshr Cc: linux-phy, devicetree, Matt Ranostay, Roger Quadros Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Acked-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com> --- drivers/phy/ti/phy-j721e-wiz.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 41725c6bcdf6..141b51af4427 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -81,14 +81,20 @@ static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); static const struct reg_field pll1_refclk_mux_sel = REG_FIELD(WIZ_SERDES_RST, 29, 29); +static const struct reg_field pll1_refclk_mux_sel_2 = + REG_FIELD(WIZ_SERDES_RST, 22, 23); static const struct reg_field pll0_refclk_mux_sel = REG_FIELD(WIZ_SERDES_RST, 28, 28); +static const struct reg_field pll0_refclk_mux_sel_2 = + REG_FIELD(WIZ_SERDES_RST, 28, 29); static const struct reg_field refclk_dig_sel_16g = REG_FIELD(WIZ_SERDES_RST, 24, 25); static const struct reg_field refclk_dig_sel_10g = REG_FIELD(WIZ_SERDES_RST, 24, 24); static const struct reg_field pma_cmn_refclk_int_mode = REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); +static const struct reg_field pma_cmn_refclk1_int_mode = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21); static const struct reg_field pma_cmn_refclk_mode = REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); static const struct reg_field pma_cmn_refclk_dig_div = @@ -315,6 +321,7 @@ enum wiz_type { J721E_WIZ_10G, /* Also for J7200 SR1.0 */ AM64_WIZ_10G, J7200_WIZ_10G, /* J7200 SR2.0 */ + J784S4_WIZ_10G, }; struct wiz_data { @@ -992,6 +999,7 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) switch (wiz->type) { case AM64_WIZ_10G: case J7200_WIZ_10G: + case J784S4_WIZ_10G: of_clk_del_provider(dev->of_node); return; default: @@ -1123,6 +1131,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) switch (wiz->type) { case AM64_WIZ_10G: case J7200_WIZ_10G: + case J784S4_WIZ_10G: ret = wiz_clock_register(wiz); if (ret) dev_err(dev, "Failed to register wiz clocks\n"); @@ -1299,6 +1308,16 @@ static struct wiz_data j7200_pg2_10g_data = { .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, }; +static struct wiz_data j784s4_10g_data = { + .type = J784S4_WIZ_10G, + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2, + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2, + .refclk_dig_sel = &refclk_dig_sel_16g, + .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode, + .clk_mux_sel = clk_mux_sel_10g_2_refclk, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, +}; + static const struct of_device_id wiz_id_table[] = { { .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, @@ -1312,6 +1331,9 @@ static const struct of_device_id wiz_id_table[] = { { .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, }, + { + .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data, + }, {} }; MODULE_DEVICE_TABLE(of, wiz_id_table); -- 2.38.0.rc0.52.gdda7228a83 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] phy: ti: phy-j721e-wiz: add j784s4 support 2022-10-15 20:11 ` Matt Ranostay @ 2022-10-17 5:29 ` Vinod Koul -1 siblings, 0 replies; 10+ messages in thread From: Vinod Koul @ 2022-10-17 5:29 UTC (permalink / raw) To: Matt Ranostay Cc: robh+dt, krzysztof.kozlowski+dt, vigneshr, linux-phy, devicetree On 15-10-22, 13:11, Matt Ranostay wrote: > WIZ modules for J784S4 platform have two input muxes which requires > additional mux sections options. Applied, thanks -- ~Vinod -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] phy: ti: phy-j721e-wiz: add j784s4 support @ 2022-10-17 5:29 ` Vinod Koul 0 siblings, 0 replies; 10+ messages in thread From: Vinod Koul @ 2022-10-17 5:29 UTC (permalink / raw) To: Matt Ranostay Cc: robh+dt, krzysztof.kozlowski+dt, vigneshr, linux-phy, devicetree On 15-10-22, 13:11, Matt Ranostay wrote: > WIZ modules for J784S4 platform have two input muxes which requires > additional mux sections options. Applied, thanks -- ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-10-17 5:29 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-10-15 20:11 [PATCH 0/2] phy: ti: phy-j721e-wiz: add j784s4 support Matt Ranostay 2022-10-15 20:11 ` Matt Ranostay 2022-10-15 20:11 ` [PATCH 1/2] dt-bindings: phy-j721e-wiz: add j784s4 compatible string Matt Ranostay 2022-10-15 20:11 ` Matt Ranostay 2022-10-16 15:04 ` Krzysztof Kozlowski 2022-10-16 15:04 ` Krzysztof Kozlowski 2022-10-15 20:11 ` [PATCH 2/2] phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module support Matt Ranostay 2022-10-15 20:11 ` Matt Ranostay 2022-10-17 5:29 ` [PATCH 0/2] phy: ti: phy-j721e-wiz: add j784s4 support Vinod Koul 2022-10-17 5:29 ` Vinod Koul
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