All of lore.kernel.org
 help / color / mirror / Atom feed
From: Matt Ranostay <mranostay@ti.com>
To: Jayesh Choudhary <j-choudhary@ti.com>
Cc: <nm@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
	<robh+dt@kernel.org>, <afd@ti.com>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator
Date: Mon, 31 Oct 2022 07:45:44 -0700	[thread overview]
Message-ID: <Y1/fmMRlsRkCS0z3@ubuntu> (raw)
In-Reply-To: <20221031135416.350010-1-j-choudhary@ti.com>

On Mon, Oct 31, 2022 at 07:24:16PM +0530, Jayesh Choudhary wrote:
> Add the node for SA2UL for supporting hardware crypto algorithms,
> including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites.
> Add rng node for hardware random number generator.
> 
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>

Acked-by: Matt Ranostay <mranostay@ti.com>

> ---
> 
> Changes have been tested on local j721s2-evm board. Tcrypt tests
> and crypto self-tests were passing.
> 
> Changelog v1 -> v2:
> - change the TI_SCI flag from shared to exclusive as OP-TEE uses MCU
>   domain SA2UL instance and not the main domain instance
> - remove the 'dma-coherent' property (Binding changes are merged)
> - add the rng node which can be used as well for hwrng along with
>   optee-rng
>   
> v1 patch: https://lore.kernel.org/all/20220628054518.350717-1-j-choudhary@ti.com/
> 
> Testing log: https://gist.github.com/Jayesh2000/26acf0e63f7edcd4b267122e4c73b9a8
> 
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index d1ec26110376..7b828afc9280 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -72,6 +72,26 @@ main_pmx0: pinctrl@11c000 {
>  		pinctrl-single,function-mask = <0xffffffff>;
>  	};
>  
> +	main_crypto: crypto@4e00000 {
> +		compatible = "ti,j721e-sa2ul";
> +		reg = <0x00 0x4e00000 0x00 0x1200>;
> +		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
> +
> +		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
> +				<&main_udmap 0x4a41>;
> +		dma-names = "tx", "rx1", "rx2";
> +
> +		rng: rng@4e10000 {
> +			compatible = "inside-secure,safexcel-eip76";
> +			reg = <0x0 0x4e10000 0x0 0x7d>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&k3_clks 297 1>;
> +		};
> +	};
> +
>  	main_uart0: serial@2800000 {
>  		compatible = "ti,j721e-uart", "ti,am654-uart";
>  		reg = <0x00 0x02800000 0x00 0x200>;
> -- 
> 2.25.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Matt Ranostay <mranostay@ti.com>
To: Jayesh Choudhary <j-choudhary@ti.com>
Cc: <nm@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
	<robh+dt@kernel.org>, <afd@ti.com>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator
Date: Mon, 31 Oct 2022 07:45:44 -0700	[thread overview]
Message-ID: <Y1/fmMRlsRkCS0z3@ubuntu> (raw)
In-Reply-To: <20221031135416.350010-1-j-choudhary@ti.com>

On Mon, Oct 31, 2022 at 07:24:16PM +0530, Jayesh Choudhary wrote:
> Add the node for SA2UL for supporting hardware crypto algorithms,
> including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites.
> Add rng node for hardware random number generator.
> 
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>

Acked-by: Matt Ranostay <mranostay@ti.com>

> ---
> 
> Changes have been tested on local j721s2-evm board. Tcrypt tests
> and crypto self-tests were passing.
> 
> Changelog v1 -> v2:
> - change the TI_SCI flag from shared to exclusive as OP-TEE uses MCU
>   domain SA2UL instance and not the main domain instance
> - remove the 'dma-coherent' property (Binding changes are merged)
> - add the rng node which can be used as well for hwrng along with
>   optee-rng
>   
> v1 patch: https://lore.kernel.org/all/20220628054518.350717-1-j-choudhary@ti.com/
> 
> Testing log: https://gist.github.com/Jayesh2000/26acf0e63f7edcd4b267122e4c73b9a8
> 
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index d1ec26110376..7b828afc9280 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -72,6 +72,26 @@ main_pmx0: pinctrl@11c000 {
>  		pinctrl-single,function-mask = <0xffffffff>;
>  	};
>  
> +	main_crypto: crypto@4e00000 {
> +		compatible = "ti,j721e-sa2ul";
> +		reg = <0x00 0x4e00000 0x00 0x1200>;
> +		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
> +
> +		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
> +				<&main_udmap 0x4a41>;
> +		dma-names = "tx", "rx1", "rx2";
> +
> +		rng: rng@4e10000 {
> +			compatible = "inside-secure,safexcel-eip76";
> +			reg = <0x0 0x4e10000 0x0 0x7d>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&k3_clks 297 1>;
> +		};
> +	};
> +
>  	main_uart0: serial@2800000 {
>  		compatible = "ti,j721e-uart", "ti,am654-uart";
>  		reg = <0x00 0x02800000 0x00 0x200>;
> -- 
> 2.25.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-10-31 14:47 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-31 13:54 [PATCH v2] arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator Jayesh Choudhary
2022-10-31 13:54 ` Jayesh Choudhary
2022-10-31 14:45 ` Matt Ranostay [this message]
2022-10-31 14:45   ` Matt Ranostay
2022-10-31 15:21 ` Andrew Davis
2022-10-31 15:21   ` Andrew Davis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=Y1/fmMRlsRkCS0z3@ubuntu \
    --to=mranostay@ti.com \
    --cc=afd@ti.com \
    --cc=devicetree@vger.kernel.org \
    --cc=j-choudhary@ti.com \
    --cc=kristo@kernel.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=nm@ti.com \
    --cc=robh+dt@kernel.org \
    --cc=vigneshr@ti.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.