From: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Peter Maydell <peter.maydell@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>,
Vincent Donnefort <vdonnefort@google.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Subject: Re: [PATCH v1 1/2] arm64: booting: Document our requirements for fine grained traps with SME
Date: Sun, 30 Oct 2022 17:40:54 +0000 [thread overview]
Message-ID: <Y163JlsMgmrNgZZb@arm.com> (raw)
In-Reply-To: <20221027210441.814061-2-broonie@kernel.org>
On Thu, Oct 27, 2022 at 10:04:39PM +0100, Mark Brown wrote:
> With SME we require that fine grained traps on access to TPIDR2_EL0 and
> SMPRI_EL1 are disabled but did not document that fact. Add the relevant
> register bits.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Peter Maydell <peter.maydell@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>,
Vincent Donnefort <vdonnefort@google.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Subject: Re: [PATCH v1 1/2] arm64: booting: Document our requirements for fine grained traps with SME
Date: Sun, 30 Oct 2022 17:40:54 +0000 [thread overview]
Message-ID: <Y163JlsMgmrNgZZb@arm.com> (raw)
In-Reply-To: <20221027210441.814061-2-broonie@kernel.org>
On Thu, Oct 27, 2022 at 10:04:39PM +0100, Mark Brown wrote:
> With SME we require that fine grained traps on access to TPIDR2_EL0 and
> SMPRI_EL1 are disabled but did not document that fact. Add the relevant
> register bits.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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next prev parent reply other threads:[~2022-10-30 17:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-27 21:04 [PATCH v1 0/2] arm64/sme: Fix SMPRI_EL1 traps for KVM guests Mark Brown
2022-10-27 21:04 ` Mark Brown
2022-10-27 21:04 ` [PATCH v1 1/2] arm64: booting: Document our requirements for fine grained traps with SME Mark Brown
2022-10-27 21:04 ` Mark Brown
2022-10-30 17:40 ` Catalin Marinas [this message]
2022-10-30 17:40 ` Catalin Marinas
2022-10-27 21:04 ` [PATCH v1 2/2] KVM: arm64: Trap access to SMPRI_EL1 in VHE mode Mark Brown
2022-10-27 21:04 ` Mark Brown
2022-10-31 9:45 ` Marc Zyngier
2022-10-31 9:45 ` Marc Zyngier
2022-10-31 12:41 ` Mark Brown
2022-10-31 12:41 ` Mark Brown
2022-10-28 0:38 ` [PATCH v1 0/2] arm64/sme: Fix SMPRI_EL1 traps for KVM guests Oliver Upton
2022-10-28 0:38 ` Oliver Upton
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