From: Richard Acayan <mailingradian@gmail.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Rob Clark <robdclark@gmail.com>, Vinod Koul <vkoul@kernel.org>,
Sai Prakash Ranjan <quic_saipraka@quicinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev,
devicetree@vger.kernel.org, freedreno@lists.freedesktop.org
Subject: Re: [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
Date: Fri, 4 Nov 2022 18:16:31 -0400 [thread overview]
Message-ID: <Y2WOwZdMLjByosel@mailingradian> (raw)
In-Reply-To: <20221102184420.534094-9-dmitry.baryshkov@linaro.org>
On Wed, Nov 02, 2022 at 09:44:17PM +0300, Dmitry Baryshkov wrote:
> There is only one platform, which needs special care in the reset
> function, the SDM845. Add special handler for sdm845 and drop the
> qcom_smmu500_reset() function.
>
> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
> 1 file changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index c3bcd6eb2f42..75bc770ccf8c 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> {
> int ret;
>
> + arm_mmu500_reset(smmu);
> +
> /*
> * To address performance degradation in non-real time clients,
> * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
> @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> return ret;
> }
>
> -static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> -{
> - const struct device_node *np = smmu->dev->of_node;
> -
> - arm_mmu500_reset(smmu);
> -
> - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
> - return qcom_sdm845_smmu500_reset(smmu);
> -
> - return 0;
> -}
> -
> static const struct arm_smmu_impl qcom_smmu_impl = {
> .init_context = qcom_smmu_init_context,
> .cfg_probe = qcom_smmu_cfg_probe,
> .def_domain_type = qcom_smmu_def_domain_type,
> - .reset = qcom_smmu500_reset,
> + .reset = arm_mmu500_reset,
> + .write_s2cr = qcom_smmu_write_s2cr,
> + .tlb_sync = qcom_smmu_tlb_sync,
> +};
> +
> +static const struct arm_smmu_impl sdm845_smmu_500_impl = {
> + .init_context = qcom_smmu_init_context,
> + .cfg_probe = qcom_smmu_cfg_probe,
> + .def_domain_type = qcom_smmu_def_domain_type,
> + .reset = qcom_sdm845_smmu500_reset,
> .write_s2cr = qcom_smmu_write_s2cr,
> .tlb_sync = qcom_smmu_tlb_sync,
> };
> @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
> static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
> .init_context = qcom_adreno_smmu_init_context,
> .def_domain_type = qcom_smmu_def_domain_type,
> - .reset = qcom_smmu500_reset,
> + .reset = arm_mmu500_reset,
> .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
> .write_sctlr = qcom_adreno_smmu_write_sctlr,
> .tlb_sync = qcom_smmu_tlb_sync,
> @@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
> .adreno_impl = &qcom_adreno_smmu_impl,
> };
>
> +static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
> + .impl = &sdm845_smmu_500_impl,
> + /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
separete -> separate
Also, while I'm here, does "No adreno impl" constitute adding a
compatible in the driver?
> +};
> +
> static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
> { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
> @@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
> + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
> { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
> --
> 2.35.1
>
WARNING: multiple messages have this Message-ID (diff)
From: Richard Acayan <mailingradian@gmail.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Rob Clark <robdclark@gmail.com>, Vinod Koul <vkoul@kernel.org>,
Sai Prakash Ranjan <quic_saipraka@quicinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev,
devicetree@vger.kernel.org, freedreno@lists.freedesktop.org
Subject: Re: [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
Date: Fri, 4 Nov 2022 18:16:31 -0400 [thread overview]
Message-ID: <Y2WOwZdMLjByosel@mailingradian> (raw)
In-Reply-To: <20221102184420.534094-9-dmitry.baryshkov@linaro.org>
On Wed, Nov 02, 2022 at 09:44:17PM +0300, Dmitry Baryshkov wrote:
> There is only one platform, which needs special care in the reset
> function, the SDM845. Add special handler for sdm845 and drop the
> qcom_smmu500_reset() function.
>
> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
> 1 file changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index c3bcd6eb2f42..75bc770ccf8c 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> {
> int ret;
>
> + arm_mmu500_reset(smmu);
> +
> /*
> * To address performance degradation in non-real time clients,
> * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
> @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> return ret;
> }
>
> -static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> -{
> - const struct device_node *np = smmu->dev->of_node;
> -
> - arm_mmu500_reset(smmu);
> -
> - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
> - return qcom_sdm845_smmu500_reset(smmu);
> -
> - return 0;
> -}
> -
> static const struct arm_smmu_impl qcom_smmu_impl = {
> .init_context = qcom_smmu_init_context,
> .cfg_probe = qcom_smmu_cfg_probe,
> .def_domain_type = qcom_smmu_def_domain_type,
> - .reset = qcom_smmu500_reset,
> + .reset = arm_mmu500_reset,
> + .write_s2cr = qcom_smmu_write_s2cr,
> + .tlb_sync = qcom_smmu_tlb_sync,
> +};
> +
> +static const struct arm_smmu_impl sdm845_smmu_500_impl = {
> + .init_context = qcom_smmu_init_context,
> + .cfg_probe = qcom_smmu_cfg_probe,
> + .def_domain_type = qcom_smmu_def_domain_type,
> + .reset = qcom_sdm845_smmu500_reset,
> .write_s2cr = qcom_smmu_write_s2cr,
> .tlb_sync = qcom_smmu_tlb_sync,
> };
> @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
> static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
> .init_context = qcom_adreno_smmu_init_context,
> .def_domain_type = qcom_smmu_def_domain_type,
> - .reset = qcom_smmu500_reset,
> + .reset = arm_mmu500_reset,
> .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
> .write_sctlr = qcom_adreno_smmu_write_sctlr,
> .tlb_sync = qcom_smmu_tlb_sync,
> @@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
> .adreno_impl = &qcom_adreno_smmu_impl,
> };
>
> +static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
> + .impl = &sdm845_smmu_500_impl,
> + /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
separete -> separate
Also, while I'm here, does "No adreno impl" constitute adding a
compatible in the driver?
> +};
> +
> static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
> { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
> @@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
> + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
> { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
> --
> 2.35.1
>
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next prev parent reply other threads:[~2022-11-04 22:16 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-02 18:44 [RFC PATCH v2 00/11] iommu/arm-smmu-qcom: Rework Qualcomm SMMU bindings and implementation Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 18:44 ` [RFC PATCH v2 01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 20:55 ` Krzysztof Kozlowski
2022-11-02 20:55 ` Krzysztof Kozlowski
2022-11-08 4:36 ` (subset) " Bjorn Andersson
2022-11-08 4:36 ` Bjorn Andersson
2022-11-02 18:44 ` [RFC PATCH v2 02/11] dt-bindings: arm-smmu: Add missing Qualcomm SMMU compatibles Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 18:44 ` [RFC PATCH v2 03/11] dt-bindings: arm-smmu: fix clocks/clock-names schema Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 20:56 ` Krzysztof Kozlowski
2022-11-02 20:56 ` Krzysztof Kozlowski
2022-11-02 20:56 ` Krzysztof Kozlowski
2022-11-02 20:56 ` Krzysztof Kozlowski
2022-11-02 18:44 ` [RFC PATCH v2 04/11] dt-bindings: arm-smmu: add special case for Google Cheza platform Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 20:59 ` Krzysztof Kozlowski
2022-11-02 20:59 ` Krzysztof Kozlowski
2022-11-02 18:44 ` [RFC PATCH v2 05/11] dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 18:44 ` [RFC PATCH v2 06/11] iommu/arm-smmu-qcom: Move implementation data into match data Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 18:44 ` [RFC PATCH v2 07/11] iommu/arm-smmu-qcom: Move the qcom,adreno-smmu check into qcom_smmu_create Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 18:44 ` [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500 Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-04 22:16 ` Richard Acayan [this message]
2022-11-04 22:16 ` Richard Acayan
2022-11-05 0:02 ` Dmitry Baryshkov
2022-11-05 0:02 ` Dmitry Baryshkov
2022-11-05 1:42 ` Richard Acayan
2022-11-05 1:42 ` Richard Acayan
2022-11-02 18:44 ` [RFC PATCH v2 09/11] iommu/arm-smmu-qcom: Merge table from arm-smmu-qcom-debug into match data Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 18:44 ` [RFC PATCH v2 10/11] iommu/arm-smmu-qcom: Stop using mmu500 reset for v2 MMUs Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-02 18:44 ` [RFC PATCH v2 11/11] iommu/arm-smmu-qcom: Add generic qcom,smmu-500 match entry Dmitry Baryshkov
2022-11-02 18:44 ` Dmitry Baryshkov
2022-11-14 14:23 ` [RFC PATCH v2 00/11] iommu/arm-smmu-qcom: Rework Qualcomm SMMU bindings and implementation Will Deacon
2022-11-14 14:23 ` Will Deacon
2022-11-14 17:07 ` Dmitry Baryshkov
2022-11-14 17:07 ` Dmitry Baryshkov
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