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From: Conor Dooley <conor@kernel.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: "Conor Dooley" <conor.dooley@microchip.com>,
	"Pierre Gondois" <pierre.gondois@arm.com>,
	linux-kernel@vger.kernel.org,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Gavin Shan" <gshan@redhat.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Jani Nikula" <jani.nikula@intel.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic OF implem
Date: Tue, 8 Nov 2022 17:21:04 +0000	[thread overview]
Message-ID: <Y2qQABd9Xsubx77Q@spud> (raw)
In-Reply-To: <20221108155906.3pssiipdfrm55q56@bogus>

On Tue, Nov 08, 2022 at 03:59:06PM +0000, Sudeep Holla wrote:
> On Tue, Nov 08, 2022 at 02:07:41PM +0000, Conor Dooley wrote:
> > On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > > Riscv's implementation of init_of_cache_level() is following
> > 
> > heh, "Riscv" always looks a bit odd!
> > Code movement looks fine, nothing surface level is broken on RISC-V.
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> >
> Thanks for the review and testing. I was planning to ask Pierre to cc you
> next time but you seem to have covered that for me :).

Ye no worries.
Feel free to add some sort of "R: Conor Dooley <conor@kernel.org>" entry
where appropriate if you want to make sure I'll take a look - but I
should see it anyway if it goes to the riscv list.
Up to you.


WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: "Conor Dooley" <conor.dooley@microchip.com>,
	"Pierre Gondois" <pierre.gondois@arm.com>,
	linux-kernel@vger.kernel.org,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Gavin Shan" <gshan@redhat.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Jani Nikula" <jani.nikula@intel.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic OF implem
Date: Tue, 8 Nov 2022 17:21:04 +0000	[thread overview]
Message-ID: <Y2qQABd9Xsubx77Q@spud> (raw)
In-Reply-To: <20221108155906.3pssiipdfrm55q56@bogus>

On Tue, Nov 08, 2022 at 03:59:06PM +0000, Sudeep Holla wrote:
> On Tue, Nov 08, 2022 at 02:07:41PM +0000, Conor Dooley wrote:
> > On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > > Riscv's implementation of init_of_cache_level() is following
> > 
> > heh, "Riscv" always looks a bit odd!
> > Code movement looks fine, nothing surface level is broken on RISC-V.
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> >
> Thanks for the review and testing. I was planning to ask Pierre to cc you
> next time but you seem to have covered that for me :).

Ye no worries.
Feel free to add some sort of "R: Conor Dooley <conor@kernel.org>" entry
where appropriate if you want to make sure I'll take a look - but I
should see it anyway if it goes to the riscv list.
Up to you.


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: "Conor Dooley" <conor.dooley@microchip.com>,
	"Pierre Gondois" <pierre.gondois@arm.com>,
	linux-kernel@vger.kernel.org,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Gavin Shan" <gshan@redhat.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Jani Nikula" <jani.nikula@intel.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic OF implem
Date: Tue, 8 Nov 2022 17:21:04 +0000	[thread overview]
Message-ID: <Y2qQABd9Xsubx77Q@spud> (raw)
In-Reply-To: <20221108155906.3pssiipdfrm55q56@bogus>

On Tue, Nov 08, 2022 at 03:59:06PM +0000, Sudeep Holla wrote:
> On Tue, Nov 08, 2022 at 02:07:41PM +0000, Conor Dooley wrote:
> > On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > > Riscv's implementation of init_of_cache_level() is following
> > 
> > heh, "Riscv" always looks a bit odd!
> > Code movement looks fine, nothing surface level is broken on RISC-V.
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> >
> Thanks for the review and testing. I was planning to ask Pierre to cc you
> next time but you seem to have covered that for me :).

Ye no worries.
Feel free to add some sort of "R: Conor Dooley <conor@kernel.org>" entry
where appropriate if you want to make sure I'll take a look - but I
should see it anyway if it goes to the riscv list.
Up to you.


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-11-08 17:21 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-08 11:04 [PATCH 0/5] arch_topology: Build cacheinfo from primary CPU Pierre Gondois
2022-11-08 11:04 ` Pierre Gondois
2022-11-08 11:04 ` Pierre Gondois
2022-11-08 11:04 ` [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic OF implem Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 14:07   ` Conor Dooley
2022-11-08 14:07     ` Conor Dooley
2022-11-08 14:07     ` Conor Dooley
2022-11-08 15:59     ` Sudeep Holla
2022-11-08 15:59       ` Sudeep Holla
2022-11-08 15:59       ` Sudeep Holla
2022-11-08 17:21       ` Conor Dooley [this message]
2022-11-08 17:21         ` Conor Dooley
2022-11-08 17:21         ` Conor Dooley
2022-11-08 16:03   ` Sudeep Holla
2022-11-08 16:03     ` Sudeep Holla
2022-11-08 16:03     ` Sudeep Holla
2022-11-08 16:08     ` Sudeep Holla
2022-11-08 16:08       ` Sudeep Holla
2022-11-08 16:08       ` Sudeep Holla
2022-11-08 11:04 ` [PATCH 2/5] cacheinfo: Return error code in init_of_cache_level() Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 16:05   ` Sudeep Holla
2022-11-08 16:05     ` Sudeep Holla
2022-11-08 16:05     ` Sudeep Holla
2022-11-08 11:04 ` [PATCH 3/5] ACPI: PPTT: Remove acpi_find_cache_levels() Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 16:13   ` Sudeep Holla
2022-11-08 16:13     ` Sudeep Holla
2022-11-08 16:13     ` Sudeep Holla
2022-11-08 16:56     ` Pierre Gondois
2022-11-08 16:56       ` Pierre Gondois
2022-11-08 16:56       ` Pierre Gondois
2022-11-10 23:17   ` Jeremy Linton
2022-11-10 23:17     ` Jeremy Linton
2022-11-10 23:17     ` Jeremy Linton
2022-11-08 11:04 ` [PATCH 4/5] ACPI: PPTT: Update acpi_find_last_cache_level() to acpi_get_cache_info() Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-10 23:13   ` Jeremy Linton
2022-11-10 23:13     ` Jeremy Linton
2022-11-10 23:13     ` Jeremy Linton
2022-11-08 11:04 ` [PATCH 5/5] arch_topology: Build cacheinfo from primary CPU Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 11:04   ` Pierre Gondois
2022-11-08 17:17   ` kernel test robot
2022-11-08 17:17     ` kernel test robot
2022-11-08 11:11 ` [PATCH 0/5] " Pierre Gondois
2022-11-08 11:11   ` Pierre Gondois
2022-11-08 11:11   ` Pierre Gondois
2022-11-08 14:04 ` Conor Dooley
2022-11-08 14:04   ` Conor Dooley
2022-11-08 14:04   ` Conor Dooley

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