[PULL 0/2] target-arm queue for rc1

[PULL 0/2] target-arm queue for rc1

[Peter Maydell]

Hi; here's the arm pullreq for rc1. Just one bugfix and
a MAINTAINERS file update...

thanks
-- PMM

The following changes since commit 305f6f62d9d250a32cdf090ddcb7e3a5b26a342e:

  Merge tag 'pull-la-20221112' of https://gitlab.com/rth7680/qemu into staging (2022-11-12 09:17:06 -0500)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221114

for you to fetch changes up to d9721f19cd05a382f4f5a7093c80d1c4a8a1aa82:

  hw/intc/arm_gicv3: fix prio masking on pmr write (2022-11-14 15:10:58 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/intc/arm_gicv3: fix prio masking on pmr write
 * MAINTAINERS: Update maintainer's email for Xilinx CAN

----------------------------------------------------------------
Jens Wiklander (1):
      hw/intc/arm_gicv3: fix prio masking on pmr write

Vikram Garhwal (1):
      MAINTAINERS: Update maintainer's email for Xilinx CAN

 hw/intc/arm_gicv3_cpuif.c | 3 +--
 MAINTAINERS               | 4 ++--
 2 files changed, 3 insertions(+), 4 deletions(-)

[PULL 1/2] MAINTAINERS: Update maintainer's email for Xilinx CAN

[Peter Maydell]

From: Vikram Garhwal <vikram.garhwal@amd.com>

Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index caba73ec41b..be151f00246 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1748,8 +1748,8 @@ F: tests/qtest/intel-hda-test.c
 F: tests/qtest/fuzz-sb16-test.c
 
 Xilinx CAN
-M: Vikram Garhwal <fnu.vikram@xilinx.com>
-M: Francisco Iglesias <francisco.iglesias@xilinx.com>
+M: Vikram Garhwal <vikram.garhwal@amd.com>
+M: Francisco Iglesias <francisco.iglesias@amd.com>
 S: Maintained
 F: hw/net/can/xlnx-*
 F: include/hw/net/xlnx-*
-- 
2.25.1

[PULL 2/2] hw/intc/arm_gicv3: fix prio masking on pmr write

[Peter Maydell]

From: Jens Wiklander <jens.wiklander@linaro.org>

With commit 39f29e599355 ("hw/intc/arm_gicv3: Use correct number of
priority bits for the CPU") the number of priority bits was changed from
the maximum value 8 to typically 5. As a consequence a few of the lowest
bits in ICC_PMR_EL1 becomes RAZ/WI. However prior to this patch one of
these bits was still used since the supplied priority value is masked
before it's eventually right shifted with one bit. So the bit is not
lost as one might expect when the register is read again.

The Linux kernel depends on lowest valid bit to be reset to zero, see
commit 33625282adaa ("irqchip/gic-v3: Probe for SCR_EL3 being clear
before resetting AP0Rn") for details.

So fix this by masking the priority value after it may have been right
shifted by one bit.

Cc: qemu-stable@nongnu.org
Fixes: 39f29e599355 ("hw/intc/arm_gicv3: Use correct number of priority bits for the CPU")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 8ca630e5ad1..b17b29288c7 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -1016,8 +1016,6 @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value);
 
-    value &= icc_fullprio_mask(cs);
-
     if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
         (env->cp15.scr_el3 & SCR_FIQ)) {
         /* NS access and Group 0 is inaccessible to NS: return the
@@ -1029,6 +1027,7 @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         }
         value = (value >> 1) | 0x80;
     }
+    value &= icc_fullprio_mask(cs);
     cs->icc_pmr_el1 = value;
     gicv3_cpuif_update(cs);
 }
-- 
2.25.1

Re: [PULL 0/2] target-arm queue for rc1

[Stefan Hajnoczi]

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On Mon, Nov 14, 2022 at 03:51:59PM +0000, Peter Maydell wrote:
> Hi; here's the arm pullreq for rc1. Just one bugfix and
> a MAINTAINERS file update...
> 
> thanks
> -- PMM
> 
> The following changes since commit 305f6f62d9d250a32cdf090ddcb7e3a5b26a342e:
> 
>   Merge tag 'pull-la-20221112' of https://gitlab.com/rth7680/qemu into staging (2022-11-12 09:17:06 -0500)
> 
> are available in the Git repository at:
> 
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221114
> 
> for you to fetch changes up to d9721f19cd05a382f4f5a7093c80d1c4a8a1aa82:
> 
>   hw/intc/arm_gicv3: fix prio masking on pmr write (2022-11-14 15:10:58 +0000)

Applied, thanks!

Stefan

> 
> ----------------------------------------------------------------
> target-arm queue:
>  * hw/intc/arm_gicv3: fix prio masking on pmr write
>  * MAINTAINERS: Update maintainer's email for Xilinx CAN
> 
> ----------------------------------------------------------------
> Jens Wiklander (1):
>       hw/intc/arm_gicv3: fix prio masking on pmr write
> 
> Vikram Garhwal (1):
>       MAINTAINERS: Update maintainer's email for Xilinx CAN
> 
>  hw/intc/arm_gicv3_cpuif.c | 3 +--
>  MAINTAINERS               | 4 ++--
>  2 files changed, 3 insertions(+), 4 deletions(-)
> 

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