From: Catalin Marinas <catalin.marinas@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, will@kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
Mark Rutland <mark.rutland@arm.com>,
linux-doc@vger.kernel.org
Subject: Re: [PATCH V2 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption
Date: Tue, 15 Nov 2022 14:02:00 +0000 [thread overview]
Message-ID: <Y3Ob2MmmuoXOs2In@arm.com> (raw)
In-Reply-To: <20221113012645.190301-3-anshuman.khandual@arm.com>
On Sun, Nov 13, 2022 at 06:56:45AM +0530, Anshuman Khandual wrote:
> diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
> index 35e9a468d13e..6552947ca7fa 100644
> --- a/arch/arm64/mm/hugetlbpage.c
> +++ b/arch/arm64/mm/hugetlbpage.c
> @@ -559,3 +559,24 @@ bool __init arch_hugetlb_valid_size(unsigned long size)
> {
> return __hugetlb_valid_size(size);
> }
> +
> +pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
> +{
> + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) {
> + pte_t pte = READ_ONCE(*ptep);
Not sure whether the generated code would be any different but we should
probably add the check for the CPU capability in the 'if' condition
above, before the READ_ONCE (which expands to some asm volatile):
if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198) &&
cpus_have_const_cap(ARM64_WORKAROUND_2645198)) {
pte_t pte = ...
...
}
> + /*
> + * Break-before-make (BBM) is required for all user space mappings
> + * when the permission changes from executable to non-executable
> + * in cases where cpu is affected with errata #2645198.
> + */
> + if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198))
> + return huge_ptep_clear_flush(vma, addr, ptep);
> + }
> + return huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
> +}
> +
> +void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
> + pte_t old_pte, pte_t pte)
> +{
> + set_huge_pte_at(vma->vm_mm, addr, ptep, pte);
> +}
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index 9a7c38965154..c1fb0ce1473c 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -1702,3 +1702,24 @@ static int __init prevent_bootmem_remove_init(void)
> }
> early_initcall(prevent_bootmem_remove_init);
> #endif
> +
> +pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
> +{
> + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) {
> + pte_t pte = READ_ONCE(*ptep);
> + /*
> + * Break-before-make (BBM) is required for all user space mappings
> + * when the permission changes from executable to non-executable
> + * in cases where cpu is affected with errata #2645198.
> + */
> + if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198))
> + return ptep_clear_flush(vma, addr, ptep);
> + }
Same here.
> + return ptep_get_and_clear(vma->vm_mm, addr, ptep);
> +}
> +
> +void ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
> + pte_t old_pte, pte_t pte)
> +{
> + __set_pte_at(vma->vm_mm, addr, ptep, pte);
> +}
--
Catalin
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, will@kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
Mark Rutland <mark.rutland@arm.com>,
linux-doc@vger.kernel.org
Subject: Re: [PATCH V2 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption
Date: Tue, 15 Nov 2022 14:02:00 +0000 [thread overview]
Message-ID: <Y3Ob2MmmuoXOs2In@arm.com> (raw)
In-Reply-To: <20221113012645.190301-3-anshuman.khandual@arm.com>
On Sun, Nov 13, 2022 at 06:56:45AM +0530, Anshuman Khandual wrote:
> diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
> index 35e9a468d13e..6552947ca7fa 100644
> --- a/arch/arm64/mm/hugetlbpage.c
> +++ b/arch/arm64/mm/hugetlbpage.c
> @@ -559,3 +559,24 @@ bool __init arch_hugetlb_valid_size(unsigned long size)
> {
> return __hugetlb_valid_size(size);
> }
> +
> +pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
> +{
> + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) {
> + pte_t pte = READ_ONCE(*ptep);
Not sure whether the generated code would be any different but we should
probably add the check for the CPU capability in the 'if' condition
above, before the READ_ONCE (which expands to some asm volatile):
if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198) &&
cpus_have_const_cap(ARM64_WORKAROUND_2645198)) {
pte_t pte = ...
...
}
> + /*
> + * Break-before-make (BBM) is required for all user space mappings
> + * when the permission changes from executable to non-executable
> + * in cases where cpu is affected with errata #2645198.
> + */
> + if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198))
> + return huge_ptep_clear_flush(vma, addr, ptep);
> + }
> + return huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
> +}
> +
> +void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
> + pte_t old_pte, pte_t pte)
> +{
> + set_huge_pte_at(vma->vm_mm, addr, ptep, pte);
> +}
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index 9a7c38965154..c1fb0ce1473c 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -1702,3 +1702,24 @@ static int __init prevent_bootmem_remove_init(void)
> }
> early_initcall(prevent_bootmem_remove_init);
> #endif
> +
> +pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
> +{
> + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) {
> + pte_t pte = READ_ONCE(*ptep);
> + /*
> + * Break-before-make (BBM) is required for all user space mappings
> + * when the permission changes from executable to non-executable
> + * in cases where cpu is affected with errata #2645198.
> + */
> + if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198))
> + return ptep_clear_flush(vma, addr, ptep);
> + }
Same here.
> + return ptep_get_and_clear(vma->vm_mm, addr, ptep);
> +}
> +
> +void ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
> + pte_t old_pte, pte_t pte)
> +{
> + __set_pte_at(vma->vm_mm, addr, ptep, pte);
> +}
--
Catalin
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next prev parent reply other threads:[~2022-11-15 14:02 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-13 1:26 [PATCH V2 0/2] arm64: errata: Workaround Cortex-A715 errata #2645198 Anshuman Khandual
2022-11-13 1:26 ` Anshuman Khandual
2022-11-13 1:26 ` [PATCH V2 1/2] arm64: Add Cortex-715 CPU part definition Anshuman Khandual
2022-11-13 1:26 ` Anshuman Khandual
2022-11-15 13:51 ` Catalin Marinas
2022-11-15 13:51 ` Catalin Marinas
2022-11-13 1:26 ` [PATCH V2 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption Anshuman Khandual
2022-11-13 1:26 ` Anshuman Khandual
2022-11-15 13:38 ` Will Deacon
2022-11-15 13:38 ` Will Deacon
2022-11-15 13:42 ` Will Deacon
2022-11-15 13:42 ` Will Deacon
2022-11-16 5:49 ` Anshuman Khandual
2022-11-16 5:49 ` Anshuman Khandual
2022-11-15 14:02 ` Catalin Marinas [this message]
2022-11-15 14:02 ` Catalin Marinas
2022-11-16 4:42 ` Anshuman Khandual
2022-11-16 4:42 ` Anshuman Khandual
2022-11-16 9:00 ` Catalin Marinas
2022-11-16 9:00 ` Catalin Marinas
2022-11-16 5:04 ` Anshuman Khandual
2022-11-16 5:04 ` Anshuman Khandual
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