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From: Conor Dooley <conor@kernel.org>
To: Vineet Gupta <vineetg@rivosinc.com>
Cc: Conor.Dooley@microchip.com, bjorn@kernel.org,
	stillson@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, vincent.chen@sifive.com,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, guoren@kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	ajones@ventanamicro.com
Subject: Re: [PATCH v12 04/17] riscv: Add vector feature to compile
Date: Tue, 15 Nov 2022 22:17:27 +0000	[thread overview]
Message-ID: <Y3QP9zjM3a4yifvi@spud> (raw)
In-Reply-To: <9cda597c-1d31-4b8b-99ba-deab58975976@rivosinc.com>

On Tue, Nov 15, 2022 at 09:38:53AM -0800, Vineet Gupta wrote:
> On 11/13/22 08:16, Conor.Dooley@microchip.com wrote:
> > > > +config VECTOR
> > > > +     bool "VECTOR support"
> > > > +     depends on GCC_VERSION >= 120000 || CLANG_VERSION >= 130000
> > > > +     default n
> > > > +     help
> > > > +       Say N here if you want to disable all vector related procedure
> > > > +       in the kernel.
> > > > +
> > > > +       If you don't know what to do here, say Y.
> > > > +
> > > > +endmenu
> > > "VECTOR" is not really consistent to how the other configs are named;
> > > RISCV_ISA_V, RISCV_ISA_VECTOR, RISCV_VECTOR?
> > It'd be RISCV_ISA_V to match the others single letter extentions, right?
> 
> Yep.
> 
> > The toolchain dependency check here also seems rather naive.
> 
> Indeed. I can build the code just fine with gcc-11 (and gcc-12), although my
> reworked patcheset doesn't include all the orig patches including the
> in-kernel xor stuff.

By naive here I meant that checking cc alone is probably not a
sufficient check for whether the toolchain supports the extension.
What about the assembler etc?

With Zicbom and Zihintpause we ran into problems with mixed usage, eg
binutils 2.35 + gcc 12. In his Zicboz series Drew has gone with insn
definitions - but while that's okay for something small like Zicboz,
do we want to do that for something with as many instructions as vector?

The alternative is cc-option, but that feels a lot less clean than what
Drew cooked up here:
https://lore.kernel.org/linux-riscv/20221027130247.31634-1-ajones@ventanamicro.com/

I've not checked this because I am lazy, but I am also assuming that
whoever put clang-13 in there picked it such that it doesn't require
experimental extensions flags. Mostly just writing this to remind myself
to check it at some point.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Vineet Gupta <vineetg@rivosinc.com>
Cc: Conor.Dooley@microchip.com, bjorn@kernel.org,
	stillson@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, vincent.chen@sifive.com,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, guoren@kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	ajones@ventanamicro.com
Subject: Re: [PATCH v12 04/17] riscv: Add vector feature to compile
Date: Tue, 15 Nov 2022 22:17:27 +0000	[thread overview]
Message-ID: <Y3QP9zjM3a4yifvi@spud> (raw)
In-Reply-To: <9cda597c-1d31-4b8b-99ba-deab58975976@rivosinc.com>

On Tue, Nov 15, 2022 at 09:38:53AM -0800, Vineet Gupta wrote:
> On 11/13/22 08:16, Conor.Dooley@microchip.com wrote:
> > > > +config VECTOR
> > > > +     bool "VECTOR support"
> > > > +     depends on GCC_VERSION >= 120000 || CLANG_VERSION >= 130000
> > > > +     default n
> > > > +     help
> > > > +       Say N here if you want to disable all vector related procedure
> > > > +       in the kernel.
> > > > +
> > > > +       If you don't know what to do here, say Y.
> > > > +
> > > > +endmenu
> > > "VECTOR" is not really consistent to how the other configs are named;
> > > RISCV_ISA_V, RISCV_ISA_VECTOR, RISCV_VECTOR?
> > It'd be RISCV_ISA_V to match the others single letter extentions, right?
> 
> Yep.
> 
> > The toolchain dependency check here also seems rather naive.
> 
> Indeed. I can build the code just fine with gcc-11 (and gcc-12), although my
> reworked patcheset doesn't include all the orig patches including the
> in-kernel xor stuff.

By naive here I meant that checking cc alone is probably not a
sufficient check for whether the toolchain supports the extension.
What about the assembler etc?

With Zicbom and Zihintpause we ran into problems with mixed usage, eg
binutils 2.35 + gcc 12. In his Zicboz series Drew has gone with insn
definitions - but while that's okay for something small like Zicboz,
do we want to do that for something with as many instructions as vector?

The alternative is cc-option, but that feels a lot less clean than what
Drew cooked up here:
https://lore.kernel.org/linux-riscv/20221027130247.31634-1-ajones@ventanamicro.com/

I've not checked this because I am lazy, but I am also assuming that
whoever put clang-13 in there picked it such that it doesn't require
experimental extensions flags. Mostly just writing this to remind myself
to check it at some point.

  reply	other threads:[~2022-11-15 22:17 UTC|newest]

Thread overview: 168+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-21 21:43 [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
     [not found]   ` <4b6e20fb-d013-0a09-0b74-b6c46e045af3@rivosinc.com>
     [not found]     ` <CAJF2gTSPoKu_owEb6+MLhAgK5nz2FTRDkTn4qfXF4KyA-XTwvw@mail.gmail.com>
     [not found]       ` <CAJF2gTT_z96V3kjPtr9hpTq8XRn0x=91wFNPYFFdetAA2u-01Q@mail.gmail.com>
2022-11-04  9:13         ` Conor.Dooley
2022-11-04 18:04           ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 03/17] riscv: Add new csr defines related to vector extension Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2023-01-23 11:24   ` Heiko Stübner
2023-01-23 11:24     ` Heiko Stübner
2023-01-23 11:24     ` Heiko Stübner
2022-09-21 21:43 ` [PATCH v12 04/17] riscv: Add vector feature to compile Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-07 17:21   ` Björn Töpel
2022-11-07 17:21     ` Björn Töpel
2022-11-08  0:04     ` Vineet Gupta
2022-11-08  0:04       ` Vineet Gupta
2022-11-08  7:56       ` Conor Dooley
2022-11-08  7:56         ` Conor Dooley
2022-11-08 17:17         ` Vineet Gupta
2022-11-08 17:17           ` Vineet Gupta
2022-11-08 17:22           ` Conor Dooley
2022-11-08 17:22             ` Conor Dooley
2022-11-13 16:16     ` Conor.Dooley
2022-11-13 16:16       ` Conor.Dooley
2022-11-15 17:38       ` Vineet Gupta
2022-11-15 17:38         ` Vineet Gupta
2022-11-15 22:17         ` Conor Dooley [this message]
2022-11-15 22:17           ` Conor Dooley
2022-12-15  0:40   ` Atish Patra
2022-12-15  0:40     ` Atish Patra
2022-12-15  0:40     ` Atish Patra
2022-09-21 21:43 ` [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save vector features Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-22  4:23   ` Samuel Holland
2022-09-22  4:23     ` Samuel Holland
2022-09-23 16:27     ` Chris Stillson
2022-09-23 16:27       ` Chris Stillson
2022-09-24 18:01       ` Conor Dooley
2022-09-24 18:01         ` Conor Dooley
2022-11-04  4:10   ` Vineet Gupta
2022-11-04  4:10     ` Vineet Gupta
2022-11-04  4:33   ` Vineet Gupta
2022-11-04  4:33     ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 06/17] riscv: Reset vector register Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-04  5:01   ` Vineet Gupta
2022-11-04  5:01     ` Vineet Gupta
2022-11-04  8:45     ` Guo Ren
2022-11-04  8:45       ` Guo Ren
2023-01-20 12:20   ` Heiko Stübner
2023-01-20 12:20     ` Heiko Stübner
2023-01-20 12:20     ` Heiko Stübner
2022-09-21 21:43 ` [PATCH v12 07/17] riscv: Add vector struct and assembler definitions Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-04  5:13   ` Vineet Gupta
2022-11-04  5:13     ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 08/17] riscv: Add task switch support for vector Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-04 22:08   ` Vineet Gupta
2022-11-04 22:08     ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 09/17] riscv: Add ptrace vector support Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-08  1:38   ` Vineet Gupta
2022-11-08  1:38     ` Vineet Gupta
2022-11-14 20:01     ` Arnd Bergmann
2022-11-14 20:01       ` Arnd Bergmann
2022-09-21 21:43 ` [PATCH v12 10/17] riscv: Add sigcontext save/restore for vector Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-09  1:27   ` Vineet Gupta
2022-11-09  1:27     ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 11/17] riscv: signal: Report signal frame size to userspace via auxv Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 12/17] riscv: Add support for kernel mode vector Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 13/17] riscv: Add vector extension XOR implementation Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 16/17] riscv: KVM: Add vector lazy save/restore support Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 17/17] riscv: prctl to enable vector commands Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-12-09  5:16   ` RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands) Vineet Gupta
2022-12-09  5:16     ` Vineet Gupta
2022-12-09  6:27     ` Palmer Dabbelt
2022-12-09  6:27       ` Palmer Dabbelt
2022-12-09  7:42       ` Andrew Waterman
2022-12-09  7:42         ` Andrew Waterman
2022-12-09 10:02         ` Florian Weimer
2022-12-09 10:02           ` Florian Weimer
2022-12-09 12:21           ` Darius Rad
2022-12-09 12:21             ` Darius Rad
2022-12-09 12:32             ` Florian Weimer
2022-12-09 12:32               ` Florian Weimer
2022-12-09 12:42               ` Darius Rad
2022-12-09 12:42                 ` Darius Rad
2022-12-09 13:04                 ` Florian Weimer
2022-12-09 13:04                   ` Florian Weimer
2022-12-09 17:21                   ` Palmer Dabbelt
2022-12-09 17:21                     ` Palmer Dabbelt
2022-12-09 19:42                     ` Vineet Gupta
2022-12-09 19:42                       ` Vineet Gupta
2022-12-09 19:58                       ` Andrew Waterman
2022-12-09 19:58                         ` Andrew Waterman
2022-12-13 16:43                       ` Darius Rad
2022-12-13 16:43                         ` Darius Rad
2022-12-14 20:07                         ` Vineet Gupta
2022-12-14 20:07                           ` Vineet Gupta
2022-12-14 23:13                           ` Samuel Holland
2022-12-14 23:13                             ` Samuel Holland
2022-12-15  2:09                           ` Darius Rad
2022-12-15  2:09                             ` Darius Rad
2022-12-15 11:48                             ` Björn Töpel
2022-12-15 11:48                               ` Björn Töpel
2022-12-15 12:28                               ` Florian Weimer
2022-12-15 12:28                                 ` Florian Weimer
2022-12-15 15:33                                 ` Richard Henderson
2022-12-15 15:33                                   ` Richard Henderson
2022-12-15 18:57                                   ` Vineet Gupta
2022-12-15 18:57                                     ` Vineet Gupta
2022-12-15 18:59                                     ` Andrew Pinski
2022-12-15 18:59                                       ` Andrew Pinski
2022-12-15 19:01                                       ` Andrew Pinski
2022-12-15 19:01                                         ` Andrew Pinski
2022-12-15 19:56                                     ` Richard Henderson
2022-12-15 19:56                                       ` Richard Henderson
2022-12-09 13:58       ` Icenowy Zheng
2022-12-09 13:58         ` Icenowy Zheng
2023-01-23 11:20 ` [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Heiko Stübner
2023-01-23 11:20   ` Heiko Stübner
2023-01-23 11:20   ` Heiko Stübner

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