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From: Klaus Jensen <its@irrelevant.dk>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-devel@nongnu.org, Andrew Jeffery <andrew@aj.id.au>,
	Keith Busch <kbusch@kernel.org>,
	Corey Minyard <cminyard@mvista.com>,
	Peter Delevoryas <peter@pjd.dev>,
	qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
	qemu-block@nongnu.org, Jeremy Kerr <jk@codeconstruct.com.au>,
	Joel Stanley <joel@jms.id.au>,
	Klaus Jensen <k.jensen@samsung.com>
Subject: Re: [PATCH maybe-7.2 1/3] hw/i2c: only schedule pending master when bus is idle
Date: Thu, 17 Nov 2022 07:40:49 +0100	[thread overview]
Message-ID: <Y3XXcWUnntBrIXq+@cormorant.local> (raw)
In-Reply-To: <8dd9ed34-93c3-0638-e152-f619f9e097e6@kaod.org>

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On Nov 16 16:58, Cédric Le Goater wrote:
> On 11/16/22 09:43, Klaus Jensen wrote:
> > From: Klaus Jensen <k.jensen@samsung.com>
> > 
> > It is not given that the current master will release the bus after a
> > transfer ends. Only schedule a pending master if the bus is idle.
> > 
> > Fixes: 37fa5ca42623 ("hw/i2c: support multiple masters")
> > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> > ---
> >   hw/i2c/aspeed_i2c.c  |  2 ++
> >   hw/i2c/core.c        | 37 ++++++++++++++++++++++---------------
> >   include/hw/i2c/i2c.h |  2 ++
> >   3 files changed, 26 insertions(+), 15 deletions(-)
> > 
> > diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
> > index c166fd20fa11..1f071a3811f7 100644
> > --- a/hw/i2c/aspeed_i2c.c
> > +++ b/hw/i2c/aspeed_i2c.c
> > @@ -550,6 +550,8 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
> >           }
> >           SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0);
> >           aspeed_i2c_set_state(bus, I2CD_IDLE);
> > +
> > +        i2c_schedule_pending_master(bus->bus);
> 
> Shouldn't it be i2c_bus_release() ?
> 

The reason for having both i2c_bus_release() and
i2c_schedule_pending_master() is that i2c_bus_release() sort of pairs
with i2c_bus_master(). They either set or clear the bus->bh member.

In the current design, the controller (in this case the Aspeed I2C) is
an "implicit" master (it does not have a bottom half driving it), so
there is no bus->bh to clear.

I should (and will) write some documentation on the asynchronous API.

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  reply	other threads:[~2022-11-17  6:41 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-16  8:43 [PATCH 0/3] hw/{i2c, nvme}: mctp endpoint, nvme management interface model Klaus Jensen
2022-11-16  8:43 ` [PATCH maybe-7.2 1/3] hw/i2c: only schedule pending master when bus is idle Klaus Jensen
2022-11-16 13:16   ` Peter Maydell
2022-11-16 13:43   ` Corey Minyard
2022-11-16 15:58   ` Cédric Le Goater
2022-11-17  6:40     ` Klaus Jensen [this message]
2022-11-17  6:56       ` Cédric Le Goater
2022-11-17  7:37         ` Klaus Jensen
2022-11-17  8:01           ` Cédric Le Goater
2022-11-17 11:58             ` Klaus Jensen
2022-11-17 13:40               ` Cédric Le Goater
2022-11-18  6:59                 ` Klaus Jensen
2022-11-22  8:45                 ` Klaus Jensen
2022-11-16  8:43 ` [PATCH RFC 2/3] hw/i2c: add mctp core Klaus Jensen
2022-11-16 14:27   ` Corey Minyard
2022-11-17  6:51     ` Klaus Jensen
2022-11-18  5:56   ` Jeremy Kerr
2022-11-18  6:15     ` Jeremy Kerr
2022-11-18  7:03       ` Klaus Jensen
2022-11-18  7:09         ` Jeremy Kerr
2022-11-18  7:01     ` Klaus Jensen
2022-11-21  8:04       ` Matt Johnston
2022-11-16  8:43 ` [PATCH RFC 3/3] hw/nvme: add nvme management interface model Klaus Jensen
2022-11-18  7:56   ` Philippe Mathieu-Daudé
2022-11-18  7:58     ` Klaus Jensen
2022-11-16  9:18 ` [PATCH 0/3] hw/{i2c,nvme}: mctp endpoint, " Jeremy Kerr

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