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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Andrew Cooper <Andrew.Cooper3@citrix.com>
Cc: Jan Beulich <jbeulich@suse.com>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	Wei Liu <wl@xen.org>, Paul Durrant <paul@xen.org>
Subject: Re: [PATCH] x86/HVM: don't mark evtchn upcall vector as pending when vLAPIC is disabled
Date: Fri, 18 Nov 2022 13:51:56 +0100	[thread overview]
Message-ID: <Y3d/7Dv6JmVTpEY1@Air-de-Roger> (raw)
In-Reply-To: <eebc4393-c322-0a2e-f600-18d384fe2647@citrix.com>

On Fri, Nov 18, 2022 at 12:33:00PM +0000, Andrew Cooper wrote:
> On 18/11/2022 10:31, Jan Beulich wrote:
> > Linux'es relatively new use of HVMOP_set_evtchn_upcall_vector has
> > exposed a problem with the marking of the respective vector as
> > pending: For quite some time Linux has been checking whether any stale
> > ISR or IRR bits would still be set while preparing the LAPIC for use.
> > This check is now triggering on the upcall vector, as the registration,
> > at least for APs, happens before the LAPIC is actually enabled.
> >
> > In software-disabled state an LAPIC would not accept any interrupt
> > requests and hence no IRR bit would newly become set while in this
> > state. As a result it is also wrong for us to mark the upcall vector as
> > having a pending request when the vLAPIC is in this state.
> 
> I agree with this.
> 
> > To compensate for the "enabled" check added to the assertion logic, add
> > logic to (conditionally) mark the upcall vector as having a request
> > pending at the time the LAPIC is being software-enabled by the guest.
> 
> But this, I don't think is appropriate.
> 
> The point of raising on enable is allegedly to work around setup race
> conditions.  I'm unconvinced by this reasoning, but it is what it is,
> and the stated behaviour is to raise there and then.
> 
> If a guest enables evtchn while the LAPIC is disabled, then the
> interrupt is lost.  Like every other interrupt in an x86 system.
> 
> I don't think there is any credible way a guest kernel author can expect
> the weird evtchn edgecase to wait for an arbitrary point in the future,
> and it's a corner case that I think is worth not keeping.

We would then need some kind of fix in order to clear
evtchn_upcall_pending, because having that set without an interrupt
pending on the vLAPIC will result in no further event channel callback
interrupts being injected (see vcpu_mark_events_pending()).

Maybe we want to change vcpu_mark_events_pending() so that it always
tries to inject the vector even if evtchn_upcall_pending is already
set by calling hvm_assert_evtchn_irq() unconditionally?

Thanks, Roger.


  reply	other threads:[~2022-11-18 12:52 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-18 10:31 [PATCH] x86/HVM: don't mark evtchn upcall vector as pending when vLAPIC is disabled Jan Beulich
2022-11-18 12:31 ` Juergen Gross
2022-11-18 12:33 ` Andrew Cooper
2022-11-18 12:51   ` Roger Pau Monné [this message]
2022-11-18 12:54   ` Jan Beulich
2022-11-18 13:55     ` Roger Pau Monné
2022-11-18 13:58       ` Jan Beulich
2022-11-18 14:09         ` Roger Pau Monné
2022-11-18 14:27     ` Andrew Cooper
2022-11-21  8:56       ` Jan Beulich
2022-11-21 12:23         ` Andrew Cooper
2022-11-21 12:34           ` Jan Beulich
2022-11-23 12:03             ` Roger Pau Monné
2022-11-24  7:59               ` Jan Beulich
2022-11-24  8:42                 ` Roger Pau Monné
2022-11-24  9:06                   ` Roger Pau Monné
2022-11-24  9:11                     ` Jan Beulich
2022-11-24  9:33                       ` Roger Pau Monné
2022-11-24 11:16                         ` Jan Beulich
2022-11-24 15:12                           ` Roger Pau Monné
2022-11-25  8:43                             ` Jan Beulich
2022-11-25  9:00                               ` Roger Pau Monné
2022-11-25  9:09                                 ` Jan Beulich
2022-11-24  9:06                   ` Jan Beulich
2022-12-05 13:44           ` Jan Beulich
2022-11-18 14:26 ` Roger Pau Monné
2022-11-21  8:33   ` Jan Beulich
2022-11-21 10:53     ` Roger Pau Monné
2022-11-21 11:14       ` Jan Beulich
2022-11-21 12:06     ` Jan Beulich

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