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From: Conor Dooley <conor@kernel.org>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Jisheng Zhang <jszhang@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Jiri Slaby <jirislaby@kernel.org>,
	linux-serial@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree
Date: Sun, 20 Nov 2022 17:51:19 +0000	[thread overview]
Message-ID: <Y3ppF88SuYAPOjbU@spud> (raw)
In-Reply-To: <CAJM55Z_f=zp3Z=wno_yr7csAUMQ472RiZXD19CrDTTxmGAmU4w@mail.gmail.com>

On Sun, Nov 20, 2022 at 03:57:17PM +0100, Emil Renner Berthing wrote:
> On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote:
> >
> > Add a baisc dtsi for the bouffalolab bl808 SoC.

> > +       xtal: xtal-clk {
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <40000000>;
> 
> This was discussed many times before, but I think the conclusion was
> that the frequency is a property of the crystal on the board, so this
> should be 0 in the SoC dtsi, and then overwritten in the board device
> tree.

Or set nothing in soc.dtsi so that dtbs_check can be used to see if
someone forgot to set a clock for their board?

> > +               clock-output-names = "xtal";
> > +               #clock-cells = <0>;
> > +       };


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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Jisheng Zhang <jszhang@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Jiri Slaby <jirislaby@kernel.org>,
	linux-serial@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree
Date: Sun, 20 Nov 2022 17:51:19 +0000	[thread overview]
Message-ID: <Y3ppF88SuYAPOjbU@spud> (raw)
In-Reply-To: <CAJM55Z_f=zp3Z=wno_yr7csAUMQ472RiZXD19CrDTTxmGAmU4w@mail.gmail.com>

On Sun, Nov 20, 2022 at 03:57:17PM +0100, Emil Renner Berthing wrote:
> On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote:
> >
> > Add a baisc dtsi for the bouffalolab bl808 SoC.

> > +       xtal: xtal-clk {
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <40000000>;
> 
> This was discussed many times before, but I think the conclusion was
> that the frequency is a property of the crystal on the board, so this
> should be 0 in the SoC dtsi, and then overwritten in the board device
> tree.

Or set nothing in soc.dtsi so that dtbs_check can be used to see if
someone forgot to set a clock for their board?

> > +               clock-output-names = "xtal";
> > +               #clock-cells = <0>;
> > +       };


  reply	other threads:[~2022-11-20 17:51 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-20  8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang
2022-11-20  8:21 ` Jisheng Zhang
2022-11-20  8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang
2022-11-20  8:21   ` Jisheng Zhang
2022-11-21 10:08   ` Krzysztof Kozlowski
2022-11-21 10:08     ` Krzysztof Kozlowski
2022-11-30 18:04   ` Rob Herring
2022-11-30 18:04     ` Rob Herring
2022-11-20  8:21 ` [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver Jisheng Zhang
2022-11-20  8:21   ` Jisheng Zhang
2022-11-21  8:09   ` Jiri Slaby
2022-11-21  8:09     ` Jiri Slaby
2022-11-21 13:59   ` Ilpo Järvinen
2022-11-21 13:59     ` Ilpo Järvinen
2022-11-20  8:21 ` [PATCH 3/7] MAINTAINERS: add myself as a reviewer for Bouffalolab uart driver Jisheng Zhang
2022-11-20  8:21   ` Jisheng Zhang
2022-11-20  8:21 ` [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang
2022-11-20  8:21   ` Jisheng Zhang
2022-11-20 10:43   ` Conor Dooley
2022-11-20 10:43     ` Conor Dooley
2022-11-20  8:21 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang
2022-11-20  8:21   ` Jisheng Zhang
2022-11-20 11:02   ` Conor Dooley
2022-11-20 11:02     ` Conor Dooley
2022-11-20 11:58     ` Icenowy Zheng
2022-11-20 11:58       ` Icenowy Zheng
2022-11-20 14:28       ` Conor Dooley
2022-11-20 14:28         ` Conor Dooley
2022-11-20 14:57   ` Emil Renner Berthing
2022-11-20 14:57     ` Emil Renner Berthing
2022-11-20 17:51     ` Conor Dooley [this message]
2022-11-20 17:51       ` Conor Dooley
2022-11-20 18:33       ` Emil Renner Berthing
2022-11-20 18:33         ` Emil Renner Berthing
2022-11-21  3:36     ` Icenowy Zheng
2022-11-21  3:36       ` Icenowy Zheng
2022-11-21 11:25       ` Emil Renner Berthing
2022-11-21 11:25         ` Emil Renner Berthing
2022-11-21 10:09   ` Krzysztof Kozlowski
2022-11-21 10:09     ` Krzysztof Kozlowski
2022-11-20  8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang
2022-11-20  8:21   ` Jisheng Zhang
2022-11-20 11:09   ` Conor Dooley
2022-11-20 11:09     ` Conor Dooley
2022-11-20 11:57   ` Icenowy Zheng
2022-11-20 11:57     ` Icenowy Zheng
2022-11-20 15:06   ` Emil Renner Berthing
2022-11-20 15:06     ` Emil Renner Berthing
2022-11-21 10:10   ` Krzysztof Kozlowski
2022-11-21 10:10     ` Krzysztof Kozlowski
2022-11-20  8:21 ` [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Jisheng Zhang
2022-11-20  8:21   ` Jisheng Zhang
2022-11-21 10:11   ` Krzysztof Kozlowski
2022-11-21 10:11     ` Krzysztof Kozlowski

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