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From: Conor Dooley <conor@kernel.org>
To: Sergey Matyukevich <geomatsi@gmail.com>
Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@rivosinc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Andrew Bresticker <abrestic@rivosinc.com>,
	Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Subject: Re: [PATCH RFC v2 1/3] riscv: add support for hardware breakpoints/watchpoints
Date: Sun, 4 Dec 2022 23:43:21 +0000	[thread overview]
Message-ID: <Y40wmUcqMQWQLBsI@spud> (raw)
In-Reply-To: <20221203215535.208948-2-geomatsi@gmail.com>

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On Sun, Dec 04, 2022 at 12:55:33AM +0300, Sergey Matyukevich wrote:
> From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> 
> RISC-V backend for hw-breakpoint framework is built on top of SBI Debug
> Trigger extension. Architecture specific hooks are implemented as kernel
> wrappers around ecalls to SBI functions. This patch implements only a
> minimal set of hooks required to support user-space debug via ptrace.
> 
> Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 2a0ef738695e..ef41d60a5ed3 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -31,6 +31,9 @@ enum sbi_ext_id {
>  	SBI_EXT_SRST = 0x53525354,
>  	SBI_EXT_PMU = 0x504D55,
>  
> +	/* Experimental: Debug Trigger Extension */
> +	SBI_EXT_DBTR = 0x44425452,
> +
>  	/* Experimentals extensions must lie within this range */
>  	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
>  	SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,

This is an RFC for something I know nothing about, so was just scrolling
mindlessly... This caught my eye as odd - There's an explicit comment
about the range for experimental stuff but you've not used it? I guess
there must be some reason for that?

Confused,
Conor.


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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Sergey Matyukevich <geomatsi@gmail.com>
Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@rivosinc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Andrew Bresticker <abrestic@rivosinc.com>,
	Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Subject: Re: [PATCH RFC v2 1/3] riscv: add support for hardware breakpoints/watchpoints
Date: Sun, 4 Dec 2022 23:43:21 +0000	[thread overview]
Message-ID: <Y40wmUcqMQWQLBsI@spud> (raw)
In-Reply-To: <20221203215535.208948-2-geomatsi@gmail.com>


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On Sun, Dec 04, 2022 at 12:55:33AM +0300, Sergey Matyukevich wrote:
> From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> 
> RISC-V backend for hw-breakpoint framework is built on top of SBI Debug
> Trigger extension. Architecture specific hooks are implemented as kernel
> wrappers around ecalls to SBI functions. This patch implements only a
> minimal set of hooks required to support user-space debug via ptrace.
> 
> Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 2a0ef738695e..ef41d60a5ed3 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -31,6 +31,9 @@ enum sbi_ext_id {
>  	SBI_EXT_SRST = 0x53525354,
>  	SBI_EXT_PMU = 0x504D55,
>  
> +	/* Experimental: Debug Trigger Extension */
> +	SBI_EXT_DBTR = 0x44425452,
> +
>  	/* Experimentals extensions must lie within this range */
>  	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
>  	SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,

This is an RFC for something I know nothing about, so was just scrolling
mindlessly... This caught my eye as odd - There's an explicit comment
about the range for experimental stuff but you've not used it? I guess
there must be some reason for that?

Confused,
Conor.


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  reply	other threads:[~2022-12-04 23:43 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-03 21:55 [PATCH RFC v2 0/3] riscv: support for hardware breakpoints/watchpoints Sergey Matyukevich
2022-12-03 21:55 ` Sergey Matyukevich
2022-12-03 21:55 ` [PATCH RFC v2 1/3] riscv: add " Sergey Matyukevich
2022-12-03 21:55   ` Sergey Matyukevich
2022-12-04 23:43   ` Conor Dooley [this message]
2022-12-04 23:43     ` Conor Dooley
2022-12-05  7:23     ` Sergey Matyukevich
2022-12-05  7:23       ` Sergey Matyukevich
2022-12-03 21:55 ` [PATCH RFC v2 2/3] riscv: ptrace: expose hardware breakpoints to debuggers Sergey Matyukevich
2022-12-03 21:55   ` Sergey Matyukevich
2022-12-03 21:55 ` [PATCH RFC v2 3/3] riscv: hw-breakpoints: add more trigger controls Sergey Matyukevich
2022-12-03 21:55   ` Sergey Matyukevich
2022-12-05 18:00   ` Andrew Bresticker
2022-12-05 18:00     ` Andrew Bresticker
2022-12-05 20:25     ` Sergey Matyukevich
2022-12-05 20:25       ` Sergey Matyukevich
2022-12-05 22:04       ` Andrew Bresticker
2022-12-05 22:04         ` Andrew Bresticker

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