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From: Conor Dooley <conor@kernel.org>
To: Samuel Holland <samuel@sholland.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <apatel@ventanamicro.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH] riscv: Fix NR_CPUS range conditions
Date: Sat, 26 Nov 2022 15:32:04 +0000	[thread overview]
Message-ID: <Y4IxdOPWhLLg5rwd@spud> (raw)
In-Reply-To: <20221126061557.3541-1-samuel@sholland.org>

On Sat, Nov 26, 2022 at 12:15:56AM -0600, Samuel Holland wrote:
> The conditions reference the symbol SBI_V01, which does not exist. The
> correct symbol is RISCV_SBI_V01.

Huh, good spot.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> Fixes: e623715f3d67 ("RISC-V: Increase range and default value of NR_CPUS")
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  arch/riscv/Kconfig | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index fec54872ab45..acbfe34c6a00 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -319,9 +319,9 @@ config SMP
>  config NR_CPUS
>  	int "Maximum number of CPUs (2-512)"
>  	depends on SMP
> -	range 2 512 if !SBI_V01
> -	range 2 32 if SBI_V01 && 32BIT
> -	range 2 64 if SBI_V01 && 64BIT
> +	range 2 512 if !RISCV_SBI_V01
> +	range 2 32 if RISCV_SBI_V01 && 32BIT
> +	range 2 64 if RISCV_SBI_V01 && 64BIT
>  	default "32" if 32BIT
>  	default "64" if 64BIT
>  
> -- 
> 2.37.4
> 

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Samuel Holland <samuel@sholland.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <apatel@ventanamicro.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH] riscv: Fix NR_CPUS range conditions
Date: Sat, 26 Nov 2022 15:32:04 +0000	[thread overview]
Message-ID: <Y4IxdOPWhLLg5rwd@spud> (raw)
In-Reply-To: <20221126061557.3541-1-samuel@sholland.org>

On Sat, Nov 26, 2022 at 12:15:56AM -0600, Samuel Holland wrote:
> The conditions reference the symbol SBI_V01, which does not exist. The
> correct symbol is RISCV_SBI_V01.

Huh, good spot.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> Fixes: e623715f3d67 ("RISC-V: Increase range and default value of NR_CPUS")
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  arch/riscv/Kconfig | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index fec54872ab45..acbfe34c6a00 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -319,9 +319,9 @@ config SMP
>  config NR_CPUS
>  	int "Maximum number of CPUs (2-512)"
>  	depends on SMP
> -	range 2 512 if !SBI_V01
> -	range 2 32 if SBI_V01 && 32BIT
> -	range 2 64 if SBI_V01 && 64BIT
> +	range 2 512 if !RISCV_SBI_V01
> +	range 2 32 if RISCV_SBI_V01 && 32BIT
> +	range 2 64 if RISCV_SBI_V01 && 64BIT
>  	default "32" if 32BIT
>  	default "64" if 64BIT
>  
> -- 
> 2.37.4
> 

  reply	other threads:[~2022-11-26 15:32 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-26  6:15 [PATCH] riscv: Fix NR_CPUS range conditions Samuel Holland
2022-11-26  6:15 ` Samuel Holland
2022-11-26 15:32 ` Conor Dooley [this message]
2022-11-26 15:32   ` Conor Dooley
2022-11-28 18:35   ` Andrew Jones
2022-11-28 18:35     ` Andrew Jones
2022-11-28 19:19     ` Conor Dooley
2022-11-28 19:19       ` Conor Dooley
2022-11-28 23:38     ` Palmer Dabbelt
2022-11-28 23:38       ` Palmer Dabbelt
2022-11-28 23:36 ` Palmer Dabbelt
2022-11-28 23:36   ` Palmer Dabbelt
2022-11-28 23:40 ` patchwork-bot+linux-riscv
2022-11-28 23:40   ` patchwork-bot+linux-riscv

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