From: Oliver Upton <oliver.upton@linux.dev>
To: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
asahi@lists.linux.dev, Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Sven Peter <sven@svenpeter.dev>, Hector Martin <marcan@marcan.st>
Subject: Re: [PATCH 0/3] KVM: arm64: Normalize cache configuration
Date: Wed, 14 Dec 2022 00:59:17 +0000 [thread overview]
Message-ID: <Y5kf5XDUb5En00BZ@google.com> (raw)
In-Reply-To: <20221211051700.275761-1-akihiko.odaki@daynix.com>
Hi Akihiko,
On Sun, Dec 11, 2022 at 02:16:57PM +0900, Akihiko Odaki wrote:
> Before this change, the cache configuration of the physical CPU was
> exposed to vcpus. This is problematic because the cache configuration a
> vcpu sees varies when it migrates between vcpus with different cache
> configurations.
>
> Fabricate cache configuration from arm64_ftr_reg_ctrel0.sys_val, which
> holds the CTR_EL0 value the userspace sees regardless of which physical
> CPU it resides on.
>
> HCR_TID2 is now always set as it is troublesome to detect the difference
> of cache configurations among physical CPUs.
>
> CSSELR_EL1 is now held in the memory instead of the corresponding
> phyisccal register as the fabricated cache configuration may have a
> cache level which does not exist in the physical CPU, and setting the
> physical CSSELR_EL1 for the level results in an UNKNOWN behavior.
>
> CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that
> the VMM can restore the values saved with the old kernel.
>
> Akihiko Odaki (3):
> arm64/sysreg: Add CCSIDR2_EL1
> arm64/cache: Move CLIDR macro definitions
> KVM: arm64: Normalize cache configuration
Next time you do a respin can you please bump the version number? I.e.
the next version should be v3.
Additionally, it is tremendously helpful to reviewers if you can provide
(1) a summary of what has changed in the current revision and (2) a
lore.kernel.org link to the last series you mailed out.
--
Thanks,
Oliver
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oliver.upton@linux.dev>
To: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Hector Martin <marcan@marcan.st>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Marc Zyngier <maz@kernel.org>, Sven Peter <sven@svenpeter.dev>,
linux-kernel@vger.kernel.org, Will Deacon <will@kernel.org>,
asahi@lists.linux.dev, Catalin Marinas <catalin.marinas@arm.com>,
kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/3] KVM: arm64: Normalize cache configuration
Date: Wed, 14 Dec 2022 00:59:17 +0000 [thread overview]
Message-ID: <Y5kf5XDUb5En00BZ@google.com> (raw)
In-Reply-To: <20221211051700.275761-1-akihiko.odaki@daynix.com>
Hi Akihiko,
On Sun, Dec 11, 2022 at 02:16:57PM +0900, Akihiko Odaki wrote:
> Before this change, the cache configuration of the physical CPU was
> exposed to vcpus. This is problematic because the cache configuration a
> vcpu sees varies when it migrates between vcpus with different cache
> configurations.
>
> Fabricate cache configuration from arm64_ftr_reg_ctrel0.sys_val, which
> holds the CTR_EL0 value the userspace sees regardless of which physical
> CPU it resides on.
>
> HCR_TID2 is now always set as it is troublesome to detect the difference
> of cache configurations among physical CPUs.
>
> CSSELR_EL1 is now held in the memory instead of the corresponding
> phyisccal register as the fabricated cache configuration may have a
> cache level which does not exist in the physical CPU, and setting the
> physical CSSELR_EL1 for the level results in an UNKNOWN behavior.
>
> CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that
> the VMM can restore the values saved with the old kernel.
>
> Akihiko Odaki (3):
> arm64/sysreg: Add CCSIDR2_EL1
> arm64/cache: Move CLIDR macro definitions
> KVM: arm64: Normalize cache configuration
Next time you do a respin can you please bump the version number? I.e.
the next version should be v3.
Additionally, it is tremendously helpful to reviewers if you can provide
(1) a summary of what has changed in the current revision and (2) a
lore.kernel.org link to the last series you mailed out.
--
Thanks,
Oliver
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oliver.upton@linux.dev>
To: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
asahi@lists.linux.dev, Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Sven Peter <sven@svenpeter.dev>, Hector Martin <marcan@marcan.st>
Subject: Re: [PATCH 0/3] KVM: arm64: Normalize cache configuration
Date: Wed, 14 Dec 2022 00:59:17 +0000 [thread overview]
Message-ID: <Y5kf5XDUb5En00BZ@google.com> (raw)
In-Reply-To: <20221211051700.275761-1-akihiko.odaki@daynix.com>
Hi Akihiko,
On Sun, Dec 11, 2022 at 02:16:57PM +0900, Akihiko Odaki wrote:
> Before this change, the cache configuration of the physical CPU was
> exposed to vcpus. This is problematic because the cache configuration a
> vcpu sees varies when it migrates between vcpus with different cache
> configurations.
>
> Fabricate cache configuration from arm64_ftr_reg_ctrel0.sys_val, which
> holds the CTR_EL0 value the userspace sees regardless of which physical
> CPU it resides on.
>
> HCR_TID2 is now always set as it is troublesome to detect the difference
> of cache configurations among physical CPUs.
>
> CSSELR_EL1 is now held in the memory instead of the corresponding
> phyisccal register as the fabricated cache configuration may have a
> cache level which does not exist in the physical CPU, and setting the
> physical CSSELR_EL1 for the level results in an UNKNOWN behavior.
>
> CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that
> the VMM can restore the values saved with the old kernel.
>
> Akihiko Odaki (3):
> arm64/sysreg: Add CCSIDR2_EL1
> arm64/cache: Move CLIDR macro definitions
> KVM: arm64: Normalize cache configuration
Next time you do a respin can you please bump the version number? I.e.
the next version should be v3.
Additionally, it is tremendously helpful to reviewers if you can provide
(1) a summary of what has changed in the current revision and (2) a
lore.kernel.org link to the last series you mailed out.
--
Thanks,
Oliver
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-12-14 0:59 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-11 5:16 [PATCH 0/3] KVM: arm64: Normalize cache configuration Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-11 5:16 ` [PATCH 1/3] arm64/sysreg: Add CCSIDR2_EL1 Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-19 13:12 ` Mark Brown
2022-12-19 13:12 ` Mark Brown
2022-12-19 13:12 ` Mark Brown
2022-12-19 14:47 ` Marc Zyngier
2022-12-19 14:47 ` Marc Zyngier
2022-12-19 14:47 ` Marc Zyngier
2022-12-19 14:50 ` Mark Brown
2022-12-19 14:50 ` Mark Brown
2022-12-19 14:50 ` Mark Brown
2022-12-19 15:04 ` Marc Zyngier
2022-12-19 15:04 ` Marc Zyngier
2022-12-19 15:04 ` Marc Zyngier
2022-12-11 5:16 ` [PATCH 2/3] arm64/cache: Move CLIDR macro definitions Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-11 5:16 ` Akihiko Odaki
2022-12-11 5:17 ` [PATCH 3/3] KVM: arm64: Normalize cache configuration Akihiko Odaki
2022-12-11 5:17 ` Akihiko Odaki
2022-12-11 5:17 ` Akihiko Odaki
2022-12-11 5:17 ` Akihiko Odaki
2022-12-14 14:58 ` Marc Zyngier
2022-12-14 14:58 ` Marc Zyngier
2022-12-14 14:58 ` Marc Zyngier
2022-12-14 0:59 ` Oliver Upton [this message]
2022-12-14 0:59 ` [PATCH 0/3] " Oliver Upton
2022-12-14 0:59 ` Oliver Upton
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