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From: Conor Dooley <conor@kernel.org>
To: Vineet Gupta <vineetg@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, linux@rivosinc.com
Subject: Re: [PATCH] riscv: add base extensions to enum riscv_isa_ext_id
Date: Thu, 22 Dec 2022 22:53:55 +0000	[thread overview]
Message-ID: <Y6TgAxg3csoQqaFr@spud> (raw)
In-Reply-To: <20221222224104.3449841-1-vineetg@rivosinc.com>


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Hi Vineet,

On Thu, Dec 22, 2022 at 02:41:04PM -0800, Vineet Gupta wrote:
> This allows for using the enum in general to refer to any extension.

What is the point of this patch? It's hard to understand the rationale
without having any user, especially...

> 
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> ---
>  arch/riscv/include/asm/hwcap.h | 19 +++++++++----------
>  1 file changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b22525290073..b861e711e3ac 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -26,16 +26,6 @@ enum {
>  
>  extern unsigned long elf_hwcap;
>  
> -#define RISCV_ISA_EXT_a		('a' - 'a')
> -#define RISCV_ISA_EXT_c		('c' - 'a')
> -#define RISCV_ISA_EXT_d		('d' - 'a')
> -#define RISCV_ISA_EXT_f		('f' - 'a')
> -#define RISCV_ISA_EXT_h		('h' - 'a')
> -#define RISCV_ISA_EXT_i		('i' - 'a')
> -#define RISCV_ISA_EXT_m		('m' - 'a')
> -#define RISCV_ISA_EXT_s		('s' - 'a')
> -#define RISCV_ISA_EXT_u		('u' - 'a')
> -
>  /*
>   * Increse this to higher value as kernel support more ISA extensions.
>   */
> @@ -53,6 +43,15 @@ extern unsigned long elf_hwcap;
>   * available logical extension id.
>   */
>  enum riscv_isa_ext_id {
> +	RISCV_ISA_EXT_a = ('a' - 'a'),
> +	RISCV_ISA_EXT_c = ('c' - 'a'),
> +	RISCV_ISA_EXT_d = ('d' - 'a'),
> +	RISCV_ISA_EXT_f = ('f' - 'a'),
> +	RISCV_ISA_EXT_h = ('h' - 'a'),
> +	RISCV_ISA_EXT_i = ('i' - 'a'),
> +	RISCV_ISA_EXT_m = ('m' - 'a'),
> +	RISCV_ISA_EXT_s = ('s' - 'a'),
> +	RISCV_ISA_EXT_u = ('u' - 'a'),

... as it is diametrically opposed to another patchset which deletes
this enum, with a rationale.
https://lore.kernel.org/linux-riscv/20221204174632.3677-5-jszhang@kernel.org/

+CC Jisheng.

Also, please run get_maintainer.pl, there's a bunch of people touching
this area at the moment & CCing them would be great.

Thanks,
Conor.

btw, is the rivos list intentionally on CC?

>  	RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
>  	RISCV_ISA_EXT_SVPBMT,
>  	RISCV_ISA_EXT_ZICBOM,
> -- 
> 2.34.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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  reply	other threads:[~2022-12-22 22:54 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-22 22:41 [PATCH] riscv: add base extensions to enum riscv_isa_ext_id Vineet Gupta
2022-12-22 22:53 ` Conor Dooley [this message]
2022-12-22 23:01   ` Conor Dooley
2022-12-22 23:13   ` Vineet Gupta
2022-12-22 23:35     ` Conor Dooley
2022-12-23  0:03       ` Vineet Gupta
2022-12-23  0:30         ` Conor Dooley

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