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From: Conor Dooley <conor@kernel.org>
To: Andre Przywara <andre.przywara@arm.com>
Cc: devicetree@vger.kernel.org, "Albert Ou" <aou@eecs.berkeley.edu>,
	"Samuel Holland" <samuel@sholland.org>,
	"Fabien Poussin" <fabien.poussin@gmail.com>,
	linux-kernel@vger.kernel.org,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org,
	"Frank Rowand" <frowand.list@gmail.com>,
	linux-sunxi@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org,
	"András Szemzö" <szemzo.andras@gmail.com>
Subject: Re: [PATCH 1/4] dts: add riscv include prefix link
Date: Sun, 8 Jan 2023 17:15:56 +0000	[thread overview]
Message-ID: <Y7r6TLTm1r+IlrYj@spud> (raw)
In-Reply-To: <20230106010155.26868-2-andre.przywara@arm.com>


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On Fri, Jan 06, 2023 at 01:01:52AM +0000, Andre Przywara wrote:
> The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
> die as their R528/T113-s siblings with ARM Cortex-A7 cores.
> 
> To allow sharing the basic SoC .dtsi files across those two
> architectures as well, introduce a symlink to the RISC-V DT directory.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  scripts/dtc/include-prefixes/riscv | 1 +
>  1 file changed, 1 insertion(+)
>  create mode 120000 scripts/dtc/include-prefixes/riscv
> 
> diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
> new file mode 120000
> index 0000000000000..2025094189380
> --- /dev/null
> +++ b/scripts/dtc/include-prefixes/riscv
> @@ -0,0 +1 @@
> +../../../arch/riscv/boot/dts
> \ No newline at end of file
> -- 
> 2.35.5
> 
> 

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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andre Przywara <andre.przywara@arm.com>
Cc: "Samuel Holland" <samuel@sholland.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Icenowy Zheng" <uwu@icenowy.me>,
	"András Szemzö" <szemzo.andras@gmail.com>,
	"Fabien Poussin" <fabien.poussin@gmail.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	"Frank Rowand" <frowand.list@gmail.com>
Subject: Re: [PATCH 1/4] dts: add riscv include prefix link
Date: Sun, 8 Jan 2023 17:15:56 +0000	[thread overview]
Message-ID: <Y7r6TLTm1r+IlrYj@spud> (raw)
In-Reply-To: <20230106010155.26868-2-andre.przywara@arm.com>

[-- Attachment #1: Type: text/plain, Size: 953 bytes --]

On Fri, Jan 06, 2023 at 01:01:52AM +0000, Andre Przywara wrote:
> The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
> die as their R528/T113-s siblings with ARM Cortex-A7 cores.
> 
> To allow sharing the basic SoC .dtsi files across those two
> architectures as well, introduce a symlink to the RISC-V DT directory.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  scripts/dtc/include-prefixes/riscv | 1 +
>  1 file changed, 1 insertion(+)
>  create mode 120000 scripts/dtc/include-prefixes/riscv
> 
> diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
> new file mode 120000
> index 0000000000000..2025094189380
> --- /dev/null
> +++ b/scripts/dtc/include-prefixes/riscv
> @@ -0,0 +1 @@
> +../../../arch/riscv/boot/dts
> \ No newline at end of file
> -- 
> 2.35.5
> 
> 

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andre Przywara <andre.przywara@arm.com>
Cc: "Samuel Holland" <samuel@sholland.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Icenowy Zheng" <uwu@icenowy.me>,
	"András Szemzö" <szemzo.andras@gmail.com>,
	"Fabien Poussin" <fabien.poussin@gmail.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	"Frank Rowand" <frowand.list@gmail.com>
Subject: Re: [PATCH 1/4] dts: add riscv include prefix link
Date: Sun, 8 Jan 2023 17:15:56 +0000	[thread overview]
Message-ID: <Y7r6TLTm1r+IlrYj@spud> (raw)
In-Reply-To: <20230106010155.26868-2-andre.przywara@arm.com>


[-- Attachment #1.1: Type: text/plain, Size: 953 bytes --]

On Fri, Jan 06, 2023 at 01:01:52AM +0000, Andre Przywara wrote:
> The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
> die as their R528/T113-s siblings with ARM Cortex-A7 cores.
> 
> To allow sharing the basic SoC .dtsi files across those two
> architectures as well, introduce a symlink to the RISC-V DT directory.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  scripts/dtc/include-prefixes/riscv | 1 +
>  1 file changed, 1 insertion(+)
>  create mode 120000 scripts/dtc/include-prefixes/riscv
> 
> diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
> new file mode 120000
> index 0000000000000..2025094189380
> --- /dev/null
> +++ b/scripts/dtc/include-prefixes/riscv
> @@ -0,0 +1 @@
> +../../../arch/riscv/boot/dts
> \ No newline at end of file
> -- 
> 2.35.5
> 
> 

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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2023-01-08 17:16 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-06  1:01 [PATCH 0/4] ARM: dts: sunxi: Add MangoPi MQ-R board support Andre Przywara
2023-01-06  1:01 ` Andre Przywara
2023-01-06  1:01 ` Andre Przywara
2023-01-06  1:01 ` [PATCH 1/4] dts: add riscv include prefix link Andre Przywara
2023-01-06  1:01   ` Andre Przywara
2023-01-06  1:01   ` Andre Przywara
2023-01-08 17:15   ` Conor Dooley [this message]
2023-01-08 17:15     ` Conor Dooley
2023-01-08 17:15     ` Conor Dooley
2023-03-07 20:59   ` Palmer Dabbelt
2023-03-07 20:59     ` Palmer Dabbelt
2023-03-07 20:59     ` Palmer Dabbelt
2023-01-06  1:01 ` [PATCH 2/4] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi Andre Przywara
2023-01-06  1:01   ` Andre Przywara
2023-01-06  1:01   ` Andre Przywara
2023-01-06  1:01 ` [PATCH 3/4] dt-bindings: arm: sunxi: document MangoPi MQ-R board name Andre Przywara
2023-01-06  1:01   ` Andre Przywara
2023-01-06  1:01   ` Andre Przywara
2023-01-06  9:21   ` Krzysztof Kozlowski
2023-01-06  9:21     ` Krzysztof Kozlowski
2023-01-06  9:21     ` Krzysztof Kozlowski
2023-01-06 10:28     ` Andre Przywara
2023-01-06 10:28       ` Andre Przywara
2023-01-06 10:28       ` Andre Przywara
2023-01-06 11:07   ` Krzysztof Kozlowski
2023-01-06 11:07     ` Krzysztof Kozlowski
2023-01-06 11:07     ` Krzysztof Kozlowski
2023-01-06  1:01 ` [PATCH 4/4] ARM: dts: sunxi: add MangoPi MQ-R board Andre Przywara
2023-01-06  1:01   ` Andre Przywara
2023-01-06  1:01   ` Andre Przywara
2023-01-06  9:21   ` Krzysztof Kozlowski
2023-01-06  9:21     ` Krzysztof Kozlowski
2023-01-06  9:21     ` Krzysztof Kozlowski
2023-01-06 16:24   ` kernel test robot
2023-01-06 16:24     ` kernel test robot
2023-01-06 18:35   ` kernel test robot
2023-01-06 18:35     ` kernel test robot
2023-01-06 17:17 ` [PATCH 0/4] ARM: dts: sunxi: Add MangoPi MQ-R board support Andre Przywara
2023-01-06 17:17   ` Andre Przywara
2023-01-06 17:17   ` Andre Przywara

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