From: Oliver Upton <oliver.upton@linux.dev>
To: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Mark Brown <broonie@kernel.org>, Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
asahi@lists.linux.dev, Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Sven Peter <sven@svenpeter.dev>, Hector Martin <marcan@marcan.st>
Subject: Re: [PATCH v7 7/7] KVM: arm64: Normalize cache configuration
Date: Thu, 19 Jan 2023 19:46:16 +0000 [thread overview]
Message-ID: <Y8meCFkrVXurXlTk@google.com> (raw)
In-Reply-To: <20230112023852.42012-8-akihiko.odaki@daynix.com>
Hi Akihiko,
On Thu, Jan 12, 2023 at 11:38:52AM +0900, Akihiko Odaki wrote:
> Before this change, the cache configuration of the physical CPU was
> exposed to vcpus. This is problematic because the cache configuration a
> vcpu sees varies when it migrates between vcpus with different cache
> configurations.
>
> Fabricate cache configuration from the sanitized value, which holds the
> CTR_EL0 value the userspace sees regardless of which physical CPU it
> resides on.
>
> CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that
> the VMM can restore the values saved with the old kernel.
>
> Suggested-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
I needed to squash in the patch below to get all of this working.
Writing back the value read for a given cache level was failing, which I
caught with the get-reg-list selftest.
Pushed the result here if you want to have a look:
https://github.com/oupton/linux/tree/kvm-arm64/virtual-cache-geometry
--
Thanks,
Oliver
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 459e6d358dab..b6228f7d1d8d 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -148,17 +148,19 @@ static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
{
- u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val);
+ u8 line_size = SYS_FIELD_GET(CCSIDR_EL1, LineSize, val);
+ u32 cur = get_ccsidr(vcpu, csselr);
+ u8 min_line_size = SYS_FIELD_GET(CCSIDR_EL1, LineSize, cur);
u32 *ccsidr = vcpu->arch.ccsidr;
u32 i;
- if ((val & CCSIDR_EL1_RES0) || line_size < get_min_cache_line_size(csselr))
+ if (cur == val)
+ return 0;
+
+ if ((val & CCSIDR_EL1_RES0) || line_size < min_line_size)
return -EINVAL;
if (!ccsidr) {
- if (val == get_ccsidr(vcpu, csselr))
- return 0;
-
ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL);
if (!ccsidr)
return -ENOMEM;
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oliver.upton@linux.dev>
To: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Mark Brown <broonie@kernel.org>, Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
asahi@lists.linux.dev, Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Sven Peter <sven@svenpeter.dev>, Hector Martin <marcan@marcan.st>
Subject: Re: [PATCH v7 7/7] KVM: arm64: Normalize cache configuration
Date: Thu, 19 Jan 2023 19:46:16 +0000 [thread overview]
Message-ID: <Y8meCFkrVXurXlTk@google.com> (raw)
In-Reply-To: <20230112023852.42012-8-akihiko.odaki@daynix.com>
Hi Akihiko,
On Thu, Jan 12, 2023 at 11:38:52AM +0900, Akihiko Odaki wrote:
> Before this change, the cache configuration of the physical CPU was
> exposed to vcpus. This is problematic because the cache configuration a
> vcpu sees varies when it migrates between vcpus with different cache
> configurations.
>
> Fabricate cache configuration from the sanitized value, which holds the
> CTR_EL0 value the userspace sees regardless of which physical CPU it
> resides on.
>
> CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that
> the VMM can restore the values saved with the old kernel.
>
> Suggested-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
I needed to squash in the patch below to get all of this working.
Writing back the value read for a given cache level was failing, which I
caught with the get-reg-list selftest.
Pushed the result here if you want to have a look:
https://github.com/oupton/linux/tree/kvm-arm64/virtual-cache-geometry
--
Thanks,
Oliver
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 459e6d358dab..b6228f7d1d8d 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -148,17 +148,19 @@ static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
{
- u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val);
+ u8 line_size = SYS_FIELD_GET(CCSIDR_EL1, LineSize, val);
+ u32 cur = get_ccsidr(vcpu, csselr);
+ u8 min_line_size = SYS_FIELD_GET(CCSIDR_EL1, LineSize, cur);
u32 *ccsidr = vcpu->arch.ccsidr;
u32 i;
- if ((val & CCSIDR_EL1_RES0) || line_size < get_min_cache_line_size(csselr))
+ if (cur == val)
+ return 0;
+
+ if ((val & CCSIDR_EL1_RES0) || line_size < min_line_size)
return -EINVAL;
if (!ccsidr) {
- if (val == get_ccsidr(vcpu, csselr))
- return 0;
-
ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL);
if (!ccsidr)
return -ENOMEM;
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next prev parent reply other threads:[~2023-01-19 19:46 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-12 2:38 [PATCH v7 0/7] KVM: arm64: Normalize cache configuration Akihiko Odaki
2023-01-12 2:38 ` Akihiko Odaki
2023-01-12 2:38 ` [PATCH v7 1/7] arm64: Allow the definition of UNKNOWN system register fields Akihiko Odaki
2023-01-12 2:38 ` Akihiko Odaki
2023-01-12 2:38 ` [PATCH v7 2/7] arm64/sysreg: Convert CCSIDR_EL1 to automatic generation Akihiko Odaki
2023-01-12 2:38 ` Akihiko Odaki
2023-01-12 2:38 ` [PATCH v7 3/7] arm64/sysreg: Add CCSIDR2_EL1 Akihiko Odaki
2023-01-12 2:38 ` Akihiko Odaki
2023-01-12 2:38 ` [PATCH v7 4/7] arm64/cache: Move CLIDR macro definitions Akihiko Odaki
2023-01-12 2:38 ` Akihiko Odaki
2023-01-12 2:38 ` [PATCH v7 5/7] KVM: arm64: Always set HCR_TID2 Akihiko Odaki
2023-01-12 2:38 ` Akihiko Odaki
2023-01-12 2:38 ` [PATCH v7 6/7] KVM: arm64: Mask FEAT_CCIDX Akihiko Odaki
2023-01-12 2:38 ` Akihiko Odaki
2023-01-12 2:38 ` [PATCH v7 7/7] KVM: arm64: Normalize cache configuration Akihiko Odaki
2023-01-12 2:38 ` Akihiko Odaki
2023-01-19 19:46 ` Oliver Upton [this message]
2023-01-19 19:46 ` Oliver Upton
2023-01-21 12:02 ` Marc Zyngier
2023-01-21 12:02 ` Marc Zyngier
2023-01-21 18:15 ` Oliver Upton
2023-01-21 18:15 ` Oliver Upton
2023-01-22 17:36 ` Akihiko Odaki
2023-01-22 17:36 ` Akihiko Odaki
2023-01-22 19:45 ` Oliver Upton
2023-01-22 19:45 ` Oliver Upton
2023-01-23 11:11 ` Marc Zyngier
2023-01-23 11:11 ` Marc Zyngier
2026-04-09 12:25 ` David Woodhouse
2026-04-09 13:36 ` Marc Zyngier
2026-04-09 14:51 ` David Woodhouse
2026-04-09 15:45 ` Marc Zyngier
2026-04-09 16:10 ` David Woodhouse
2026-04-09 15:29 ` [PATCH] KVM: arm64: Add KVM_CAP_ARM_NATIVE_CACHE_CONFIG vcpu capability David Woodhouse
2026-04-09 17:07 ` Marc Zyngier
2026-04-09 17:49 ` David Woodhouse
2026-04-09 18:12 ` Marc Zyngier
2026-04-09 21:10 ` David Woodhouse
2023-01-23 20:24 ` [PATCH v7 0/7] KVM: arm64: Normalize cache configuration Oliver Upton
2023-01-23 20:24 ` Oliver Upton
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