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From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: linux-spi@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH] spi: sh-msiof: Enforce fixed DTDL for R-Car H3
Date: Thu, 26 Jan 2023 14:07:06 +0100	[thread overview]
Message-ID: <Y9J6+uoXxUIs4Bkk@ninjato> (raw)
In-Reply-To: <CAMuHMdUnUf+ZTRTBSmjz1_61CpWvaO=fyDv7ExT+FnQi=ujFXw@mail.gmail.com>

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Hi Geert,

> > Documentation says only DTDL of 200 is allowed for this SoC.
> 
> Do you have a pointer to that?

Yes: Gen3 docs Rev.2.30 from Aug 2021, Section 59.2.1, Bits 22-20:

"[R-Car H3, R-Car H3-N]
010: 2-clock-cycle delay
Other than above: Setting prohibited"

> We already have "renesas,dtdl" to configure this from DT.
> Iff this is really needed, perhaps it should be added to r8a77951.dtsi?

I have to disagree here. The docs say that other values are prohibited.
IMO the driver should take care of valid values then. We should not rely
on user provided input.

> I suspect this is a leftover in the BSP from attempts to get MSIOF
> working on R-Car H3 ES1.0 (which it never did for me, as CLK starts
> and stops too soon, compared to MOSI/MISO).
> On R-Car H3 ES2.0, everything works fine, without touching DTDL.

The BSP originally has this patch for ES3 only. I extended to ES2 as
well because that is what the docs say.

Happy hacking,

   Wolfram


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  reply	other threads:[~2023-01-26 13:07 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-24  7:47 [PATCH] spi: sh-msiof: Enforce fixed DTDL for R-Car H3 Wolfram Sang
2023-01-26  9:57 ` Geert Uytterhoeven
2023-01-26 13:07   ` Wolfram Sang [this message]
2023-01-26 13:26     ` Geert Uytterhoeven
2023-01-26 13:40       ` Wolfram Sang
2023-01-26 13:43         ` Geert Uytterhoeven
2023-02-15  8:02         ` Geert Uytterhoeven
2023-02-16  2:59 ` Yoshihiro Shimoda

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