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From: Conor Dooley <conor@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers
Date: Thu, 26 Jan 2023 21:06:49 +0000	[thread overview]
Message-ID: <Y9LraUk0SZfYWu+O@spud> (raw)
In-Reply-To: <20230125142056.18356-7-andy.chiu@sifive.com>

Hey Andy,

On Wed, Jan 25, 2023 at 02:20:43PM +0000, Andy Chiu wrote:
> These are small and likely to be frequently called so implement as
> inline routines (vs. function call).
> 
> Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> [vineetg: create new patch from meshup, introduced asm variant]
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> [andy.chiu: remove calls from asm thus remove asm vaiant]

Again, these chains are odd but a reflection of the series' history I
guess.

> ---
>  arch/riscv/include/asm/vector.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 917c8867e702..0fda0faf5277 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -11,12 +11,23 @@
>  #ifdef CONFIG_RISCV_ISA_V
>  
>  #include <asm/hwcap.h>
> +#include <asm/csr.h>
>  
>  static __always_inline bool has_vector(void)
>  {
>  	return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]);

This likely will need to drop the static branch due to Jisheng's series.
See here for what the equivalent change to has_fpu() was:
https://lore.kernel.org/all/20230115154953.831-1-jszhang at kernel.org/
Hopefully that series has been queued by the time you are resubmitting
this one.

>  }
>  
> +static __always_inline void rvv_enable(void)

I'm not keen on these function names. IMO, they should be
riscv_v_{en,dis}able() to match other riscv specific functions, like
those of zicbom or sbi stuff.
Other parts of this series use riscv_v_foo & riscv_vfoo. Some of the kvm
bits spell out vector rather than v. Consistent naming of functions etc
would be appreciated.

Thanks,
Conor.

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>
Subject: Re: [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers
Date: Thu, 26 Jan 2023 21:06:49 +0000	[thread overview]
Message-ID: <Y9LraUk0SZfYWu+O@spud> (raw)
In-Reply-To: <20230125142056.18356-7-andy.chiu@sifive.com>


[-- Attachment #1.1: Type: text/plain, Size: 2046 bytes --]

Hey Andy,

On Wed, Jan 25, 2023 at 02:20:43PM +0000, Andy Chiu wrote:
> These are small and likely to be frequently called so implement as
> inline routines (vs. function call).
> 
> Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> [vineetg: create new patch from meshup, introduced asm variant]
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> [andy.chiu: remove calls from asm thus remove asm vaiant]

Again, these chains are odd but a reflection of the series' history I
guess.

> ---
>  arch/riscv/include/asm/vector.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 917c8867e702..0fda0faf5277 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -11,12 +11,23 @@
>  #ifdef CONFIG_RISCV_ISA_V
>  
>  #include <asm/hwcap.h>
> +#include <asm/csr.h>
>  
>  static __always_inline bool has_vector(void)
>  {
>  	return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]);

This likely will need to drop the static branch due to Jisheng's series.
See here for what the equivalent change to has_fpu() was:
https://lore.kernel.org/all/20230115154953.831-1-jszhang@kernel.org/
Hopefully that series has been queued by the time you are resubmitting
this one.

>  }
>  
> +static __always_inline void rvv_enable(void)

I'm not keen on these function names. IMO, they should be
riscv_v_{en,dis}able() to match other riscv specific functions, like
those of zicbom or sbi stuff.
Other parts of this series use riscv_v_foo & riscv_vfoo. Some of the kvm
bits spell out vector rather than v. Consistent naming of functions etc
would be appreciated.

Thanks,
Conor.


[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>
Subject: Re: [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers
Date: Thu, 26 Jan 2023 21:06:49 +0000	[thread overview]
Message-ID: <Y9LraUk0SZfYWu+O@spud> (raw)
In-Reply-To: <20230125142056.18356-7-andy.chiu@sifive.com>

[-- Attachment #1: Type: text/plain, Size: 2046 bytes --]

Hey Andy,

On Wed, Jan 25, 2023 at 02:20:43PM +0000, Andy Chiu wrote:
> These are small and likely to be frequently called so implement as
> inline routines (vs. function call).
> 
> Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> [vineetg: create new patch from meshup, introduced asm variant]
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> [andy.chiu: remove calls from asm thus remove asm vaiant]

Again, these chains are odd but a reflection of the series' history I
guess.

> ---
>  arch/riscv/include/asm/vector.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 917c8867e702..0fda0faf5277 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -11,12 +11,23 @@
>  #ifdef CONFIG_RISCV_ISA_V
>  
>  #include <asm/hwcap.h>
> +#include <asm/csr.h>
>  
>  static __always_inline bool has_vector(void)
>  {
>  	return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]);

This likely will need to drop the static branch due to Jisheng's series.
See here for what the equivalent change to has_fpu() was:
https://lore.kernel.org/all/20230115154953.831-1-jszhang@kernel.org/
Hopefully that series has been queued by the time you are resubmitting
this one.

>  }
>  
> +static __always_inline void rvv_enable(void)

I'm not keen on these function names. IMO, they should be
riscv_v_{en,dis}able() to match other riscv specific functions, like
those of zicbom or sbi stuff.
Other parts of this series use riscv_v_foo & riscv_vfoo. Some of the kvm
bits spell out vector rather than v. Consistent naming of functions etc
would be appreciated.

Thanks,
Conor.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

  reply	other threads:[~2023-01-26 21:06 UTC|newest]

Thread overview: 192+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:15   ` Conor Dooley
2023-01-25 21:15     ` Conor Dooley
2023-01-25 21:15     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:33   ` Conor Dooley
2023-01-25 21:33     ` Conor Dooley
2023-01-25 21:33     ` Conor Dooley
2023-01-28  7:09     ` Guo Ren
2023-01-28  7:09       ` Guo Ren
2023-01-28  7:09       ` Guo Ren
2023-01-28 10:28       ` Conor Dooley
2023-01-28 10:28         ` Conor Dooley
2023-01-28 10:28         ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 22:16   ` Conor Dooley
2023-01-25 22:16     ` Conor Dooley
2023-01-25 22:16     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:54   ` Conor Dooley
2023-01-25 21:54     ` Conor Dooley
2023-01-25 21:54     ` Conor Dooley
2023-01-25 21:57     ` Vineet Gupta
2023-01-25 21:57       ` Vineet Gupta
2023-01-25 21:57       ` Vineet Gupta
2023-01-25 22:18       ` Conor Dooley
2023-01-25 22:18         ` Conor Dooley
2023-01-25 22:18         ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:51   ` Conor Dooley
2023-01-25 21:51     ` Conor Dooley
2023-01-25 21:51     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 21:06   ` Conor Dooley [this message]
2023-01-26 21:06     ` Conor Dooley
2023-01-26 21:06     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 21:24   ` Conor Dooley
2023-01-26 21:24     ` Conor Dooley
2023-01-26 21:24     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 21:32   ` Conor Dooley
2023-01-26 21:32     ` Conor Dooley
2023-01-26 21:32     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 21:44   ` Conor Dooley
2023-01-26 21:44     ` Conor Dooley
2023-01-26 21:44     ` Conor Dooley
2023-01-31  2:55   ` Vineet Gupta
2023-01-31  2:55     ` Vineet Gupta
2023-01-31  2:55     ` Vineet Gupta
2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 23:11   ` Conor Dooley
2023-01-26 23:11     ` Conor Dooley
2023-01-26 23:11     ` Conor Dooley
2023-02-06 12:00     ` Andy Chiu
2023-02-06 12:00       ` Andy Chiu
2023-02-06 12:00       ` Andy Chiu
2023-02-06 13:40       ` Conor Dooley
2023-02-06 13:40         ` Conor Dooley
2023-02-06 13:40         ` Conor Dooley
2023-02-10 12:00         ` Andy Chiu
2023-02-10 12:00           ` Andy Chiu
2023-02-10 12:00           ` Andy Chiu
2023-02-07 14:36   ` Björn Töpel
2023-02-07 14:36     ` Björn Töpel
2023-02-07 14:36     ` Björn Töpel
2023-02-13 22:54     ` Vineet Gupta
2023-02-13 22:54       ` Vineet Gupta
2023-02-13 22:54       ` Vineet Gupta
2023-02-14  6:43       ` Björn Töpel
2023-02-14  6:43         ` Björn Töpel
2023-02-14  6:43         ` Björn Töpel
2023-02-14 15:36         ` Andy Chiu
2023-02-14 15:36           ` Andy Chiu
2023-02-14 15:36           ` Andy Chiu
2023-02-14 16:50           ` Björn Töpel
2023-02-14 16:50             ` Björn Töpel
2023-02-14 16:50             ` Björn Töpel
2023-02-14 17:24             ` Vineet Gupta
2023-02-14 17:24               ` Vineet Gupta
2023-02-14 17:24               ` Vineet Gupta
2023-02-15  7:14               ` Björn Töpel
2023-02-15  7:14                 ` Björn Töpel
2023-02-15  7:14                 ` Björn Töpel
2023-02-15 14:39                 ` Andy Chiu
2023-02-15 14:39                   ` Andy Chiu
2023-02-15 14:39                   ` Andy Chiu
2023-02-07 21:18   ` Vineet Gupta
2023-02-07 21:18     ` Vineet Gupta
2023-02-07 21:18     ` Vineet Gupta
2023-02-08  9:20     ` Björn Töpel
2023-02-08  9:20       ` Björn Töpel
2023-02-08  9:20       ` Björn Töpel
2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 23:19   ` Conor Dooley
2023-01-26 23:19     ` Conor Dooley
2023-01-26 23:19     ` Conor Dooley
2023-01-31 12:34     ` Andy Chiu
2023-01-31 12:34       ` Andy Chiu
2023-01-31 12:34       ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-27 20:31   ` Conor Dooley
2023-01-27 20:31     ` Conor Dooley
2023-01-27 20:31     ` Conor Dooley
2023-01-31 12:34     ` Andy Chiu
2023-01-31 12:34       ` Andy Chiu
2023-01-31 12:34       ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-27 20:43   ` Conor Dooley
2023-01-27 20:43     ` Conor Dooley
2023-01-27 20:43     ` Conor Dooley
2023-01-30  9:58     ` Andy Chiu
2023-01-30  9:58       ` Andy Chiu
2023-01-30  9:58       ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-27 11:28   ` Anup Patel
2023-01-27 11:28     ` Anup Patel
2023-01-27 11:28     ` Anup Patel
2023-01-30  8:18     ` Andy Chiu
2023-01-30  8:18       ` Andy Chiu
2023-01-30  8:18       ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:04   ` Conor Dooley
2023-01-25 21:04     ` Conor Dooley
2023-01-25 21:04     ` Conor Dooley
2023-01-25 21:38     ` Jessica Clarke
2023-01-25 21:38       ` Jessica Clarke
2023-01-25 21:38       ` Jessica Clarke
2023-01-25 22:24       ` Conor Dooley
2023-01-25 22:24         ` Conor Dooley
2023-01-25 22:24         ` Conor Dooley
2023-01-30  6:38     ` Andy Chiu
2023-01-30  6:38       ` Andy Chiu
2023-01-30  6:38       ` Andy Chiu
2023-01-30 18:38       ` Vineet Gupta
2023-01-30 18:38         ` Vineet Gupta
2023-01-30 18:38         ` Vineet Gupta
2023-01-30  7:46     ` Andy Chiu
2023-01-30  7:46       ` Andy Chiu
2023-01-30  7:46       ` Andy Chiu
2023-01-30  8:13       ` Conor Dooley
2023-01-30  8:13         ` Conor Dooley
2023-01-30  8:13         ` Conor Dooley
2023-02-08 18:19         ` Conor Dooley
2023-02-08 18:19           ` Conor Dooley
2023-02-08 18:19           ` Conor Dooley

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