* [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-01-29 6:49 ` Jinyu Tang
0 siblings, 0 replies; 18+ messages in thread
From: Jinyu Tang @ 2023-01-29 6:49 UTC (permalink / raw)
To: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, ajones,
guoren, tongtiangen, anup
Cc: akpm, falcon, linux-riscv, linux-kernel, Jinyu Tang
The arch_has_hw_pte_young() is false for riscv by default. If it's
false, page table walk is almost skipped for MGLRU reclaim. And it
will also cause useless step in __wp_page_copy_user().
RISC-V Privileged Book says that riscv have two schemes to manage A
and D bit.
So add a config for selecting, the default is true. For simple
implementation riscv CPU which just generate page fault, unselect it.
Signed-off-by: Jinyu Tang <tjytimi@163.com>
---
arch/riscv/Kconfig | 10 ++++++++++
arch/riscv/include/asm/pgtable.h | 7 +++++++
2 files changed, 17 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index e2b656043abf..17c82885549c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -180,6 +180,16 @@ config PAGE_OFFSET
default 0x80000000 if 64BIT && !MMU
default 0xff60000000000000 if 64BIT
+config ARCH_HAS_HARDWARE_PTE_YOUNG
+ bool "Hardware Set PTE Access Bit"
+ default y
+ help
+ Select if hardware set A bit when PTE is accessed. The default is
+ 'Y', because most RISC-V CPU hardware can manage A and D bit.
+ But RISC-V may have simple implementation that do not support
+ hardware set A bit but only generate page fault, for that case just
+ unselect it.
+
config KASAN_SHADOW_OFFSET
hex
depends on KASAN_GENERIC
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 4eba9a98d0e3..1db54ab4e1ba 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
*/
return ptep_test_and_clear_young(vma, address, ptep);
}
+#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
+#define arch_has_hw_pte_young arch_has_hw_pte_young
+static inline bool arch_has_hw_pte_young(void)
+{
+ return true;
+}
+#endif
#define pgprot_noncached pgprot_noncached
static inline pgprot_t pgprot_noncached(pgprot_t _prot)
--
2.30.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
2023-01-29 6:49 ` Jinyu Tang
@ 2023-01-30 8:22 ` Andrew Jones
-1 siblings, 0 replies; 18+ messages in thread
From: Andrew Jones @ 2023-01-30 8:22 UTC (permalink / raw)
To: Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, guoren,
tongtiangen, anup, akpm, falcon, linux-riscv, linux-kernel
On Sun, Jan 29, 2023 at 02:49:56PM +0800, Jinyu Tang wrote:
> The arch_has_hw_pte_young() is false for riscv by default. If it's
> false, page table walk is almost skipped for MGLRU reclaim. And it
> will also cause useless step in __wp_page_copy_user().
>
> RISC-V Privileged Book says that riscv have two schemes to manage A
> and D bit.
>
> So add a config for selecting, the default is true. For simple
> implementation riscv CPU which just generate page fault, unselect it.
>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> ---
> arch/riscv/Kconfig | 10 ++++++++++
> arch/riscv/include/asm/pgtable.h | 7 +++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..17c82885549c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> default 0x80000000 if 64BIT && !MMU
> default 0xff60000000000000 if 64BIT
>
> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> + bool "Hardware Set PTE Access Bit"
> + default y
> + help
> + Select if hardware set A bit when PTE is accessed. The default is
> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> + But RISC-V may have simple implementation that do not support
> + hardware set A bit but only generate page fault, for that case just
> + unselect it.
> +
> config KASAN_SHADOW_OFFSET
> hex
> depends on KASAN_GENERIC
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 4eba9a98d0e3..1db54ab4e1ba 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> */
> return ptep_test_and_clear_young(vma, address, ptep);
> }
> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> +static inline bool arch_has_hw_pte_young(void)
> +{
> + return true;
> +}
> +#endif
>
> #define pgprot_noncached pgprot_noncached
> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> --
> 2.30.2
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-01-30 8:22 ` Andrew Jones
0 siblings, 0 replies; 18+ messages in thread
From: Andrew Jones @ 2023-01-30 8:22 UTC (permalink / raw)
To: Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, guoren,
tongtiangen, anup, akpm, falcon, linux-riscv, linux-kernel
On Sun, Jan 29, 2023 at 02:49:56PM +0800, Jinyu Tang wrote:
> The arch_has_hw_pte_young() is false for riscv by default. If it's
> false, page table walk is almost skipped for MGLRU reclaim. And it
> will also cause useless step in __wp_page_copy_user().
>
> RISC-V Privileged Book says that riscv have two schemes to manage A
> and D bit.
>
> So add a config for selecting, the default is true. For simple
> implementation riscv CPU which just generate page fault, unselect it.
>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> ---
> arch/riscv/Kconfig | 10 ++++++++++
> arch/riscv/include/asm/pgtable.h | 7 +++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..17c82885549c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> default 0x80000000 if 64BIT && !MMU
> default 0xff60000000000000 if 64BIT
>
> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> + bool "Hardware Set PTE Access Bit"
> + default y
> + help
> + Select if hardware set A bit when PTE is accessed. The default is
> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> + But RISC-V may have simple implementation that do not support
> + hardware set A bit but only generate page fault, for that case just
> + unselect it.
> +
> config KASAN_SHADOW_OFFSET
> hex
> depends on KASAN_GENERIC
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 4eba9a98d0e3..1db54ab4e1ba 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> */
> return ptep_test_and_clear_young(vma, address, ptep);
> }
> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> +static inline bool arch_has_hw_pte_young(void)
> +{
> + return true;
> +}
> +#endif
>
> #define pgprot_noncached pgprot_noncached
> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> --
> 2.30.2
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
2023-01-29 6:49 ` Jinyu Tang
@ 2023-01-30 10:14 ` Conor Dooley
-1 siblings, 0 replies; 18+ messages in thread
From: Conor Dooley @ 2023-01-30 10:14 UTC (permalink / raw)
To: Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, ajones, guoren,
tongtiangen, anup, akpm, falcon, linux-riscv, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1592 bytes --]
On Sun, Jan 29, 2023 at 02:49:56PM +0800, Jinyu Tang wrote:
> The arch_has_hw_pte_young() is false for riscv by default. If it's
> false, page table walk is almost skipped for MGLRU reclaim. And it
> will also cause useless step in __wp_page_copy_user().
>
> RISC-V Privileged Book says that riscv have two schemes to manage A
> and D bit.
>
> So add a config for selecting, the default is true. For simple
> implementation riscv CPU which just generate page fault, unselect it.
>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> ---
> arch/riscv/Kconfig | 10 ++++++++++
> arch/riscv/include/asm/pgtable.h | 7 +++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..17c82885549c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> default 0x80000000 if 64BIT && !MMU
> default 0xff60000000000000 if 64BIT
>
> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> + bool "Hardware Set PTE Access Bit"
> + default y
> + help
> + Select if hardware set A bit when PTE is accessed. The default is
> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> + But RISC-V may have simple implementation that do not support
> + hardware set A bit but only generate page fault, for that case just
> + unselect it.
Hmm, I am not really sure if this is the right way to go. Should we
really be defaulting this option to enabled if there are going to be
implementations that do not support it?
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-01-30 10:14 ` Conor Dooley
0 siblings, 0 replies; 18+ messages in thread
From: Conor Dooley @ 2023-01-30 10:14 UTC (permalink / raw)
To: Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, ajones, guoren,
tongtiangen, anup, akpm, falcon, linux-riscv, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1592 bytes --]
On Sun, Jan 29, 2023 at 02:49:56PM +0800, Jinyu Tang wrote:
> The arch_has_hw_pte_young() is false for riscv by default. If it's
> false, page table walk is almost skipped for MGLRU reclaim. And it
> will also cause useless step in __wp_page_copy_user().
>
> RISC-V Privileged Book says that riscv have two schemes to manage A
> and D bit.
>
> So add a config for selecting, the default is true. For simple
> implementation riscv CPU which just generate page fault, unselect it.
>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> ---
> arch/riscv/Kconfig | 10 ++++++++++
> arch/riscv/include/asm/pgtable.h | 7 +++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..17c82885549c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> default 0x80000000 if 64BIT && !MMU
> default 0xff60000000000000 if 64BIT
>
> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> + bool "Hardware Set PTE Access Bit"
> + default y
> + help
> + Select if hardware set A bit when PTE is accessed. The default is
> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> + But RISC-V may have simple implementation that do not support
> + hardware set A bit but only generate page fault, for that case just
> + unselect it.
Hmm, I am not really sure if this is the right way to go. Should we
really be defaulting this option to enabled if there are going to be
implementations that do not support it?
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
2023-01-29 6:49 ` Jinyu Tang
@ 2023-01-30 10:25 ` Anup Patel
-1 siblings, 0 replies; 18+ messages in thread
From: Anup Patel @ 2023-01-30 10:25 UTC (permalink / raw)
To: Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, ajones,
guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel
On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote:
>
> The arch_has_hw_pte_young() is false for riscv by default. If it's
> false, page table walk is almost skipped for MGLRU reclaim. And it
> will also cause useless step in __wp_page_copy_user().
>
> RISC-V Privileged Book says that riscv have two schemes to manage A
> and D bit.
>
> So add a config for selecting, the default is true. For simple
> implementation riscv CPU which just generate page fault, unselect it.
I totally disagree with this approach.
Almost all existing RISC-V platforms don't have HW support
PTE.A and PTE.D updates.
We want the same kernel image to run HW with/without PTE.A
and PTE.D updates so kconfig based approach is not going to
fly.
>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> ---
> arch/riscv/Kconfig | 10 ++++++++++
> arch/riscv/include/asm/pgtable.h | 7 +++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..17c82885549c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> default 0x80000000 if 64BIT && !MMU
> default 0xff60000000000000 if 64BIT
>
> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> + bool "Hardware Set PTE Access Bit"
> + default y
> + help
> + Select if hardware set A bit when PTE is accessed. The default is
> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> + But RISC-V may have simple implementation that do not support
> + hardware set A bit but only generate page fault, for that case just
> + unselect it.
> +
> config KASAN_SHADOW_OFFSET
> hex
> depends on KASAN_GENERIC
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 4eba9a98d0e3..1db54ab4e1ba 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> */
> return ptep_test_and_clear_young(vma, address, ptep);
> }
> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> +static inline bool arch_has_hw_pte_young(void)
> +{
> + return true;
Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG
and instead use code patching to return true only when Svadu
ISA extension is available in DT ISA string.
> +}
> +#endif
>
> #define pgprot_noncached pgprot_noncached
> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> --
> 2.30.2
>
Regards,
Anup
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-01-30 10:25 ` Anup Patel
0 siblings, 0 replies; 18+ messages in thread
From: Anup Patel @ 2023-01-30 10:25 UTC (permalink / raw)
To: Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, ajones,
guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel
On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote:
>
> The arch_has_hw_pte_young() is false for riscv by default. If it's
> false, page table walk is almost skipped for MGLRU reclaim. And it
> will also cause useless step in __wp_page_copy_user().
>
> RISC-V Privileged Book says that riscv have two schemes to manage A
> and D bit.
>
> So add a config for selecting, the default is true. For simple
> implementation riscv CPU which just generate page fault, unselect it.
I totally disagree with this approach.
Almost all existing RISC-V platforms don't have HW support
PTE.A and PTE.D updates.
We want the same kernel image to run HW with/without PTE.A
and PTE.D updates so kconfig based approach is not going to
fly.
>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> ---
> arch/riscv/Kconfig | 10 ++++++++++
> arch/riscv/include/asm/pgtable.h | 7 +++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..17c82885549c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> default 0x80000000 if 64BIT && !MMU
> default 0xff60000000000000 if 64BIT
>
> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> + bool "Hardware Set PTE Access Bit"
> + default y
> + help
> + Select if hardware set A bit when PTE is accessed. The default is
> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> + But RISC-V may have simple implementation that do not support
> + hardware set A bit but only generate page fault, for that case just
> + unselect it.
> +
> config KASAN_SHADOW_OFFSET
> hex
> depends on KASAN_GENERIC
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 4eba9a98d0e3..1db54ab4e1ba 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> */
> return ptep_test_and_clear_young(vma, address, ptep);
> }
> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> +static inline bool arch_has_hw_pte_young(void)
> +{
> + return true;
Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG
and instead use code patching to return true only when Svadu
ISA extension is available in DT ISA string.
> +}
> +#endif
>
> #define pgprot_noncached pgprot_noncached
> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> --
> 2.30.2
>
Regards,
Anup
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
2023-01-30 10:25 ` Anup Patel
@ 2023-01-30 10:49 ` Andrew Jones
-1 siblings, 0 replies; 18+ messages in thread
From: Andrew Jones @ 2023-01-30 10:49 UTC (permalink / raw)
To: Anup Patel
Cc: Jinyu Tang, palmer, paul.walmsley, palmer, yuzhao, conor.dooley,
guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel
On Mon, Jan 30, 2023 at 03:55:55PM +0530, Anup Patel wrote:
> On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote:
> >
> > The arch_has_hw_pte_young() is false for riscv by default. If it's
> > false, page table walk is almost skipped for MGLRU reclaim. And it
> > will also cause useless step in __wp_page_copy_user().
> >
> > RISC-V Privileged Book says that riscv have two schemes to manage A
> > and D bit.
> >
> > So add a config for selecting, the default is true. For simple
> > implementation riscv CPU which just generate page fault, unselect it.
>
> I totally disagree with this approach.
>
> Almost all existing RISC-V platforms don't have HW support
> PTE.A and PTE.D updates.
>
> We want the same kernel image to run HW with/without PTE.A
> and PTE.D updates so kconfig based approach is not going to
> fly.
>
> >
> > Signed-off-by: Jinyu Tang <tjytimi@163.com>
> > ---
> > arch/riscv/Kconfig | 10 ++++++++++
> > arch/riscv/include/asm/pgtable.h | 7 +++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index e2b656043abf..17c82885549c 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -180,6 +180,16 @@ config PAGE_OFFSET
> > default 0x80000000 if 64BIT && !MMU
> > default 0xff60000000000000 if 64BIT
> >
> > +config ARCH_HAS_HARDWARE_PTE_YOUNG
> > + bool "Hardware Set PTE Access Bit"
> > + default y
> > + help
> > + Select if hardware set A bit when PTE is accessed. The default is
> > + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> > + But RISC-V may have simple implementation that do not support
> > + hardware set A bit but only generate page fault, for that case just
> > + unselect it.
> > +
> > config KASAN_SHADOW_OFFSET
> > hex
> > depends on KASAN_GENERIC
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 4eba9a98d0e3..1db54ab4e1ba 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> > */
> > return ptep_test_and_clear_young(vma, address, ptep);
> > }
> > +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
>
> > +#define arch_has_hw_pte_young arch_has_hw_pte_young
> > +static inline bool arch_has_hw_pte_young(void)
> > +{
> > + return true;
>
> Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG
> and instead use code patching to return true only when Svadu
> ISA extension is available in DT ISA string.
Indeed. I should have checked if there was an extension for this
first. It crossed my mind that we should only be enabling features
when the extensions are present, but looking at the privileged manual
isn't sufficient to learn about the Svadu extension. I should have
checked https://wiki.riscv.org/display/HOME/Specification+Status
Anyway, I retract my r-b and agree with Anup.
Thanks,
drew
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-01-30 10:49 ` Andrew Jones
0 siblings, 0 replies; 18+ messages in thread
From: Andrew Jones @ 2023-01-30 10:49 UTC (permalink / raw)
To: Anup Patel
Cc: Jinyu Tang, palmer, paul.walmsley, palmer, yuzhao, conor.dooley,
guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel
On Mon, Jan 30, 2023 at 03:55:55PM +0530, Anup Patel wrote:
> On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote:
> >
> > The arch_has_hw_pte_young() is false for riscv by default. If it's
> > false, page table walk is almost skipped for MGLRU reclaim. And it
> > will also cause useless step in __wp_page_copy_user().
> >
> > RISC-V Privileged Book says that riscv have two schemes to manage A
> > and D bit.
> >
> > So add a config for selecting, the default is true. For simple
> > implementation riscv CPU which just generate page fault, unselect it.
>
> I totally disagree with this approach.
>
> Almost all existing RISC-V platforms don't have HW support
> PTE.A and PTE.D updates.
>
> We want the same kernel image to run HW with/without PTE.A
> and PTE.D updates so kconfig based approach is not going to
> fly.
>
> >
> > Signed-off-by: Jinyu Tang <tjytimi@163.com>
> > ---
> > arch/riscv/Kconfig | 10 ++++++++++
> > arch/riscv/include/asm/pgtable.h | 7 +++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index e2b656043abf..17c82885549c 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -180,6 +180,16 @@ config PAGE_OFFSET
> > default 0x80000000 if 64BIT && !MMU
> > default 0xff60000000000000 if 64BIT
> >
> > +config ARCH_HAS_HARDWARE_PTE_YOUNG
> > + bool "Hardware Set PTE Access Bit"
> > + default y
> > + help
> > + Select if hardware set A bit when PTE is accessed. The default is
> > + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> > + But RISC-V may have simple implementation that do not support
> > + hardware set A bit but only generate page fault, for that case just
> > + unselect it.
> > +
> > config KASAN_SHADOW_OFFSET
> > hex
> > depends on KASAN_GENERIC
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 4eba9a98d0e3..1db54ab4e1ba 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> > */
> > return ptep_test_and_clear_young(vma, address, ptep);
> > }
> > +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
>
> > +#define arch_has_hw_pte_young arch_has_hw_pte_young
> > +static inline bool arch_has_hw_pte_young(void)
> > +{
> > + return true;
>
> Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG
> and instead use code patching to return true only when Svadu
> ISA extension is available in DT ISA string.
Indeed. I should have checked if there was an extension for this
first. It crossed my mind that we should only be enabling features
when the extensions are present, but looking at the privileged manual
isn't sufficient to learn about the Svadu extension. I should have
checked https://wiki.riscv.org/display/HOME/Specification+Status
Anyway, I retract my r-b and agree with Anup.
Thanks,
drew
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
2023-01-30 10:49 ` Andrew Jones
@ 2023-01-30 17:27 ` Jessica Clarke
-1 siblings, 0 replies; 18+ messages in thread
From: Jessica Clarke @ 2023-01-30 17:27 UTC (permalink / raw)
To: Andrew Jones
Cc: Anup Patel, Jinyu Tang, Palmer Dabbelt, Paul Walmsley,
Palmer Dabbelt, yuzhao, Conor Dooley, Guo Ren, tongtiangen,
Anup Patel, Andrew Morton, falcon, linux-riscv, linux-kernel
On 30 Jan 2023, at 10:49, Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Mon, Jan 30, 2023 at 03:55:55PM +0530, Anup Patel wrote:
>> On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote:
>>>
>>> The arch_has_hw_pte_young() is false for riscv by default. If it's
>>> false, page table walk is almost skipped for MGLRU reclaim. And it
>>> will also cause useless step in __wp_page_copy_user().
>>>
>>> RISC-V Privileged Book says that riscv have two schemes to manage A
>>> and D bit.
>>>
>>> So add a config for selecting, the default is true. For simple
>>> implementation riscv CPU which just generate page fault, unselect it.
>>
>> I totally disagree with this approach.
>>
>> Almost all existing RISC-V platforms don't have HW support
>> PTE.A and PTE.D updates.
>>
>> We want the same kernel image to run HW with/without PTE.A
>> and PTE.D updates so kconfig based approach is not going to
>> fly.
>>
>>>
>>> Signed-off-by: Jinyu Tang <tjytimi@163.com>
>>> ---
>>> arch/riscv/Kconfig | 10 ++++++++++
>>> arch/riscv/include/asm/pgtable.h | 7 +++++++
>>> 2 files changed, 17 insertions(+)
>>>
>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>> index e2b656043abf..17c82885549c 100644
>>> --- a/arch/riscv/Kconfig
>>> +++ b/arch/riscv/Kconfig
>>> @@ -180,6 +180,16 @@ config PAGE_OFFSET
>>> default 0x80000000 if 64BIT && !MMU
>>> default 0xff60000000000000 if 64BIT
>>>
>>> +config ARCH_HAS_HARDWARE_PTE_YOUNG
>>> + bool "Hardware Set PTE Access Bit"
>>> + default y
>>> + help
>>> + Select if hardware set A bit when PTE is accessed. The default is
>>> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
>>> + But RISC-V may have simple implementation that do not support
>>> + hardware set A bit but only generate page fault, for that case just
>>> + unselect it.
>>> +
>>> config KASAN_SHADOW_OFFSET
>>> hex
>>> depends on KASAN_GENERIC
>>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>>> index 4eba9a98d0e3..1db54ab4e1ba 100644
>>> --- a/arch/riscv/include/asm/pgtable.h
>>> +++ b/arch/riscv/include/asm/pgtable.h
>>> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
>>> */
>>> return ptep_test_and_clear_young(vma, address, ptep);
>>> }
>>> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
>>
>>> +#define arch_has_hw_pte_young arch_has_hw_pte_young
>>> +static inline bool arch_has_hw_pte_young(void)
>>> +{
>>> + return true;
>>
>> Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG
>> and instead use code patching to return true only when Svadu
>> ISA extension is available in DT ISA string.
>
> Indeed. I should have checked if there was an extension for this
> first. It crossed my mind that we should only be enabling features
> when the extensions are present, but looking at the privileged manual
> isn't sufficient to learn about the Svadu extension. I should have
> checked https://wiki.riscv.org/display/HOME/Specification+Status
>
> Anyway, I retract my r-b and agree with Anup.
Svadu is a bit of a mess, for years it’s been legal to implement
hardware A/D tracking and such implementations exist (it’s what QEMU
has done for many years, and I know of an FPGA-based implementation
that does it too), yet RVA20S64 outlaws that by requiring what it calls
Ssptead and Svadu gets introduced to re-allow that behaviour gated
behind a CSR bit.
Jess
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-01-30 17:27 ` Jessica Clarke
0 siblings, 0 replies; 18+ messages in thread
From: Jessica Clarke @ 2023-01-30 17:27 UTC (permalink / raw)
To: Andrew Jones
Cc: Anup Patel, Jinyu Tang, Palmer Dabbelt, Paul Walmsley,
Palmer Dabbelt, yuzhao, Conor Dooley, Guo Ren, tongtiangen,
Anup Patel, Andrew Morton, falcon, linux-riscv, linux-kernel
On 30 Jan 2023, at 10:49, Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Mon, Jan 30, 2023 at 03:55:55PM +0530, Anup Patel wrote:
>> On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote:
>>>
>>> The arch_has_hw_pte_young() is false for riscv by default. If it's
>>> false, page table walk is almost skipped for MGLRU reclaim. And it
>>> will also cause useless step in __wp_page_copy_user().
>>>
>>> RISC-V Privileged Book says that riscv have two schemes to manage A
>>> and D bit.
>>>
>>> So add a config for selecting, the default is true. For simple
>>> implementation riscv CPU which just generate page fault, unselect it.
>>
>> I totally disagree with this approach.
>>
>> Almost all existing RISC-V platforms don't have HW support
>> PTE.A and PTE.D updates.
>>
>> We want the same kernel image to run HW with/without PTE.A
>> and PTE.D updates so kconfig based approach is not going to
>> fly.
>>
>>>
>>> Signed-off-by: Jinyu Tang <tjytimi@163.com>
>>> ---
>>> arch/riscv/Kconfig | 10 ++++++++++
>>> arch/riscv/include/asm/pgtable.h | 7 +++++++
>>> 2 files changed, 17 insertions(+)
>>>
>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>> index e2b656043abf..17c82885549c 100644
>>> --- a/arch/riscv/Kconfig
>>> +++ b/arch/riscv/Kconfig
>>> @@ -180,6 +180,16 @@ config PAGE_OFFSET
>>> default 0x80000000 if 64BIT && !MMU
>>> default 0xff60000000000000 if 64BIT
>>>
>>> +config ARCH_HAS_HARDWARE_PTE_YOUNG
>>> + bool "Hardware Set PTE Access Bit"
>>> + default y
>>> + help
>>> + Select if hardware set A bit when PTE is accessed. The default is
>>> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
>>> + But RISC-V may have simple implementation that do not support
>>> + hardware set A bit but only generate page fault, for that case just
>>> + unselect it.
>>> +
>>> config KASAN_SHADOW_OFFSET
>>> hex
>>> depends on KASAN_GENERIC
>>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>>> index 4eba9a98d0e3..1db54ab4e1ba 100644
>>> --- a/arch/riscv/include/asm/pgtable.h
>>> +++ b/arch/riscv/include/asm/pgtable.h
>>> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
>>> */
>>> return ptep_test_and_clear_young(vma, address, ptep);
>>> }
>>> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
>>
>>> +#define arch_has_hw_pte_young arch_has_hw_pte_young
>>> +static inline bool arch_has_hw_pte_young(void)
>>> +{
>>> + return true;
>>
>> Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG
>> and instead use code patching to return true only when Svadu
>> ISA extension is available in DT ISA string.
>
> Indeed. I should have checked if there was an extension for this
> first. It crossed my mind that we should only be enabling features
> when the extensions are present, but looking at the privileged manual
> isn't sufficient to learn about the Svadu extension. I should have
> checked https://wiki.riscv.org/display/HOME/Specification+Status
>
> Anyway, I retract my r-b and agree with Anup.
Svadu is a bit of a mess, for years it’s been legal to implement
hardware A/D tracking and such implementations exist (it’s what QEMU
has done for many years, and I know of an FPGA-based implementation
that does it too), yet RVA20S64 outlaws that by requiring what it calls
Ssptead and Svadu gets introduced to re-allow that behaviour gated
behind a CSR bit.
Jess
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
2023-01-29 6:49 ` Jinyu Tang
@ 2023-08-25 5:42 ` Yong-Xuan Wang
-1 siblings, 0 replies; 18+ messages in thread
From: Yong-Xuan Wang @ 2023-08-25 5:42 UTC (permalink / raw)
To: Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, ajones,
guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel, Greentime Hu, Vincent Chen
Hi Jinyu,
It seems like it has been a while since the last release of this patch. Do
you have any plans for the patch recently? Or, do you mind sharing any
internal progress on the patch?
We are starting to work on the Svadu extension of pte A/D bit feature on
Linux. Do you find any places where we may potentially work together to
get things moving? Also, I am willing to base on top of your work and
continue sending the series (by keeping all the credits from the original
work)
Please let me know if you have any thoughts, thanks :)
Regards,
Yong-Xuan
On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote:
>
> The arch_has_hw_pte_young() is false for riscv by default. If it's
> false, page table walk is almost skipped for MGLRU reclaim. And it
> will also cause useless step in __wp_page_copy_user().
>
> RISC-V Privileged Book says that riscv have two schemes to manage A
> and D bit.
>
> So add a config for selecting, the default is true. For simple
> implementation riscv CPU which just generate page fault, unselect it.
>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> ---
> arch/riscv/Kconfig | 10 ++++++++++
> arch/riscv/include/asm/pgtable.h | 7 +++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..17c82885549c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> default 0x80000000 if 64BIT && !MMU
> default 0xff60000000000000 if 64BIT
>
> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> + bool "Hardware Set PTE Access Bit"
> + default y
> + help
> + Select if hardware set A bit when PTE is accessed. The default is
> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> + But RISC-V may have simple implementation that do not support
> + hardware set A bit but only generate page fault, for that case just
> + unselect it.
> +
> config KASAN_SHADOW_OFFSET
> hex
> depends on KASAN_GENERIC
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 4eba9a98d0e3..1db54ab4e1ba 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> */
> return ptep_test_and_clear_young(vma, address, ptep);
> }
> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> +static inline bool arch_has_hw_pte_young(void)
> +{
> + return true;
> +}
> +#endif
>
> #define pgprot_noncached pgprot_noncached
> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> --
> 2.30.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-08-25 5:42 ` Yong-Xuan Wang
0 siblings, 0 replies; 18+ messages in thread
From: Yong-Xuan Wang @ 2023-08-25 5:42 UTC (permalink / raw)
To: Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, ajones,
guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel, Greentime Hu, Vincent Chen
Hi Jinyu,
It seems like it has been a while since the last release of this patch. Do
you have any plans for the patch recently? Or, do you mind sharing any
internal progress on the patch?
We are starting to work on the Svadu extension of pte A/D bit feature on
Linux. Do you find any places where we may potentially work together to
get things moving? Also, I am willing to base on top of your work and
continue sending the series (by keeping all the credits from the original
work)
Please let me know if you have any thoughts, thanks :)
Regards,
Yong-Xuan
On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote:
>
> The arch_has_hw_pte_young() is false for riscv by default. If it's
> false, page table walk is almost skipped for MGLRU reclaim. And it
> will also cause useless step in __wp_page_copy_user().
>
> RISC-V Privileged Book says that riscv have two schemes to manage A
> and D bit.
>
> So add a config for selecting, the default is true. For simple
> implementation riscv CPU which just generate page fault, unselect it.
>
> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> ---
> arch/riscv/Kconfig | 10 ++++++++++
> arch/riscv/include/asm/pgtable.h | 7 +++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..17c82885549c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> default 0x80000000 if 64BIT && !MMU
> default 0xff60000000000000 if 64BIT
>
> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> + bool "Hardware Set PTE Access Bit"
> + default y
> + help
> + Select if hardware set A bit when PTE is accessed. The default is
> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> + But RISC-V may have simple implementation that do not support
> + hardware set A bit but only generate page fault, for that case just
> + unselect it.
> +
> config KASAN_SHADOW_OFFSET
> hex
> depends on KASAN_GENERIC
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 4eba9a98d0e3..1db54ab4e1ba 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> */
> return ptep_test_and_clear_young(vma, address, ptep);
> }
> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> +static inline bool arch_has_hw_pte_young(void)
> +{
> + return true;
> +}
> +#endif
>
> #define pgprot_noncached pgprot_noncached
> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> --
> 2.30.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
2023-08-25 5:42 ` Yong-Xuan Wang
@ 2023-08-25 19:39 ` Alexandre Ghiti
-1 siblings, 0 replies; 18+ messages in thread
From: Alexandre Ghiti @ 2023-08-25 19:39 UTC (permalink / raw)
To: Yong-Xuan Wang, Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, ajones,
guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel, Greentime Hu, Vincent Chen
Hi Yong-Xuan,
On 25/08/2023 07:42, Yong-Xuan Wang wrote:
> Hi Jinyu,
>
> It seems like it has been a while since the last release of this patch. Do
> you have any plans for the patch recently? Or, do you mind sharing any
> internal progress on the patch?
>
> We are starting to work on the Svadu extension of pte A/D bit feature on
> Linux.
This task was assigned to me on the RISE kernel spreadsheet, if you
indeed take over, I'll change it to your name: any objection?
Thanks,
Alex
> Do you find any places where we may potentially work together to
> get things moving? Also, I am willing to base on top of your work and
> continue sending the series (by keeping all the credits from the original
> work)
>
> Please let me know if you have any thoughts, thanks :)
>
> Regards,
> Yong-Xuan
>
> On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote:
>> The arch_has_hw_pte_young() is false for riscv by default. If it's
>> false, page table walk is almost skipped for MGLRU reclaim. And it
>> will also cause useless step in __wp_page_copy_user().
>>
>> RISC-V Privileged Book says that riscv have two schemes to manage A
>> and D bit.
>>
>> So add a config for selecting, the default is true. For simple
>> implementation riscv CPU which just generate page fault, unselect it.
>>
>> Signed-off-by: Jinyu Tang <tjytimi@163.com>
>> ---
>> arch/riscv/Kconfig | 10 ++++++++++
>> arch/riscv/include/asm/pgtable.h | 7 +++++++
>> 2 files changed, 17 insertions(+)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index e2b656043abf..17c82885549c 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -180,6 +180,16 @@ config PAGE_OFFSET
>> default 0x80000000 if 64BIT && !MMU
>> default 0xff60000000000000 if 64BIT
>>
>> +config ARCH_HAS_HARDWARE_PTE_YOUNG
>> + bool "Hardware Set PTE Access Bit"
>> + default y
>> + help
>> + Select if hardware set A bit when PTE is accessed. The default is
>> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
>> + But RISC-V may have simple implementation that do not support
>> + hardware set A bit but only generate page fault, for that case just
>> + unselect it.
>> +
>> config KASAN_SHADOW_OFFSET
>> hex
>> depends on KASAN_GENERIC
>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>> index 4eba9a98d0e3..1db54ab4e1ba 100644
>> --- a/arch/riscv/include/asm/pgtable.h
>> +++ b/arch/riscv/include/asm/pgtable.h
>> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
>> */
>> return ptep_test_and_clear_young(vma, address, ptep);
>> }
>> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
>> +#define arch_has_hw_pte_young arch_has_hw_pte_young
>> +static inline bool arch_has_hw_pte_young(void)
>> +{
>> + return true;
>> +}
>> +#endif
>>
>> #define pgprot_noncached pgprot_noncached
>> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
>> --
>> 2.30.2
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-08-25 19:39 ` Alexandre Ghiti
0 siblings, 0 replies; 18+ messages in thread
From: Alexandre Ghiti @ 2023-08-25 19:39 UTC (permalink / raw)
To: Yong-Xuan Wang, Jinyu Tang
Cc: palmer, paul.walmsley, palmer, yuzhao, conor.dooley, ajones,
guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel, Greentime Hu, Vincent Chen
Hi Yong-Xuan,
On 25/08/2023 07:42, Yong-Xuan Wang wrote:
> Hi Jinyu,
>
> It seems like it has been a while since the last release of this patch. Do
> you have any plans for the patch recently? Or, do you mind sharing any
> internal progress on the patch?
>
> We are starting to work on the Svadu extension of pte A/D bit feature on
> Linux.
This task was assigned to me on the RISE kernel spreadsheet, if you
indeed take over, I'll change it to your name: any objection?
Thanks,
Alex
> Do you find any places where we may potentially work together to
> get things moving? Also, I am willing to base on top of your work and
> continue sending the series (by keeping all the credits from the original
> work)
>
> Please let me know if you have any thoughts, thanks :)
>
> Regards,
> Yong-Xuan
>
> On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote:
>> The arch_has_hw_pte_young() is false for riscv by default. If it's
>> false, page table walk is almost skipped for MGLRU reclaim. And it
>> will also cause useless step in __wp_page_copy_user().
>>
>> RISC-V Privileged Book says that riscv have two schemes to manage A
>> and D bit.
>>
>> So add a config for selecting, the default is true. For simple
>> implementation riscv CPU which just generate page fault, unselect it.
>>
>> Signed-off-by: Jinyu Tang <tjytimi@163.com>
>> ---
>> arch/riscv/Kconfig | 10 ++++++++++
>> arch/riscv/include/asm/pgtable.h | 7 +++++++
>> 2 files changed, 17 insertions(+)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index e2b656043abf..17c82885549c 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -180,6 +180,16 @@ config PAGE_OFFSET
>> default 0x80000000 if 64BIT && !MMU
>> default 0xff60000000000000 if 64BIT
>>
>> +config ARCH_HAS_HARDWARE_PTE_YOUNG
>> + bool "Hardware Set PTE Access Bit"
>> + default y
>> + help
>> + Select if hardware set A bit when PTE is accessed. The default is
>> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
>> + But RISC-V may have simple implementation that do not support
>> + hardware set A bit but only generate page fault, for that case just
>> + unselect it.
>> +
>> config KASAN_SHADOW_OFFSET
>> hex
>> depends on KASAN_GENERIC
>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>> index 4eba9a98d0e3..1db54ab4e1ba 100644
>> --- a/arch/riscv/include/asm/pgtable.h
>> +++ b/arch/riscv/include/asm/pgtable.h
>> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
>> */
>> return ptep_test_and_clear_young(vma, address, ptep);
>> }
>> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
>> +#define arch_has_hw_pte_young arch_has_hw_pte_young
>> +static inline bool arch_has_hw_pte_young(void)
>> +{
>> + return true;
>> +}
>> +#endif
>>
>> #define pgprot_noncached pgprot_noncached
>> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
>> --
>> 2.30.2
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
2023-08-25 19:39 ` Alexandre Ghiti
@ 2023-08-28 7:26 ` Yong-Xuan Wang
-1 siblings, 0 replies; 18+ messages in thread
From: Yong-Xuan Wang @ 2023-08-28 7:26 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Jinyu Tang, palmer, paul.walmsley, palmer, yuzhao, conor.dooley,
ajones, guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel, Greentime Hu, Vincent Chen
Hi Alex,
On Sat, Aug 26, 2023 at 3:39 AM Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> Hi Yong-Xuan,
>
>
> On 25/08/2023 07:42, Yong-Xuan Wang wrote:
> > Hi Jinyu,
> >
> > It seems like it has been a while since the last release of this patch. Do
> > you have any plans for the patch recently? Or, do you mind sharing any
> > internal progress on the patch?
> >
> > We are starting to work on the Svadu extension of pte A/D bit feature on
> > Linux.
>
>
> This task was assigned to me on the RISE kernel spreadsheet, if you
> indeed take over, I'll change it to your name: any objection?
>
>
Yes, that's fine with me. Thank you!
Regards,
Yong-Xuan
> Thanks,
>
>
> Alex
>
>
> > Do you find any places where we may potentially work together to
> > get things moving? Also, I am willing to base on top of your work and
> > continue sending the series (by keeping all the credits from the original
> > work)
> >
> > Please let me know if you have any thoughts, thanks :)
> >
> > Regards,
> > Yong-Xuan
> >
> > On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote:
> >> The arch_has_hw_pte_young() is false for riscv by default. If it's
> >> false, page table walk is almost skipped for MGLRU reclaim. And it
> >> will also cause useless step in __wp_page_copy_user().
> >>
> >> RISC-V Privileged Book says that riscv have two schemes to manage A
> >> and D bit.
> >>
> >> So add a config for selecting, the default is true. For simple
> >> implementation riscv CPU which just generate page fault, unselect it.
> >>
> >> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> >> ---
> >> arch/riscv/Kconfig | 10 ++++++++++
> >> arch/riscv/include/asm/pgtable.h | 7 +++++++
> >> 2 files changed, 17 insertions(+)
> >>
> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >> index e2b656043abf..17c82885549c 100644
> >> --- a/arch/riscv/Kconfig
> >> +++ b/arch/riscv/Kconfig
> >> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> >> default 0x80000000 if 64BIT && !MMU
> >> default 0xff60000000000000 if 64BIT
> >>
> >> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> >> + bool "Hardware Set PTE Access Bit"
> >> + default y
> >> + help
> >> + Select if hardware set A bit when PTE is accessed. The default is
> >> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> >> + But RISC-V may have simple implementation that do not support
> >> + hardware set A bit but only generate page fault, for that case just
> >> + unselect it.
> >> +
> >> config KASAN_SHADOW_OFFSET
> >> hex
> >> depends on KASAN_GENERIC
> >> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> >> index 4eba9a98d0e3..1db54ab4e1ba 100644
> >> --- a/arch/riscv/include/asm/pgtable.h
> >> +++ b/arch/riscv/include/asm/pgtable.h
> >> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> >> */
> >> return ptep_test_and_clear_young(vma, address, ptep);
> >> }
> >> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
> >> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> >> +static inline bool arch_has_hw_pte_young(void)
> >> +{
> >> + return true;
> >> +}
> >> +#endif
> >>
> >> #define pgprot_noncached pgprot_noncached
> >> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> >> --
> >> 2.30.2
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1] riscv: support arch_has_hw_pte_young()
@ 2023-08-28 7:26 ` Yong-Xuan Wang
0 siblings, 0 replies; 18+ messages in thread
From: Yong-Xuan Wang @ 2023-08-28 7:26 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Jinyu Tang, palmer, paul.walmsley, palmer, yuzhao, conor.dooley,
ajones, guoren, tongtiangen, anup, akpm, falcon, linux-riscv,
linux-kernel, Greentime Hu, Vincent Chen
Hi Alex,
On Sat, Aug 26, 2023 at 3:39 AM Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> Hi Yong-Xuan,
>
>
> On 25/08/2023 07:42, Yong-Xuan Wang wrote:
> > Hi Jinyu,
> >
> > It seems like it has been a while since the last release of this patch. Do
> > you have any plans for the patch recently? Or, do you mind sharing any
> > internal progress on the patch?
> >
> > We are starting to work on the Svadu extension of pte A/D bit feature on
> > Linux.
>
>
> This task was assigned to me on the RISE kernel spreadsheet, if you
> indeed take over, I'll change it to your name: any objection?
>
>
Yes, that's fine with me. Thank you!
Regards,
Yong-Xuan
> Thanks,
>
>
> Alex
>
>
> > Do you find any places where we may potentially work together to
> > get things moving? Also, I am willing to base on top of your work and
> > continue sending the series (by keeping all the credits from the original
> > work)
> >
> > Please let me know if you have any thoughts, thanks :)
> >
> > Regards,
> > Yong-Xuan
> >
> > On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote:
> >> The arch_has_hw_pte_young() is false for riscv by default. If it's
> >> false, page table walk is almost skipped for MGLRU reclaim. And it
> >> will also cause useless step in __wp_page_copy_user().
> >>
> >> RISC-V Privileged Book says that riscv have two schemes to manage A
> >> and D bit.
> >>
> >> So add a config for selecting, the default is true. For simple
> >> implementation riscv CPU which just generate page fault, unselect it.
> >>
> >> Signed-off-by: Jinyu Tang <tjytimi@163.com>
> >> ---
> >> arch/riscv/Kconfig | 10 ++++++++++
> >> arch/riscv/include/asm/pgtable.h | 7 +++++++
> >> 2 files changed, 17 insertions(+)
> >>
> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >> index e2b656043abf..17c82885549c 100644
> >> --- a/arch/riscv/Kconfig
> >> +++ b/arch/riscv/Kconfig
> >> @@ -180,6 +180,16 @@ config PAGE_OFFSET
> >> default 0x80000000 if 64BIT && !MMU
> >> default 0xff60000000000000 if 64BIT
> >>
> >> +config ARCH_HAS_HARDWARE_PTE_YOUNG
> >> + bool "Hardware Set PTE Access Bit"
> >> + default y
> >> + help
> >> + Select if hardware set A bit when PTE is accessed. The default is
> >> + 'Y', because most RISC-V CPU hardware can manage A and D bit.
> >> + But RISC-V may have simple implementation that do not support
> >> + hardware set A bit but only generate page fault, for that case just
> >> + unselect it.
> >> +
> >> config KASAN_SHADOW_OFFSET
> >> hex
> >> depends on KASAN_GENERIC
> >> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> >> index 4eba9a98d0e3..1db54ab4e1ba 100644
> >> --- a/arch/riscv/include/asm/pgtable.h
> >> +++ b/arch/riscv/include/asm/pgtable.h
> >> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> >> */
> >> return ptep_test_and_clear_young(vma, address, ptep);
> >> }
> >> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG
> >> +#define arch_has_hw_pte_young arch_has_hw_pte_young
> >> +static inline bool arch_has_hw_pte_young(void)
> >> +{
> >> + return true;
> >> +}
> >> +#endif
> >>
> >> #define pgprot_noncached pgprot_noncached
> >> static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> >> --
> >> 2.30.2
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread