From: Conor Dooley <conor.dooley@microchip.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v4 13/14] RISC-V: KVM: Support firmware events
Date: Thu, 2 Feb 2023 11:40:58 +0000 [thread overview]
Message-ID: <Y9uhSoOvodeQRO6G@wendy> (raw)
In-Reply-To: <20230201231250.3806412-14-atishp@rivosinc.com>
Hey Atish,
On Wed, Feb 01, 2023 at 03:12:49PM -0800, Atish Patra wrote:
> SBI PMU extension defines a set of firmware events which can provide
> useful information to guests about the number of SBI calls. As
> hypervisor implements the SBI PMU extension, these firmware events
> correspond to ecall invocations between VS->HS mode. All other firmware
> events will always report zero if monitored as KVM doesn't implement them.
>
> This patch adds all the infrastructure required to support firmware
> events.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
> index 473ad80..dd16e60 100644
> --- a/arch/riscv/kvm/vcpu_pmu.c
> +++ b/arch/riscv/kvm/vcpu_pmu.c
> @@ -202,12 +202,15 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
> struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
> struct kvm_pmc *pmc;
> u64 enabled, running;
> + int fevent_code;
>
> pmc = &kvpmu->pmc[cidx];
> - if (!pmc->perf_event)
> - return -EINVAL;
>
> - pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
> + if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
> + fevent_code = get_event_code(pmc->event_idx);
> + pmc->counter_val = kvpmu->fw_event[fevent_code].value;
> + } else if (pmc->perf_event)
> + pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
Here, and elsewhere, all branches of an if/else must use {} if one
branch needs them.
Patches 4 & 12 have similar issues, which checkpatch in the patchwork
CI stuff also complained about.
Thanks,
Conor.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 228 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/kvm-riscv/attachments/20230202/6bf08187/attachment-0001.sig>
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: <linux-kernel@vger.kernel.org>, Anup Patel <anup@brainfault.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Eric Lin <eric.lin@sifive.com>, Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko@sntech.de>, <kvm-riscv@lists.infradead.org>,
<kvm@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH v4 13/14] RISC-V: KVM: Support firmware events
Date: Thu, 2 Feb 2023 11:40:58 +0000 [thread overview]
Message-ID: <Y9uhSoOvodeQRO6G@wendy> (raw)
In-Reply-To: <20230201231250.3806412-14-atishp@rivosinc.com>
[-- Attachment #1.1: Type: text/plain, Size: 1688 bytes --]
Hey Atish,
On Wed, Feb 01, 2023 at 03:12:49PM -0800, Atish Patra wrote:
> SBI PMU extension defines a set of firmware events which can provide
> useful information to guests about the number of SBI calls. As
> hypervisor implements the SBI PMU extension, these firmware events
> correspond to ecall invocations between VS->HS mode. All other firmware
> events will always report zero if monitored as KVM doesn't implement them.
>
> This patch adds all the infrastructure required to support firmware
> events.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
> index 473ad80..dd16e60 100644
> --- a/arch/riscv/kvm/vcpu_pmu.c
> +++ b/arch/riscv/kvm/vcpu_pmu.c
> @@ -202,12 +202,15 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
> struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
> struct kvm_pmc *pmc;
> u64 enabled, running;
> + int fevent_code;
>
> pmc = &kvpmu->pmc[cidx];
> - if (!pmc->perf_event)
> - return -EINVAL;
>
> - pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
> + if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
> + fevent_code = get_event_code(pmc->event_idx);
> + pmc->counter_val = kvpmu->fw_event[fevent_code].value;
> + } else if (pmc->perf_event)
> + pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
Here, and elsewhere, all branches of an if/else must use {} if one
branch needs them.
Patches 4 & 12 have similar issues, which checkpatch in the patchwork
CI stuff also complained about.
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: <linux-kernel@vger.kernel.org>, Anup Patel <anup@brainfault.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Eric Lin <eric.lin@sifive.com>, Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko@sntech.de>, <kvm-riscv@lists.infradead.org>,
<kvm@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH v4 13/14] RISC-V: KVM: Support firmware events
Date: Thu, 2 Feb 2023 11:40:58 +0000 [thread overview]
Message-ID: <Y9uhSoOvodeQRO6G@wendy> (raw)
In-Reply-To: <20230201231250.3806412-14-atishp@rivosinc.com>
[-- Attachment #1: Type: text/plain, Size: 1688 bytes --]
Hey Atish,
On Wed, Feb 01, 2023 at 03:12:49PM -0800, Atish Patra wrote:
> SBI PMU extension defines a set of firmware events which can provide
> useful information to guests about the number of SBI calls. As
> hypervisor implements the SBI PMU extension, these firmware events
> correspond to ecall invocations between VS->HS mode. All other firmware
> events will always report zero if monitored as KVM doesn't implement them.
>
> This patch adds all the infrastructure required to support firmware
> events.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
> index 473ad80..dd16e60 100644
> --- a/arch/riscv/kvm/vcpu_pmu.c
> +++ b/arch/riscv/kvm/vcpu_pmu.c
> @@ -202,12 +202,15 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
> struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
> struct kvm_pmc *pmc;
> u64 enabled, running;
> + int fevent_code;
>
> pmc = &kvpmu->pmc[cidx];
> - if (!pmc->perf_event)
> - return -EINVAL;
>
> - pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
> + if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
> + fevent_code = get_event_code(pmc->event_idx);
> + pmc->counter_val = kvpmu->fw_event[fevent_code].value;
> + } else if (pmc->perf_event)
> + pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
Here, and elsewhere, all branches of an if/else must use {} if one
branch needs them.
Patches 4 & 12 have similar issues, which checkpatch in the patchwork
CI stuff also complained about.
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2023-02-02 11:40 UTC|newest]
Thread overview: 126+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-01 23:12 [PATCH v4 00/14] KVM perf support Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` [PATCH v4 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 14:59 ` Andrew Jones
2023-02-02 14:59 ` Andrew Jones
2023-02-02 14:59 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 02/14] perf: RISC-V: Improve privilege mode filtering for perf Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` [PATCH v4 03/14] RISC-V: Improve SBI PMU extension related definitions Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 4:00 ` Anup Patel
2023-02-02 4:00 ` Anup Patel
2023-02-02 4:00 ` Anup Patel
2023-02-02 15:01 ` Andrew Jones
2023-02-02 15:01 ` Andrew Jones
2023-02-02 15:01 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 15:14 ` Andrew Jones
2023-02-02 15:14 ` Andrew Jones
2023-02-02 15:14 ` Andrew Jones
2023-02-02 15:16 ` Andrew Jones
2023-02-02 15:16 ` Andrew Jones
2023-02-02 15:16 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 05/14] RISC-V: KVM: Return correct code for hsm stop function Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 15:26 ` Andrew Jones
2023-02-02 15:26 ` Andrew Jones
2023-02-02 15:26 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 4:01 ` Anup Patel
2023-02-02 4:01 ` Anup Patel
2023-02-02 4:01 ` Anup Patel
2023-02-02 8:52 ` Anup Patel
2023-02-02 8:52 ` Anup Patel
2023-02-02 8:52 ` Anup Patel
2023-02-02 15:56 ` Andrew Jones
2023-02-02 15:56 ` Andrew Jones
2023-02-02 15:56 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 07/14] RISC-V: KVM: Add skeleton support for perf Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 4:02 ` Anup Patel
2023-02-02 4:02 ` Anup Patel
2023-02-02 4:02 ` Anup Patel
2023-02-02 11:33 ` Conor Dooley
2023-02-02 11:33 ` Conor Dooley
2023-02-02 11:33 ` Conor Dooley
2023-02-03 8:04 ` Atish Patra
2023-02-03 8:04 ` Atish Patra
2023-02-03 8:04 ` Atish Patra
2023-02-03 8:08 ` Conor Dooley
2023-02-03 8:08 ` Conor Dooley
2023-02-03 8:08 ` Conor Dooley
2023-02-02 17:03 ` Andrew Jones
2023-02-02 17:03 ` Andrew Jones
2023-02-02 17:03 ` Andrew Jones
2023-02-03 8:47 ` Atish Patra
2023-02-03 8:47 ` Atish Patra
2023-02-03 8:47 ` Atish Patra
2023-02-05 7:37 ` Atish Patra
2023-02-05 7:37 ` Atish Patra
2023-02-05 7:37 ` Atish Patra
2023-02-06 9:22 ` Andrew Jones
2023-02-06 9:22 ` Andrew Jones
2023-02-06 9:22 ` Andrew Jones
2023-02-06 11:39 ` Andrew Jones
2023-02-06 11:39 ` Andrew Jones
2023-02-06 11:39 ` Andrew Jones
2023-02-07 9:20 ` Atish Patra
2023-02-07 9:20 ` Atish Patra
2023-02-07 9:20 ` Atish Patra
2023-02-01 23:12 ` [PATCH v4 08/14] RISC-V: KVM: Add SBI PMU extension support Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 7:52 ` Conor Dooley
2023-02-02 7:52 ` Conor Dooley
2023-02-02 7:52 ` Conor Dooley
2023-02-02 17:29 ` Andrew Jones
2023-02-02 17:29 ` Andrew Jones
2023-02-02 17:29 ` Andrew Jones
2023-02-03 9:07 ` Atish Patra
2023-02-03 9:07 ` Atish Patra
2023-02-03 9:07 ` Atish Patra
2023-02-01 23:12 ` [PATCH v4 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 17:30 ` Andrew Jones
2023-02-02 17:30 ` Andrew Jones
2023-02-02 17:30 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` [PATCH v4 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` [PATCH v4 12/14] RISC-V: KVM: Implement perf support without sampling Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 18:44 ` Andrew Jones
2023-02-02 18:44 ` Andrew Jones
2023-02-02 18:44 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 13/14] RISC-V: KVM: Support firmware events Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 11:40 ` Conor Dooley [this message]
2023-02-02 11:40 ` Conor Dooley
2023-02-02 11:40 ` Conor Dooley
2023-02-03 10:14 ` Andrew Jones
2023-02-03 10:14 ` Andrew Jones
2023-02-03 10:14 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 14/14] RISC-V: KVM: Increment firmware pmu events Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-01 23:12 ` Atish Patra
2023-02-02 18:48 ` Andrew Jones
2023-02-02 18:48 ` Andrew Jones
2023-02-02 18:48 ` Andrew Jones
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y9uhSoOvodeQRO6G@wendy \
--to=conor.dooley@microchip.com \
--cc=kvm-riscv@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.