* [PATCH v9 0/2] perf vendor events: Support PMU events for A64FX @ 2021-03-08 10:53 ` Shunsuke Nakamura 0 siblings, 0 replies; 10+ messages in thread From: Shunsuke Nakamura @ 2021-03-08 10:53 UTC (permalink / raw) To: john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung Cc: linux-arm-kernel, linux-kernel This patch series supports A64FX PMU event v1.2. The first patch add more common and microarchitecture events. This patch is based on john's patch [1]. The second patch adds PMU events for A64FX. Changes in v8: - Merge 'perf vendor events arm64: Add Fujitsu A64FX pmu event' and 'perf vendor events arm64: Add "_" to the event name, which starts with a number' Changes in v7: - Rename an event name that starts with a number. - Drop 'perf tools: Add lexical definition of event name'. - Drop 'perf test: Add test for event name starting with a number'. Changes in v6: - Add test to the second patch. - Add Acked-by tag to the third patch. - Add Reviewed-by tag to the third patch. Changes in v5: - Removed john's patch [1] from this patch series. - Added the missing Reviewed-by tag to the patch. - Fixed the base of the patch series.[2] - Changed subject from fix to added. Changes in v4: - Add arm64 to the subjects of the second and fourth patches. - Add reference URLs to the body of the second patch. Changes in v3: - Add linux-arm-kernel mailing list to cc. Changes in v2: - Added armv8-common-and-microarch based on John's patch.[1] - Fixed A64FX Json to refer to standard events in armv8-common-and-microarch. [1] https://lore.kernel.org/lkml/1611835236-34696-3-git-send-email-john.garry@huawei.com/ [2] https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core Shunsuke Nakamura (2): perf vendor events arm64: Add more common and uarch events perf vendor events arm64: Add Fujitsu A64FX pmu event .../arm64/armv8-common-and-microarch.json | 228 ++++++++++++++++++ .../arch/arm64/fujitsu/a64fx/branch.json | 8 + .../arch/arm64/fujitsu/a64fx/bus.json | 62 +++++ .../arch/arm64/fujitsu/a64fx/cache.json | 128 ++++++++++ .../arch/arm64/fujitsu/a64fx/cycle.json | 5 + .../arch/arm64/fujitsu/a64fx/exception.json | 29 +++ .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++++++++ .../arch/arm64/fujitsu/a64fx/memory.json | 8 + .../arch/arm64/fujitsu/a64fx/other.json | 188 +++++++++++++++ .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 +++++++++++++++ .../arch/arm64/fujitsu/a64fx/sve.json | 110 +++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 12 files changed, 1092 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v9 0/2] perf vendor events: Support PMU events for A64FX @ 2021-03-08 10:53 ` Shunsuke Nakamura 0 siblings, 0 replies; 10+ messages in thread From: Shunsuke Nakamura @ 2021-03-08 10:53 UTC (permalink / raw) To: john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung Cc: linux-arm-kernel, linux-kernel This patch series supports A64FX PMU event v1.2. The first patch add more common and microarchitecture events. This patch is based on john's patch [1]. The second patch adds PMU events for A64FX. Changes in v8: - Merge 'perf vendor events arm64: Add Fujitsu A64FX pmu event' and 'perf vendor events arm64: Add "_" to the event name, which starts with a number' Changes in v7: - Rename an event name that starts with a number. - Drop 'perf tools: Add lexical definition of event name'. - Drop 'perf test: Add test for event name starting with a number'. Changes in v6: - Add test to the second patch. - Add Acked-by tag to the third patch. - Add Reviewed-by tag to the third patch. Changes in v5: - Removed john's patch [1] from this patch series. - Added the missing Reviewed-by tag to the patch. - Fixed the base of the patch series.[2] - Changed subject from fix to added. Changes in v4: - Add arm64 to the subjects of the second and fourth patches. - Add reference URLs to the body of the second patch. Changes in v3: - Add linux-arm-kernel mailing list to cc. Changes in v2: - Added armv8-common-and-microarch based on John's patch.[1] - Fixed A64FX Json to refer to standard events in armv8-common-and-microarch. [1] https://lore.kernel.org/lkml/1611835236-34696-3-git-send-email-john.garry@huawei.com/ [2] https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core Shunsuke Nakamura (2): perf vendor events arm64: Add more common and uarch events perf vendor events arm64: Add Fujitsu A64FX pmu event .../arm64/armv8-common-and-microarch.json | 228 ++++++++++++++++++ .../arch/arm64/fujitsu/a64fx/branch.json | 8 + .../arch/arm64/fujitsu/a64fx/bus.json | 62 +++++ .../arch/arm64/fujitsu/a64fx/cache.json | 128 ++++++++++ .../arch/arm64/fujitsu/a64fx/cycle.json | 5 + .../arch/arm64/fujitsu/a64fx/exception.json | 29 +++ .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++++++++ .../arch/arm64/fujitsu/a64fx/memory.json | 8 + .../arch/arm64/fujitsu/a64fx/other.json | 188 +++++++++++++++ .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 +++++++++++++++ .../arch/arm64/fujitsu/a64fx/sve.json | 110 +++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 12 files changed, 1092 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json -- 2.25.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v9 1/2] perf vendor events arm64: Add more common and uarch events 2021-03-08 10:53 ` Shunsuke Nakamura @ 2021-03-08 10:53 ` Shunsuke Nakamura -1 siblings, 0 replies; 10+ messages in thread From: Shunsuke Nakamura @ 2021-03-08 10:53 UTC (permalink / raw) To: john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung Cc: linux-arm-kernel, linux-kernel Add the following events.[1] Common architectural events: - L2I_TLB_REFILL - L2I_TLB - SIMD_INST_RETIRED - SVE_INST_RETIRED Common microarchitectural events: - UOP_SPEC - SVE_MATH_SPEC - FP_SPEC - FP_FMA_SPEC - FP_RECPE_SPEC - FP_CVT_SPEC - ASE_SVE_INT_SPEC - SVE_PRED_SPEC - SVE_MOVPRFX_SPEC - SVE_MOVPRFX_U_SPEC - ASE_SVE_LD_SPEC - ASE_SVE_ST_SPEC - PRF_SPEC - BASE_LD_REG_SPEC - BASE_ST_REG_SPEC - SVE_LDR_REG_SPEC - SVE_STR_REG_SPEC - SVE_LDR_PREG_SPEC - SVE_STR_PREG_SPEC - SVE_PRF_CONTIG_SPEC - ASE_SVE_LD_MULTI_SPEC - ASE_SVE_ST_MULTI_SPEC - SVE_LD_GATHER_SPEC - SVE_ST_SCATTER_SPEC - SVE_PRF_GATHER_SPEC - SVE_LDFF_SPEC - FP_SCALE_OPS_SPEC - FP_FIXED_OPS_SPEC - FP_HP_SCALE_OPS_SPEC - FP_HP_FIXED_OPS_SPEC - FP_SP_SCALE_OPS_SPEC - FP_SP_FIXED_OPS_SPEC - FP_DP_SCALE_OPS_SPEC - FP_DP_FIXED_OPS_SPEC Reference document is at the following: [1] https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com> Reviewed-by: John Garry <john.garry@huawei.com> --- .../arm64/armv8-common-and-microarch.json | 228 ++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json index 75376c7cc072..913fb200ea52 100644 --- a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json @@ -209,12 +209,24 @@ "EventName": "L2D_TLB_REFILL", "BriefDescription": "Attributable Level 2 data TLB refill" }, + { + "PublicDescription": "Attributable Level 2 instruction TLB refill.", + "EventCode": "0x2E", + "EventName": "L2I_TLB_REFILL", + "BriefDescription": "Attributable Level 2 instruction TLB refill." + }, { "PublicDescription": "Attributable Level 2 data or unified TLB access", "EventCode": "0x2F", "EventName": "L2D_TLB", "BriefDescription": "Attributable Level 2 data or unified TLB access" }, + { + "PublicDescription": "Attributable Level 2 instruction TLB access.", + "EventCode": "0x30", + "EventName": "L2I_TLB", + "BriefDescription": "Attributable Level 2 instruction TLB access." + }, { "PublicDescription": "Access to another socket in a multi-socket system", "EventCode": "0x31", @@ -244,5 +256,221 @@ "EventCode": "0x37", "EventName": "LL_CACHE_MISS_RD", "BriefDescription": "Last level cache miss, read" + }, + { + "PublicDescription": "SIMD Instruction architecturally executed.", + "EventCode": "0x8000", + "EventName": "SIMD_INST_RETIRED", + "BriefDescription": "SIMD Instruction architecturally executed." + }, + { + "PublicDescription": "Instruction architecturally executed, SVE.", + "EventCode": "0x8002", + "EventName": "SVE_INST_RETIRED", + "BriefDescription": "Instruction architecturally executed, SVE." + }, + { + "PublicDescription": "Microarchitectural operation, Operations speculatively executed.", + "EventCode": "0x8008", + "EventName": "UOP_SPEC", + "BriefDescription": "Microarchitectural operation, Operations speculatively executed." + }, + { + "PublicDescription": "SVE Math accelerator Operations speculatively executed.", + "EventCode": "0x800E", + "EventName": "SVE_MATH_SPEC", + "BriefDescription": "SVE Math accelerator Operations speculatively executed." + }, + { + "PublicDescription": "Floating-point Operations speculatively executed.", + "EventCode": "0x8010", + "EventName": "FP_SPEC", + "BriefDescription": "Floating-point Operations speculatively executed." + }, + { + "PublicDescription": "Floating-point FMA Operations speculatively executed.", + "EventCode": "0x8028", + "EventName": "FP_FMA_SPEC", + "BriefDescription": "Floating-point FMA Operations speculatively executed." + }, + { + "PublicDescription": "Floating-point reciprocal estimate Operations speculatively executed.", + "EventCode": "0x8034", + "EventName": "FP_RECPE_SPEC", + "BriefDescription": "Floating-point reciprocal estimate Operations speculatively executed." + }, + { + "PublicDescription": "floating-point convert Operations speculatively executed.", + "EventCode": "0x8038", + "EventName": "FP_CVT_SPEC", + "BriefDescription": "floating-point convert Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE integer Operations speculatively executed.", + "EventCode": "0x8043", + "EventName": "ASE_SVE_INT_SPEC", + "BriefDescription": "Advanced SIMD and SVE integer Operations speculatively executed." + }, + { + "PublicDescription": "SVE predicated Operations speculatively executed.", + "EventCode": "0x8074", + "EventName": "SVE_PRED_SPEC", + "BriefDescription": "SVE predicated Operations speculatively executed." + }, + { + "PublicDescription": "SVE MOVPRFX Operations speculatively executed.", + "EventCode": "0x807C", + "EventName": "SVE_MOVPRFX_SPEC", + "BriefDescription": "SVE MOVPRFX Operations speculatively executed." + }, + { + "PublicDescription": "SVE MOVPRFX unfused Operations speculatively executed.", + "EventCode": "0x807F", + "EventName": "SVE_MOVPRFX_U_SPEC", + "BriefDescription": "SVE MOVPRFX unfused Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE load Operations speculatively executed.", + "EventCode": "0x8085", + "EventName": "ASE_SVE_LD_SPEC", + "BriefDescription": "Advanced SIMD and SVE load Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE store Operations speculatively executed.", + "EventCode": "0x8086", + "EventName": "ASE_SVE_ST_SPEC", + "BriefDescription": "Advanced SIMD and SVE store Operations speculatively executed." + }, + { + "PublicDescription": "Prefetch Operations speculatively executed.", + "EventCode": "0x8087", + "EventName": "PRF_SPEC", + "BriefDescription": "Prefetch Operations speculatively executed." + }, + { + "PublicDescription": "General-purpose register load Operations speculatively executed.", + "EventCode": "0x8089", + "EventName": "BASE_LD_REG_SPEC", + "BriefDescription": "General-purpose register load Operations speculatively executed." + }, + { + "PublicDescription": "General-purpose register store Operations speculatively executed.", + "EventCode": "0x808A", + "EventName": "BASE_ST_REG_SPEC", + "BriefDescription": "General-purpose register store Operations speculatively executed." + }, + { + "PublicDescription": "SVE unpredicated load register Operations speculatively executed.", + "EventCode": "0x8091", + "EventName": "SVE_LDR_REG_SPEC", + "BriefDescription": "SVE unpredicated load register Operations speculatively executed." + }, + { + "PublicDescription": "SVE unpredicated store register Operations speculatively executed.", + "EventCode": "0x8092", + "EventName": "SVE_STR_REG_SPEC", + "BriefDescription": "SVE unpredicated store register Operations speculatively executed." + }, + { + "PublicDescription": "SVE load predicate register Operations speculatively executed.", + "EventCode": "0x8095", + "EventName": "SVE_LDR_PREG_SPEC", + "BriefDescription": "SVE load predicate register Operations speculatively executed." + }, + { + "PublicDescription": "SVE store predicate register Operations speculatively executed.", + "EventCode": "0x8096", + "EventName": "SVE_STR_PREG_SPEC", + "BriefDescription": "SVE store predicate register Operations speculatively executed." + }, + { + "PublicDescription": "SVE contiguous prefetch element Operations speculatively executed.", + "EventCode": "0x809F", + "EventName": "SVE_PRF_CONTIG_SPEC", + "BriefDescription": "SVE contiguous prefetch element Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed.", + "EventCode": "0x80A5", + "EventName": "ASE_SVE_LD_MULTI_SPEC", + "BriefDescription": "Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE contiguous store multiple vector Operations speculatively executed.", + "EventCode": "0x80A6", + "EventName": "ASE_SVE_ST_MULTI_SPEC", + "BriefDescription": "Advanced SIMD and SVE contiguous store multiple vector Operations speculatively executed." + }, + { + "PublicDescription": "SVE gather-load Operations speculatively executed.", + "EventCode": "0x80AD", + "EventName": "SVE_LD_GATHER_SPEC", + "BriefDescription": "SVE gather-load Operations speculatively executed." + }, + { + "PublicDescription": "SVE scatter-store Operations speculatively executed.", + "EventCode": "0x80AE", + "EventName": "SVE_ST_SCATTER_SPEC", + "BriefDescription": "SVE scatter-store Operations speculatively executed." + }, + { + "PublicDescription": "SVE gather-prefetch Operations speculatively executed.", + "EventCode": "0x80AF", + "EventName": "SVE_PRF_GATHER_SPEC", + "BriefDescription": "SVE gather-prefetch Operations speculatively executed." + }, + { + "PublicDescription": "SVE First-fault load Operations speculatively executed.", + "EventCode": "0x80BC", + "EventName": "SVE_LDFF_SPEC", + "BriefDescription": "SVE First-fault load Operations speculatively executed." + }, + { + "PublicDescription": "Scalable floating-point element Operations speculatively executed.", + "EventCode": "0x80C0", + "EventName": "FP_SCALE_OPS_SPEC", + "BriefDescription": "Scalable floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Non-scalable floating-point element Operations speculatively executed.", + "EventCode": "0x80C1", + "EventName": "FP_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Scalable half-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C2", + "EventName": "FP_HP_SCALE_OPS_SPEC", + "BriefDescription": "Scalable half-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Non-scalable half-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C3", + "EventName": "FP_HP_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable half-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Scalable single-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C4", + "EventName": "FP_SP_SCALE_OPS_SPEC", + "BriefDescription": "Scalable single-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Non-scalable single-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C5", + "EventName": "FP_SP_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable single-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Scalable double-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C6", + "EventName": "FP_DP_SCALE_OPS_SPEC", + "BriefDescription": "Scalable double-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Non-scalable double-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C7", + "EventName": "FP_DP_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable double-precision floating-point element Operations speculatively executed." } ] -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v9 1/2] perf vendor events arm64: Add more common and uarch events @ 2021-03-08 10:53 ` Shunsuke Nakamura 0 siblings, 0 replies; 10+ messages in thread From: Shunsuke Nakamura @ 2021-03-08 10:53 UTC (permalink / raw) To: john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung Cc: linux-arm-kernel, linux-kernel Add the following events.[1] Common architectural events: - L2I_TLB_REFILL - L2I_TLB - SIMD_INST_RETIRED - SVE_INST_RETIRED Common microarchitectural events: - UOP_SPEC - SVE_MATH_SPEC - FP_SPEC - FP_FMA_SPEC - FP_RECPE_SPEC - FP_CVT_SPEC - ASE_SVE_INT_SPEC - SVE_PRED_SPEC - SVE_MOVPRFX_SPEC - SVE_MOVPRFX_U_SPEC - ASE_SVE_LD_SPEC - ASE_SVE_ST_SPEC - PRF_SPEC - BASE_LD_REG_SPEC - BASE_ST_REG_SPEC - SVE_LDR_REG_SPEC - SVE_STR_REG_SPEC - SVE_LDR_PREG_SPEC - SVE_STR_PREG_SPEC - SVE_PRF_CONTIG_SPEC - ASE_SVE_LD_MULTI_SPEC - ASE_SVE_ST_MULTI_SPEC - SVE_LD_GATHER_SPEC - SVE_ST_SCATTER_SPEC - SVE_PRF_GATHER_SPEC - SVE_LDFF_SPEC - FP_SCALE_OPS_SPEC - FP_FIXED_OPS_SPEC - FP_HP_SCALE_OPS_SPEC - FP_HP_FIXED_OPS_SPEC - FP_SP_SCALE_OPS_SPEC - FP_SP_FIXED_OPS_SPEC - FP_DP_SCALE_OPS_SPEC - FP_DP_FIXED_OPS_SPEC Reference document is at the following: [1] https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com> Reviewed-by: John Garry <john.garry@huawei.com> --- .../arm64/armv8-common-and-microarch.json | 228 ++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json index 75376c7cc072..913fb200ea52 100644 --- a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json @@ -209,12 +209,24 @@ "EventName": "L2D_TLB_REFILL", "BriefDescription": "Attributable Level 2 data TLB refill" }, + { + "PublicDescription": "Attributable Level 2 instruction TLB refill.", + "EventCode": "0x2E", + "EventName": "L2I_TLB_REFILL", + "BriefDescription": "Attributable Level 2 instruction TLB refill." + }, { "PublicDescription": "Attributable Level 2 data or unified TLB access", "EventCode": "0x2F", "EventName": "L2D_TLB", "BriefDescription": "Attributable Level 2 data or unified TLB access" }, + { + "PublicDescription": "Attributable Level 2 instruction TLB access.", + "EventCode": "0x30", + "EventName": "L2I_TLB", + "BriefDescription": "Attributable Level 2 instruction TLB access." + }, { "PublicDescription": "Access to another socket in a multi-socket system", "EventCode": "0x31", @@ -244,5 +256,221 @@ "EventCode": "0x37", "EventName": "LL_CACHE_MISS_RD", "BriefDescription": "Last level cache miss, read" + }, + { + "PublicDescription": "SIMD Instruction architecturally executed.", + "EventCode": "0x8000", + "EventName": "SIMD_INST_RETIRED", + "BriefDescription": "SIMD Instruction architecturally executed." + }, + { + "PublicDescription": "Instruction architecturally executed, SVE.", + "EventCode": "0x8002", + "EventName": "SVE_INST_RETIRED", + "BriefDescription": "Instruction architecturally executed, SVE." + }, + { + "PublicDescription": "Microarchitectural operation, Operations speculatively executed.", + "EventCode": "0x8008", + "EventName": "UOP_SPEC", + "BriefDescription": "Microarchitectural operation, Operations speculatively executed." + }, + { + "PublicDescription": "SVE Math accelerator Operations speculatively executed.", + "EventCode": "0x800E", + "EventName": "SVE_MATH_SPEC", + "BriefDescription": "SVE Math accelerator Operations speculatively executed." + }, + { + "PublicDescription": "Floating-point Operations speculatively executed.", + "EventCode": "0x8010", + "EventName": "FP_SPEC", + "BriefDescription": "Floating-point Operations speculatively executed." + }, + { + "PublicDescription": "Floating-point FMA Operations speculatively executed.", + "EventCode": "0x8028", + "EventName": "FP_FMA_SPEC", + "BriefDescription": "Floating-point FMA Operations speculatively executed." + }, + { + "PublicDescription": "Floating-point reciprocal estimate Operations speculatively executed.", + "EventCode": "0x8034", + "EventName": "FP_RECPE_SPEC", + "BriefDescription": "Floating-point reciprocal estimate Operations speculatively executed." + }, + { + "PublicDescription": "floating-point convert Operations speculatively executed.", + "EventCode": "0x8038", + "EventName": "FP_CVT_SPEC", + "BriefDescription": "floating-point convert Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE integer Operations speculatively executed.", + "EventCode": "0x8043", + "EventName": "ASE_SVE_INT_SPEC", + "BriefDescription": "Advanced SIMD and SVE integer Operations speculatively executed." + }, + { + "PublicDescription": "SVE predicated Operations speculatively executed.", + "EventCode": "0x8074", + "EventName": "SVE_PRED_SPEC", + "BriefDescription": "SVE predicated Operations speculatively executed." + }, + { + "PublicDescription": "SVE MOVPRFX Operations speculatively executed.", + "EventCode": "0x807C", + "EventName": "SVE_MOVPRFX_SPEC", + "BriefDescription": "SVE MOVPRFX Operations speculatively executed." + }, + { + "PublicDescription": "SVE MOVPRFX unfused Operations speculatively executed.", + "EventCode": "0x807F", + "EventName": "SVE_MOVPRFX_U_SPEC", + "BriefDescription": "SVE MOVPRFX unfused Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE load Operations speculatively executed.", + "EventCode": "0x8085", + "EventName": "ASE_SVE_LD_SPEC", + "BriefDescription": "Advanced SIMD and SVE load Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE store Operations speculatively executed.", + "EventCode": "0x8086", + "EventName": "ASE_SVE_ST_SPEC", + "BriefDescription": "Advanced SIMD and SVE store Operations speculatively executed." + }, + { + "PublicDescription": "Prefetch Operations speculatively executed.", + "EventCode": "0x8087", + "EventName": "PRF_SPEC", + "BriefDescription": "Prefetch Operations speculatively executed." + }, + { + "PublicDescription": "General-purpose register load Operations speculatively executed.", + "EventCode": "0x8089", + "EventName": "BASE_LD_REG_SPEC", + "BriefDescription": "General-purpose register load Operations speculatively executed." + }, + { + "PublicDescription": "General-purpose register store Operations speculatively executed.", + "EventCode": "0x808A", + "EventName": "BASE_ST_REG_SPEC", + "BriefDescription": "General-purpose register store Operations speculatively executed." + }, + { + "PublicDescription": "SVE unpredicated load register Operations speculatively executed.", + "EventCode": "0x8091", + "EventName": "SVE_LDR_REG_SPEC", + "BriefDescription": "SVE unpredicated load register Operations speculatively executed." + }, + { + "PublicDescription": "SVE unpredicated store register Operations speculatively executed.", + "EventCode": "0x8092", + "EventName": "SVE_STR_REG_SPEC", + "BriefDescription": "SVE unpredicated store register Operations speculatively executed." + }, + { + "PublicDescription": "SVE load predicate register Operations speculatively executed.", + "EventCode": "0x8095", + "EventName": "SVE_LDR_PREG_SPEC", + "BriefDescription": "SVE load predicate register Operations speculatively executed." + }, + { + "PublicDescription": "SVE store predicate register Operations speculatively executed.", + "EventCode": "0x8096", + "EventName": "SVE_STR_PREG_SPEC", + "BriefDescription": "SVE store predicate register Operations speculatively executed." + }, + { + "PublicDescription": "SVE contiguous prefetch element Operations speculatively executed.", + "EventCode": "0x809F", + "EventName": "SVE_PRF_CONTIG_SPEC", + "BriefDescription": "SVE contiguous prefetch element Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed.", + "EventCode": "0x80A5", + "EventName": "ASE_SVE_LD_MULTI_SPEC", + "BriefDescription": "Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed." + }, + { + "PublicDescription": "Advanced SIMD and SVE contiguous store multiple vector Operations speculatively executed.", + "EventCode": "0x80A6", + "EventName": "ASE_SVE_ST_MULTI_SPEC", + "BriefDescription": "Advanced SIMD and SVE contiguous store multiple vector Operations speculatively executed." + }, + { + "PublicDescription": "SVE gather-load Operations speculatively executed.", + "EventCode": "0x80AD", + "EventName": "SVE_LD_GATHER_SPEC", + "BriefDescription": "SVE gather-load Operations speculatively executed." + }, + { + "PublicDescription": "SVE scatter-store Operations speculatively executed.", + "EventCode": "0x80AE", + "EventName": "SVE_ST_SCATTER_SPEC", + "BriefDescription": "SVE scatter-store Operations speculatively executed." + }, + { + "PublicDescription": "SVE gather-prefetch Operations speculatively executed.", + "EventCode": "0x80AF", + "EventName": "SVE_PRF_GATHER_SPEC", + "BriefDescription": "SVE gather-prefetch Operations speculatively executed." + }, + { + "PublicDescription": "SVE First-fault load Operations speculatively executed.", + "EventCode": "0x80BC", + "EventName": "SVE_LDFF_SPEC", + "BriefDescription": "SVE First-fault load Operations speculatively executed." + }, + { + "PublicDescription": "Scalable floating-point element Operations speculatively executed.", + "EventCode": "0x80C0", + "EventName": "FP_SCALE_OPS_SPEC", + "BriefDescription": "Scalable floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Non-scalable floating-point element Operations speculatively executed.", + "EventCode": "0x80C1", + "EventName": "FP_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Scalable half-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C2", + "EventName": "FP_HP_SCALE_OPS_SPEC", + "BriefDescription": "Scalable half-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Non-scalable half-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C3", + "EventName": "FP_HP_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable half-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Scalable single-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C4", + "EventName": "FP_SP_SCALE_OPS_SPEC", + "BriefDescription": "Scalable single-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Non-scalable single-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C5", + "EventName": "FP_SP_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable single-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Scalable double-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C6", + "EventName": "FP_DP_SCALE_OPS_SPEC", + "BriefDescription": "Scalable double-precision floating-point element Operations speculatively executed." + }, + { + "PublicDescription": "Non-scalable double-precision floating-point element Operations speculatively executed.", + "EventCode": "0x80C7", + "EventName": "FP_DP_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable double-precision floating-point element Operations speculatively executed." } ] -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v9 2/2] perf vendor events arm64: Add Fujitsu A64FX pmu event 2021-03-08 10:53 ` Shunsuke Nakamura @ 2021-03-08 10:53 ` Shunsuke Nakamura -1 siblings, 0 replies; 10+ messages in thread From: Shunsuke Nakamura @ 2021-03-08 10:53 UTC (permalink / raw) To: john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung Cc: linux-arm-kernel, linux-kernel Add pmu events for A64FX. Documentation source: https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com> Reviewed-by: John Garry <john.garry@huawei.com> --- .../arch/arm64/fujitsu/a64fx/branch.json | 8 + .../arch/arm64/fujitsu/a64fx/bus.json | 62 ++++++ .../arch/arm64/fujitsu/a64fx/cache.json | 128 ++++++++++++ .../arch/arm64/fujitsu/a64fx/cycle.json | 5 + .../arch/arm64/fujitsu/a64fx/exception.json | 29 +++ .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++++++++++ .../arch/arm64/fujitsu/a64fx/memory.json | 8 + .../arch/arm64/fujitsu/a64fx/other.json | 188 +++++++++++++++++ .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 ++++++++++++++++++ .../arch/arm64/fujitsu/a64fx/sve.json | 110 ++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 11 files changed, 864 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json new file mode 100644 index 000000000000..b011af11bf94 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json new file mode 100644 index 000000000000..084e88d7df73 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json @@ -0,0 +1,62 @@ +[ + { + "PublicDescription": "This event counts read transactions from tofu controller to measured CMG.", + "EventCode": "0x314", + "EventName": "BUS_READ_TOTAL_TOFU", + "BriefDescription": "This event counts read transactions from tofu controller to measured CMG." + }, + { + "PublicDescription": "This event counts read transactions from PCI controller to measured CMG.", + "EventCode": "0x315", + "EventName": "BUS_READ_TOTAL_PCI", + "BriefDescription": "This event counts read transactions from PCI controller to measured CMG." + }, + { + "PublicDescription": "This event counts read transactions from measured CMG local memory to measured CMG.", + "EventCode": "0x316", + "EventName": "BUS_READ_TOTAL_MEM", + "BriefDescription": "This event counts read transactions from measured CMG local memory to measured CMG." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0.", + "EventCode": "0x318", + "EventName": "BUS_WRITE_TOTAL_CMG0", + "BriefDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1.", + "EventCode": "0x319", + "EventName": "BUS_WRITE_TOTAL_CMG1", + "BriefDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2.", + "EventCode": "0x31A", + "EventName": "BUS_WRITE_TOTAL_CMG2", + "BriefDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3.", + "EventCode": "0x31B", + "EventName": "BUS_WRITE_TOTAL_CMG3", + "BriefDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to tofu controller.", + "EventCode": "0x31C", + "EventName": "BUS_WRITE_TOTAL_TOFU", + "BriefDescription": "This event counts write transactions from measured CMG to tofu controller." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to PCI controller.", + "EventCode": "0x31D", + "EventName": "BUS_WRITE_TOTAL_PCI", + "BriefDescription": "This event counts write transactions from measured CMG to PCI controller." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to measured CMG local memory.", + "EventCode": "0x31E", + "EventName": "BUS_WRITE_TOTAL_MEM", + "BriefDescription": "This event counts write transactions from measured CMG to measured CMG local memory." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json new file mode 100644 index 000000000000..2e341a951a10 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json @@ -0,0 +1,128 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2I_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "L2I_TLB" + }, + { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x49", + "EventName": "L1D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." + }, + { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x59", + "EventName": "L2D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." + }, + { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.", + "EventCode": "0x200", + "EventName": "L1D_CACHE_REFILL_DM", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." + }, + { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", + "EventCode": "0x202", + "EventName": "L1D_CACHE_REFILL_HWPRF", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch." + }, + { + "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", + "EventCode": "0x208", + "EventName": "L1_MISS_WAIT", + "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." + }, + { + "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.", + "EventCode": "0x209", + "EventName": "L1I_MISS_WAIT", + "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle." + }, + { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by demand access.", + "EventCode": "0x300", + "EventName": "L2D_CACHE_REFILL_DM", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access." + }, + { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch.", + "EventCode": "0x302", + "EventName": "L2D_CACHE_REFILL_HWPRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch." + }, + { + "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.", + "EventCode": "0x308", + "EventName": "L2_MISS_WAIT", + "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle." + }, + { + "PublicDescription": "This event counts the number of times of L2 cache miss.", + "EventCode": "0x309", + "EventName": "L2_MISS_COUNT", + "BriefDescription": "This event counts the number of times of L2 cache miss." + }, + { + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", + "EventCode": "0x325", + "EventName": "L2D_SWAP_DM", + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." + }, + { + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", + "EventCode": "0x326", + "EventName": "L2D_CACHE_MIBMCH_PRF", + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." + }, + { + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", + "EventCode": "0x396", + "EventName": "L2D_CACHE_SWAP_LOCAL", + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." + }, + { + "PublicDescription": "This event counts energy consumption per cycle of L2 cache.", + "EventCode": "0x3E0", + "EventName": "EA_L2", + "BriefDescription": "This event counts energy consumption per cycle of L2 cache." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json new file mode 100644 index 000000000000..b16484628290 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json @@ -0,0 +1,5 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json new file mode 100644 index 000000000000..348749c154c0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json @@ -0,0 +1,29 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_SMC" + }, + { + "ArchStdEvent": "EXC_HVC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json new file mode 100644 index 000000000000..6d258b1080cf --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json @@ -0,0 +1,131 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", + "EventCode": "0x9F", + "EventName": "DCZVA_SPEC", + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." + }, + { + "PublicDescription": "This event counts architecturally executed floating-point move operations.", + "EventCode": "0x105", + "EventName": "FP_MV_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point move operations." + }, + { + "PublicDescription": "This event counts architecturally executed operations that using predicate register.", + "EventCode": "0x108", + "EventName": "PRD_SPEC", + "BriefDescription": "This event counts architecturally executed operations that using predicate register." + }, + { + "PublicDescription": "This event counts architecturally executed inter-element manipulation operations.", + "EventCode": "0x109", + "EventName": "IEL_SPEC", + "BriefDescription": "This event counts architecturally executed inter-element manipulation operations." + }, + { + "PublicDescription": "This event counts architecturally executed inter-register manipulation operations.", + "EventCode": "0x10A", + "EventName": "IREG_SPEC", + "BriefDescription": "This event counts architecturally executed inter-register manipulation operations." + }, + { + "PublicDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.", + "EventCode": "0x112", + "EventName": "FP_LD_SPEC", + "BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers." + }, + { + "PublicDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.", + "EventCode": "0x113", + "EventName": "FP_ST_SPEC", + "BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers." + }, + { + "PublicDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations.", + "EventCode": "0x11A", + "EventName": "BC_LD_SPEC", + "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations." + }, + { + "PublicDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.", + "EventCode": "0x121", + "EventName": "EFFECTIVE_INST_SPEC", + "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction." + }, + { + "PublicDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.", + "EventCode": "0x123", + "EventName": "PRE_INDEX_SPEC", + "BriefDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode." + }, + { + "PublicDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode.", + "EventCode": "0x124", + "EventName": "POST_INDEX_SPEC", + "BriefDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json new file mode 100644 index 000000000000..c1f6479e92b4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json @@ -0,0 +1,8 @@ +[ + { + "PublicDescription": "This event counts energy consumption per cycle of CMG local memory.", + "EventCode": "0x3E8", + "EventName": "EA_MEMORY", + "BriefDescription": "This event counts energy consumption per cycle of CMG local memory." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json new file mode 100644 index 000000000000..10c823ac26cc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json @@ -0,0 +1,188 @@ +[ + { + "PublicDescription": "This event counts the occurrence count of the micro-operation split.", + "EventCode": "0x139", + "EventName": "UOP_SPLIT", + "BriefDescription": "This event counts the occurrence count of the micro-operation split." + }, + { + "PublicDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access.", + "EventCode": "0x180", + "EventName": "LD_COMP_WAIT_L2_MISS", + "BriefDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access.", + "EventCode": "0x181", + "EventName": "LD_COMP_WAIT_L2_MISS_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.", + "EventCode": "0x182", + "EventName": "LD_COMP_WAIT_L1_MISS", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.", + "EventCode": "0x183", + "EventName": "LD_COMP_WAIT_L1_MISS_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", + "EventCode": "0x184", + "EventName": "LD_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", + "EventCode": "0x185", + "EventName": "LD_COMP_WAIT_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.", + "EventCode": "0x186", + "EventName": "LD_COMP_WAIT_PFP_BUSY", + "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port." + }, + { + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.", + "EventCode": "0x187", + "EventName": "LD_COMP_WAIT_PFP_BUSY_EX", + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation." + }, + { + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.", + "EventCode": "0x188", + "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF", + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction.", + "EventCode": "0x189", + "EventName": "EU_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.", + "EventCode": "0x18A", + "EventName": "FL_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.", + "EventCode": "0x18B", + "EventName": "BR_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty.", + "EventCode": "0x18C", + "EventName": "ROB_EMPTY", + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.", + "EventCode": "0x18D", + "EventName": "ROB_EMPTY_STQ_BUSY", + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full." + }, + { + "PublicDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.", + "EventCode": "0x18E", + "EventName": "WFE_WFI_CYCLE", + "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only.", + "EventCode": "0x190", + "EventName": "_0INST_COMMIT", + "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only." + }, + { + "PublicDescription": "This event counts every cycle that one instruction is committed.", + "EventCode": "0x191", + "EventName": "_1INST_COMMIT", + "BriefDescription": "This event counts every cycle that one instruction is committed." + }, + { + "PublicDescription": "This event counts every cycle that two instructions are committed.", + "EventCode": "0x192", + "EventName": "_2INST_COMMIT", + "BriefDescription": "This event counts every cycle that two instructions are committed." + }, + { + "PublicDescription": "This event counts every cycle that three instructions are committed.", + "EventCode": "0x193", + "EventName": "_3INST_COMMIT", + "BriefDescription": "This event counts every cycle that three instructions are committed." + }, + { + "PublicDescription": "This event counts every cycle that four instructions are committed.", + "EventCode": "0x194", + "EventName": "_4INST_COMMIT", + "BriefDescription": "This event counts every cycle that four instructions are committed." + }, + { + "PublicDescription": "This event counts every cycle that only any micro-operations are committed.", + "EventCode": "0x198", + "EventName": "UOP_ONLY_COMMIT", + "BriefDescription": "This event counts every cycle that only any micro-operations are committed." + }, + { + "PublicDescription": "This event counts every cycle that only the MOVPRFX instruction is committed.", + "EventCode": "0x199", + "EventName": "SINGLE_MOVPRFX_COMMIT", + "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed." + }, + { + "PublicDescription": "This event counts energy consumption per cycle of core.", + "EventCode": "0x1E0", + "EventName": "EA_CORE", + "BriefDescription": "This event counts energy consumption per cycle of core." + }, + { + "PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.", + "EventCode": "0x230", + "EventName": "L1HWPF_STREAM_PF", + "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", + "EventCode": "0x231", + "EventName": "L1HWPF_INJ_ALLOC_PF", + "BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", + "EventCode": "0x232", + "EventName": "L1HWPF_INJ_NOALLOC_PF", + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.", + "EventCode": "0x233", + "EventName": "L2HWPF_STREAM_PF", + "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher." + }, + { + "PublicDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", + "EventCode": "0x234", + "EventName": "L2HWPF_INJ_ALLOC_PF", + "BriefDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", + "EventCode": "0x235", + "EventName": "L2HWPF_INJ_NOALLOC_PF", + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts prefetch requests to L2 cache generated by the other causes.", + "EventCode": "0x236", + "EventName": "L2HWPF_OTHER", + "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json new file mode 100644 index 000000000000..dd7c97a9972b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json @@ -0,0 +1,194 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "PublicDescription": "This event counts valid cycles of EAGA pipeline.", + "EventCode": "0x1A0", + "EventName": "EAGA_VAL", + "BriefDescription": "This event counts valid cycles of EAGA pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of EAGB pipeline.", + "EventCode": "0x1A1", + "EventName": "EAGB_VAL", + "BriefDescription": "This event counts valid cycles of EAGB pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of EXA pipeline.", + "EventCode": "0x1A2", + "EventName": "EXA_VAL", + "BriefDescription": "This event counts valid cycles of EXA pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of EXB pipeline.", + "EventCode": "0x1A3", + "EventName": "EXB_VAL", + "BriefDescription": "This event counts valid cycles of EXB pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of FLA pipeline.", + "EventCode": "0x1A4", + "EventName": "FLA_VAL", + "BriefDescription": "This event counts valid cycles of FLA pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of FLB pipeline.", + "EventCode": "0x1A5", + "EventName": "FLB_VAL", + "BriefDescription": "This event counts valid cycles of FLB pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of PRX pipeline.", + "EventCode": "0x1A6", + "EventName": "PRX_VAL", + "BriefDescription": "This event counts valid cycles of PRX pipeline." + }, + { + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1.", + "EventCode": "0x1B4", + "EventName": "FLA_VAL_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1." + }, + { + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1.", + "EventCode": "0x1B5", + "EventName": "FLB_VAL_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1." + }, + { + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#0.", + "EventCode": "0x240", + "EventName": "L1_PIPE0_VAL", + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." + }, + { + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#1.", + "EventCode": "0x241", + "EventName": "L1_PIPE1_VAL", + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.", + "EventCode": "0x250", + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1.", + "EventCode": "0x251", + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_PFE", + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.", + "EventCode": "0x252", + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1.", + "EventCode": "0x253", + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_PFE", + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1." + }, + { + "PublicDescription": "This event counts completed requests in L1D cache pipeline#0.", + "EventCode": "0x260", + "EventName": "L1_PIPE0_COMP", + "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." + }, + { + "PublicDescription": "This event counts completed requests in L1D cache pipeline#1.", + "EventCode": "0x261", + "EventName": "L1_PIPE1_COMP", + "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." + }, + { + "PublicDescription": "This event counts completed requests in L1I cache pipeline.", + "EventCode": "0x268", + "EventName": "L1I_PIPE_COMP", + "BriefDescription": "This event counts completed requests in L1I cache pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of L1I cache pipeline.", + "EventCode": "0x269", + "EventName": "L1I_PIPE_VAL", + "BriefDescription": "This event counts valid cycles of L1I cache pipeline." + }, + { + "PublicDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock.", + "EventCode": "0x274", + "EventName": "L1_PIPE_ABORT_STLD_INTLK", + "BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0.", + "EventCode": "0x2A0", + "EventName": "L1_PIPE0_VAL_IU_NOT_SEC0", + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0.", + "EventCode": "0x2A1", + "EventName": "L1_PIPE1_VAL_IU_NOT_SEC0", + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0." + }, + { + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", + "EventCode": "0x2B0", + "EventName": "L1_PIPE_COMP_GATHER_2FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined." + }, + { + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", + "EventCode": "0x2B1", + "EventName": "L1_PIPE_COMP_GATHER_1FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined." + }, + { + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", + "EventCode": "0x2B2", + "EventName": "L1_PIPE_COMP_GATHER_0FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0." + }, + { + "PublicDescription": "This event counts the number of flows of the scatter instructions.", + "EventCode": "0x2B3", + "EventName": "L1_PIPE_COMP_SCATTER_1FLOW", + "BriefDescription": "This event counts the number of flows of the scatter instructions." + }, + { + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1.", + "EventCode": "0x2B8", + "EventName": "L1_PIPE0_COMP_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1." + }, + { + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1.", + "EventCode": "0x2B9", + "EventName": "L1_PIPE1_COMP_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1." + }, + { + "PublicDescription": "This event counts valid cycles of L2 cache pipeline.", + "EventCode": "0x330", + "EventName": "L2_PIPE_VAL", + "BriefDescription": "This event counts valid cycles of L2 cache pipeline." + }, + { + "PublicDescription": "This event counts completed requests in L2 cache pipeline.", + "EventCode": "0x350", + "EventName": "L2_PIPE_COMP_ALL", + "BriefDescription": "This event counts completed requests in L2 cache pipeline." + }, + { + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", + "EventCode": "0x370", + "EventName": "L2_PIPE_COMP_PF_L2MIB_MCH", + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json new file mode 100644 index 000000000000..dc1b95e42c32 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json @@ -0,0 +1,110 @@ +[ + { + "ArchStdEvent": "SIMD_INST_RETIRED" + }, + { + "ArchStdEvent": "SVE_INST_RETIRED" + }, + { + "ArchStdEvent": "UOP_SPEC" + }, + { + "ArchStdEvent": "SVE_MATH_SPEC" + }, + { + "ArchStdEvent": "FP_SPEC" + }, + { + "ArchStdEvent": "FP_FMA_SPEC" + }, + { + "ArchStdEvent": "FP_RECPE_SPEC" + }, + { + "ArchStdEvent": "FP_CVT_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_SPEC" + }, + { + "ArchStdEvent": "SVE_MOVPRFX_SPEC" + }, + { + "ArchStdEvent": "SVE_MOVPRFX_U_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_LD_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_ST_SPEC" + }, + { + "ArchStdEvent": "PRF_SPEC" + }, + { + "ArchStdEvent": "BASE_LD_REG_SPEC" + }, + { + "ArchStdEvent": "BASE_ST_REG_SPEC" + }, + { + "ArchStdEvent": "SVE_LDR_REG_SPEC" + }, + { + "ArchStdEvent": "SVE_STR_REG_SPEC" + }, + { + "ArchStdEvent": "SVE_LDR_PREG_SPEC" + }, + { + "ArchStdEvent": "SVE_STR_PREG_SPEC" + }, + { + "ArchStdEvent": "SVE_PRF_CONTIG_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC" + }, + { + "ArchStdEvent": "SVE_LD_GATHER_SPEC" + }, + { + "ArchStdEvent": "SVE_ST_SCATTER_SPEC" + }, + { + "ArchStdEvent": "SVE_PRF_GATHER_SPEC" + }, + { + "ArchStdEvent": "SVE_LDFF_SPEC" + }, + { + "ArchStdEvent": "FP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_FIXED_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 0d609149b82a..c43591d831b8 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -20,5 +20,6 @@ 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core +0x00000000460f0010,v1,fujitsu/a64fx,core 0x00000000480fd010,v1,hisilicon/hip08,core 0x00000000500f0000,v1,ampere/emag,core -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v9 2/2] perf vendor events arm64: Add Fujitsu A64FX pmu event @ 2021-03-08 10:53 ` Shunsuke Nakamura 0 siblings, 0 replies; 10+ messages in thread From: Shunsuke Nakamura @ 2021-03-08 10:53 UTC (permalink / raw) To: john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung Cc: linux-arm-kernel, linux-kernel Add pmu events for A64FX. Documentation source: https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com> Reviewed-by: John Garry <john.garry@huawei.com> --- .../arch/arm64/fujitsu/a64fx/branch.json | 8 + .../arch/arm64/fujitsu/a64fx/bus.json | 62 ++++++ .../arch/arm64/fujitsu/a64fx/cache.json | 128 ++++++++++++ .../arch/arm64/fujitsu/a64fx/cycle.json | 5 + .../arch/arm64/fujitsu/a64fx/exception.json | 29 +++ .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++++++++++ .../arch/arm64/fujitsu/a64fx/memory.json | 8 + .../arch/arm64/fujitsu/a64fx/other.json | 188 +++++++++++++++++ .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 ++++++++++++++++++ .../arch/arm64/fujitsu/a64fx/sve.json | 110 ++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 11 files changed, 864 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json new file mode 100644 index 000000000000..b011af11bf94 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json new file mode 100644 index 000000000000..084e88d7df73 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json @@ -0,0 +1,62 @@ +[ + { + "PublicDescription": "This event counts read transactions from tofu controller to measured CMG.", + "EventCode": "0x314", + "EventName": "BUS_READ_TOTAL_TOFU", + "BriefDescription": "This event counts read transactions from tofu controller to measured CMG." + }, + { + "PublicDescription": "This event counts read transactions from PCI controller to measured CMG.", + "EventCode": "0x315", + "EventName": "BUS_READ_TOTAL_PCI", + "BriefDescription": "This event counts read transactions from PCI controller to measured CMG." + }, + { + "PublicDescription": "This event counts read transactions from measured CMG local memory to measured CMG.", + "EventCode": "0x316", + "EventName": "BUS_READ_TOTAL_MEM", + "BriefDescription": "This event counts read transactions from measured CMG local memory to measured CMG." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0.", + "EventCode": "0x318", + "EventName": "BUS_WRITE_TOTAL_CMG0", + "BriefDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1.", + "EventCode": "0x319", + "EventName": "BUS_WRITE_TOTAL_CMG1", + "BriefDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2.", + "EventCode": "0x31A", + "EventName": "BUS_WRITE_TOTAL_CMG2", + "BriefDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3.", + "EventCode": "0x31B", + "EventName": "BUS_WRITE_TOTAL_CMG3", + "BriefDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to tofu controller.", + "EventCode": "0x31C", + "EventName": "BUS_WRITE_TOTAL_TOFU", + "BriefDescription": "This event counts write transactions from measured CMG to tofu controller." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to PCI controller.", + "EventCode": "0x31D", + "EventName": "BUS_WRITE_TOTAL_PCI", + "BriefDescription": "This event counts write transactions from measured CMG to PCI controller." + }, + { + "PublicDescription": "This event counts write transactions from measured CMG to measured CMG local memory.", + "EventCode": "0x31E", + "EventName": "BUS_WRITE_TOTAL_MEM", + "BriefDescription": "This event counts write transactions from measured CMG to measured CMG local memory." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json new file mode 100644 index 000000000000..2e341a951a10 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json @@ -0,0 +1,128 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2I_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "L2I_TLB" + }, + { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x49", + "EventName": "L1D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." + }, + { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x59", + "EventName": "L2D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." + }, + { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.", + "EventCode": "0x200", + "EventName": "L1D_CACHE_REFILL_DM", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." + }, + { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", + "EventCode": "0x202", + "EventName": "L1D_CACHE_REFILL_HWPRF", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch." + }, + { + "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", + "EventCode": "0x208", + "EventName": "L1_MISS_WAIT", + "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." + }, + { + "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.", + "EventCode": "0x209", + "EventName": "L1I_MISS_WAIT", + "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle." + }, + { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by demand access.", + "EventCode": "0x300", + "EventName": "L2D_CACHE_REFILL_DM", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access." + }, + { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch.", + "EventCode": "0x302", + "EventName": "L2D_CACHE_REFILL_HWPRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch." + }, + { + "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.", + "EventCode": "0x308", + "EventName": "L2_MISS_WAIT", + "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle." + }, + { + "PublicDescription": "This event counts the number of times of L2 cache miss.", + "EventCode": "0x309", + "EventName": "L2_MISS_COUNT", + "BriefDescription": "This event counts the number of times of L2 cache miss." + }, + { + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", + "EventCode": "0x325", + "EventName": "L2D_SWAP_DM", + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." + }, + { + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", + "EventCode": "0x326", + "EventName": "L2D_CACHE_MIBMCH_PRF", + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." + }, + { + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", + "EventCode": "0x396", + "EventName": "L2D_CACHE_SWAP_LOCAL", + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." + }, + { + "PublicDescription": "This event counts energy consumption per cycle of L2 cache.", + "EventCode": "0x3E0", + "EventName": "EA_L2", + "BriefDescription": "This event counts energy consumption per cycle of L2 cache." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json new file mode 100644 index 000000000000..b16484628290 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json @@ -0,0 +1,5 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json new file mode 100644 index 000000000000..348749c154c0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json @@ -0,0 +1,29 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_SMC" + }, + { + "ArchStdEvent": "EXC_HVC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json new file mode 100644 index 000000000000..6d258b1080cf --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json @@ -0,0 +1,131 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", + "EventCode": "0x9F", + "EventName": "DCZVA_SPEC", + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." + }, + { + "PublicDescription": "This event counts architecturally executed floating-point move operations.", + "EventCode": "0x105", + "EventName": "FP_MV_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point move operations." + }, + { + "PublicDescription": "This event counts architecturally executed operations that using predicate register.", + "EventCode": "0x108", + "EventName": "PRD_SPEC", + "BriefDescription": "This event counts architecturally executed operations that using predicate register." + }, + { + "PublicDescription": "This event counts architecturally executed inter-element manipulation operations.", + "EventCode": "0x109", + "EventName": "IEL_SPEC", + "BriefDescription": "This event counts architecturally executed inter-element manipulation operations." + }, + { + "PublicDescription": "This event counts architecturally executed inter-register manipulation operations.", + "EventCode": "0x10A", + "EventName": "IREG_SPEC", + "BriefDescription": "This event counts architecturally executed inter-register manipulation operations." + }, + { + "PublicDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.", + "EventCode": "0x112", + "EventName": "FP_LD_SPEC", + "BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers." + }, + { + "PublicDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.", + "EventCode": "0x113", + "EventName": "FP_ST_SPEC", + "BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers." + }, + { + "PublicDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations.", + "EventCode": "0x11A", + "EventName": "BC_LD_SPEC", + "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations." + }, + { + "PublicDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.", + "EventCode": "0x121", + "EventName": "EFFECTIVE_INST_SPEC", + "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction." + }, + { + "PublicDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.", + "EventCode": "0x123", + "EventName": "PRE_INDEX_SPEC", + "BriefDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode." + }, + { + "PublicDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode.", + "EventCode": "0x124", + "EventName": "POST_INDEX_SPEC", + "BriefDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json new file mode 100644 index 000000000000..c1f6479e92b4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json @@ -0,0 +1,8 @@ +[ + { + "PublicDescription": "This event counts energy consumption per cycle of CMG local memory.", + "EventCode": "0x3E8", + "EventName": "EA_MEMORY", + "BriefDescription": "This event counts energy consumption per cycle of CMG local memory." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json new file mode 100644 index 000000000000..10c823ac26cc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json @@ -0,0 +1,188 @@ +[ + { + "PublicDescription": "This event counts the occurrence count of the micro-operation split.", + "EventCode": "0x139", + "EventName": "UOP_SPLIT", + "BriefDescription": "This event counts the occurrence count of the micro-operation split." + }, + { + "PublicDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access.", + "EventCode": "0x180", + "EventName": "LD_COMP_WAIT_L2_MISS", + "BriefDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access.", + "EventCode": "0x181", + "EventName": "LD_COMP_WAIT_L2_MISS_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.", + "EventCode": "0x182", + "EventName": "LD_COMP_WAIT_L1_MISS", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.", + "EventCode": "0x183", + "EventName": "LD_COMP_WAIT_L1_MISS_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", + "EventCode": "0x184", + "EventName": "LD_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", + "EventCode": "0x185", + "EventName": "LD_COMP_WAIT_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.", + "EventCode": "0x186", + "EventName": "LD_COMP_WAIT_PFP_BUSY", + "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port." + }, + { + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.", + "EventCode": "0x187", + "EventName": "LD_COMP_WAIT_PFP_BUSY_EX", + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation." + }, + { + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.", + "EventCode": "0x188", + "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF", + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction.", + "EventCode": "0x189", + "EventName": "EU_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.", + "EventCode": "0x18A", + "EventName": "FL_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.", + "EventCode": "0x18B", + "EventName": "BR_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty.", + "EventCode": "0x18C", + "EventName": "ROB_EMPTY", + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.", + "EventCode": "0x18D", + "EventName": "ROB_EMPTY_STQ_BUSY", + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full." + }, + { + "PublicDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.", + "EventCode": "0x18E", + "EventName": "WFE_WFI_CYCLE", + "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction." + }, + { + "PublicDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only.", + "EventCode": "0x190", + "EventName": "_0INST_COMMIT", + "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only." + }, + { + "PublicDescription": "This event counts every cycle that one instruction is committed.", + "EventCode": "0x191", + "EventName": "_1INST_COMMIT", + "BriefDescription": "This event counts every cycle that one instruction is committed." + }, + { + "PublicDescription": "This event counts every cycle that two instructions are committed.", + "EventCode": "0x192", + "EventName": "_2INST_COMMIT", + "BriefDescription": "This event counts every cycle that two instructions are committed." + }, + { + "PublicDescription": "This event counts every cycle that three instructions are committed.", + "EventCode": "0x193", + "EventName": "_3INST_COMMIT", + "BriefDescription": "This event counts every cycle that three instructions are committed." + }, + { + "PublicDescription": "This event counts every cycle that four instructions are committed.", + "EventCode": "0x194", + "EventName": "_4INST_COMMIT", + "BriefDescription": "This event counts every cycle that four instructions are committed." + }, + { + "PublicDescription": "This event counts every cycle that only any micro-operations are committed.", + "EventCode": "0x198", + "EventName": "UOP_ONLY_COMMIT", + "BriefDescription": "This event counts every cycle that only any micro-operations are committed." + }, + { + "PublicDescription": "This event counts every cycle that only the MOVPRFX instruction is committed.", + "EventCode": "0x199", + "EventName": "SINGLE_MOVPRFX_COMMIT", + "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed." + }, + { + "PublicDescription": "This event counts energy consumption per cycle of core.", + "EventCode": "0x1E0", + "EventName": "EA_CORE", + "BriefDescription": "This event counts energy consumption per cycle of core." + }, + { + "PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.", + "EventCode": "0x230", + "EventName": "L1HWPF_STREAM_PF", + "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", + "EventCode": "0x231", + "EventName": "L1HWPF_INJ_ALLOC_PF", + "BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", + "EventCode": "0x232", + "EventName": "L1HWPF_INJ_NOALLOC_PF", + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.", + "EventCode": "0x233", + "EventName": "L2HWPF_STREAM_PF", + "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher." + }, + { + "PublicDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", + "EventCode": "0x234", + "EventName": "L2HWPF_INJ_ALLOC_PF", + "BriefDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", + "EventCode": "0x235", + "EventName": "L2HWPF_INJ_NOALLOC_PF", + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." + }, + { + "PublicDescription": "This event counts prefetch requests to L2 cache generated by the other causes.", + "EventCode": "0x236", + "EventName": "L2HWPF_OTHER", + "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json new file mode 100644 index 000000000000..dd7c97a9972b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json @@ -0,0 +1,194 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "PublicDescription": "This event counts valid cycles of EAGA pipeline.", + "EventCode": "0x1A0", + "EventName": "EAGA_VAL", + "BriefDescription": "This event counts valid cycles of EAGA pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of EAGB pipeline.", + "EventCode": "0x1A1", + "EventName": "EAGB_VAL", + "BriefDescription": "This event counts valid cycles of EAGB pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of EXA pipeline.", + "EventCode": "0x1A2", + "EventName": "EXA_VAL", + "BriefDescription": "This event counts valid cycles of EXA pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of EXB pipeline.", + "EventCode": "0x1A3", + "EventName": "EXB_VAL", + "BriefDescription": "This event counts valid cycles of EXB pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of FLA pipeline.", + "EventCode": "0x1A4", + "EventName": "FLA_VAL", + "BriefDescription": "This event counts valid cycles of FLA pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of FLB pipeline.", + "EventCode": "0x1A5", + "EventName": "FLB_VAL", + "BriefDescription": "This event counts valid cycles of FLB pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of PRX pipeline.", + "EventCode": "0x1A6", + "EventName": "PRX_VAL", + "BriefDescription": "This event counts valid cycles of PRX pipeline." + }, + { + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1.", + "EventCode": "0x1B4", + "EventName": "FLA_VAL_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1." + }, + { + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1.", + "EventCode": "0x1B5", + "EventName": "FLB_VAL_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1." + }, + { + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#0.", + "EventCode": "0x240", + "EventName": "L1_PIPE0_VAL", + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." + }, + { + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#1.", + "EventCode": "0x241", + "EventName": "L1_PIPE1_VAL", + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.", + "EventCode": "0x250", + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1.", + "EventCode": "0x251", + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_PFE", + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.", + "EventCode": "0x252", + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1.", + "EventCode": "0x253", + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_PFE", + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1." + }, + { + "PublicDescription": "This event counts completed requests in L1D cache pipeline#0.", + "EventCode": "0x260", + "EventName": "L1_PIPE0_COMP", + "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." + }, + { + "PublicDescription": "This event counts completed requests in L1D cache pipeline#1.", + "EventCode": "0x261", + "EventName": "L1_PIPE1_COMP", + "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." + }, + { + "PublicDescription": "This event counts completed requests in L1I cache pipeline.", + "EventCode": "0x268", + "EventName": "L1I_PIPE_COMP", + "BriefDescription": "This event counts completed requests in L1I cache pipeline." + }, + { + "PublicDescription": "This event counts valid cycles of L1I cache pipeline.", + "EventCode": "0x269", + "EventName": "L1I_PIPE_VAL", + "BriefDescription": "This event counts valid cycles of L1I cache pipeline." + }, + { + "PublicDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock.", + "EventCode": "0x274", + "EventName": "L1_PIPE_ABORT_STLD_INTLK", + "BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0.", + "EventCode": "0x2A0", + "EventName": "L1_PIPE0_VAL_IU_NOT_SEC0", + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0." + }, + { + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0.", + "EventCode": "0x2A1", + "EventName": "L1_PIPE1_VAL_IU_NOT_SEC0", + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0." + }, + { + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", + "EventCode": "0x2B0", + "EventName": "L1_PIPE_COMP_GATHER_2FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined." + }, + { + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", + "EventCode": "0x2B1", + "EventName": "L1_PIPE_COMP_GATHER_1FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined." + }, + { + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", + "EventCode": "0x2B2", + "EventName": "L1_PIPE_COMP_GATHER_0FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0." + }, + { + "PublicDescription": "This event counts the number of flows of the scatter instructions.", + "EventCode": "0x2B3", + "EventName": "L1_PIPE_COMP_SCATTER_1FLOW", + "BriefDescription": "This event counts the number of flows of the scatter instructions." + }, + { + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1.", + "EventCode": "0x2B8", + "EventName": "L1_PIPE0_COMP_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1." + }, + { + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1.", + "EventCode": "0x2B9", + "EventName": "L1_PIPE1_COMP_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1." + }, + { + "PublicDescription": "This event counts valid cycles of L2 cache pipeline.", + "EventCode": "0x330", + "EventName": "L2_PIPE_VAL", + "BriefDescription": "This event counts valid cycles of L2 cache pipeline." + }, + { + "PublicDescription": "This event counts completed requests in L2 cache pipeline.", + "EventCode": "0x350", + "EventName": "L2_PIPE_COMP_ALL", + "BriefDescription": "This event counts completed requests in L2 cache pipeline." + }, + { + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", + "EventCode": "0x370", + "EventName": "L2_PIPE_COMP_PF_L2MIB_MCH", + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json new file mode 100644 index 000000000000..dc1b95e42c32 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json @@ -0,0 +1,110 @@ +[ + { + "ArchStdEvent": "SIMD_INST_RETIRED" + }, + { + "ArchStdEvent": "SVE_INST_RETIRED" + }, + { + "ArchStdEvent": "UOP_SPEC" + }, + { + "ArchStdEvent": "SVE_MATH_SPEC" + }, + { + "ArchStdEvent": "FP_SPEC" + }, + { + "ArchStdEvent": "FP_FMA_SPEC" + }, + { + "ArchStdEvent": "FP_RECPE_SPEC" + }, + { + "ArchStdEvent": "FP_CVT_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_SPEC" + }, + { + "ArchStdEvent": "SVE_MOVPRFX_SPEC" + }, + { + "ArchStdEvent": "SVE_MOVPRFX_U_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_LD_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_ST_SPEC" + }, + { + "ArchStdEvent": "PRF_SPEC" + }, + { + "ArchStdEvent": "BASE_LD_REG_SPEC" + }, + { + "ArchStdEvent": "BASE_ST_REG_SPEC" + }, + { + "ArchStdEvent": "SVE_LDR_REG_SPEC" + }, + { + "ArchStdEvent": "SVE_STR_REG_SPEC" + }, + { + "ArchStdEvent": "SVE_LDR_PREG_SPEC" + }, + { + "ArchStdEvent": "SVE_STR_PREG_SPEC" + }, + { + "ArchStdEvent": "SVE_PRF_CONTIG_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC" + }, + { + "ArchStdEvent": "SVE_LD_GATHER_SPEC" + }, + { + "ArchStdEvent": "SVE_ST_SCATTER_SPEC" + }, + { + "ArchStdEvent": "SVE_PRF_GATHER_SPEC" + }, + { + "ArchStdEvent": "SVE_LDFF_SPEC" + }, + { + "ArchStdEvent": "FP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_FIXED_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 0d609149b82a..c43591d831b8 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -20,5 +20,6 @@ 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core +0x00000000460f0010,v1,fujitsu/a64fx,core 0x00000000480fd010,v1,hisilicon/hip08,core 0x00000000500f0000,v1,ampere/emag,core -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/2] perf vendor events arm64: Add Fujitsu A64FX pmu event 2021-03-08 10:53 ` Shunsuke Nakamura @ 2021-03-09 16:59 ` Masayoshi Mizuma -1 siblings, 0 replies; 10+ messages in thread From: Masayoshi Mizuma @ 2021-03-09 16:59 UTC (permalink / raw) To: Shunsuke Nakamura Cc: john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung, linux-arm-kernel, linux-kernel On Mon, Mar 08, 2021 at 07:53:41PM +0900, Shunsuke Nakamura wrote: > Add pmu events for A64FX. > > Documentation source: > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf The PMU events described in above document seems to work well with this patch! Please feel free to add: Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com> Thanks! Masa > > Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com> > Reviewed-by: John Garry <john.garry@huawei.com> > --- > .../arch/arm64/fujitsu/a64fx/branch.json | 8 + > .../arch/arm64/fujitsu/a64fx/bus.json | 62 ++++++ > .../arch/arm64/fujitsu/a64fx/cache.json | 128 ++++++++++++ > .../arch/arm64/fujitsu/a64fx/cycle.json | 5 + > .../arch/arm64/fujitsu/a64fx/exception.json | 29 +++ > .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++++++++++ > .../arch/arm64/fujitsu/a64fx/memory.json | 8 + > .../arch/arm64/fujitsu/a64fx/other.json | 188 +++++++++++++++++ > .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 ++++++++++++++++++ > .../arch/arm64/fujitsu/a64fx/sve.json | 110 ++++++++++ > tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + > 11 files changed, 864 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > new file mode 100644 > index 000000000000..b011af11bf94 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > @@ -0,0 +1,8 @@ > +[ > + { > + "ArchStdEvent": "BR_MIS_PRED" > + }, > + { > + "ArchStdEvent": "BR_PRED" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > new file mode 100644 > index 000000000000..084e88d7df73 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > @@ -0,0 +1,62 @@ > +[ > + { > + "PublicDescription": "This event counts read transactions from tofu controller to measured CMG.", > + "EventCode": "0x314", > + "EventName": "BUS_READ_TOTAL_TOFU", > + "BriefDescription": "This event counts read transactions from tofu controller to measured CMG." > + }, > + { > + "PublicDescription": "This event counts read transactions from PCI controller to measured CMG.", > + "EventCode": "0x315", > + "EventName": "BUS_READ_TOTAL_PCI", > + "BriefDescription": "This event counts read transactions from PCI controller to measured CMG." > + }, > + { > + "PublicDescription": "This event counts read transactions from measured CMG local memory to measured CMG.", > + "EventCode": "0x316", > + "EventName": "BUS_READ_TOTAL_MEM", > + "BriefDescription": "This event counts read transactions from measured CMG local memory to measured CMG." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0.", > + "EventCode": "0x318", > + "EventName": "BUS_WRITE_TOTAL_CMG0", > + "BriefDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1.", > + "EventCode": "0x319", > + "EventName": "BUS_WRITE_TOTAL_CMG1", > + "BriefDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2.", > + "EventCode": "0x31A", > + "EventName": "BUS_WRITE_TOTAL_CMG2", > + "BriefDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3.", > + "EventCode": "0x31B", > + "EventName": "BUS_WRITE_TOTAL_CMG3", > + "BriefDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to tofu controller.", > + "EventCode": "0x31C", > + "EventName": "BUS_WRITE_TOTAL_TOFU", > + "BriefDescription": "This event counts write transactions from measured CMG to tofu controller." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to PCI controller.", > + "EventCode": "0x31D", > + "EventName": "BUS_WRITE_TOTAL_PCI", > + "BriefDescription": "This event counts write transactions from measured CMG to PCI controller." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to measured CMG local memory.", > + "EventCode": "0x31E", > + "EventName": "BUS_WRITE_TOTAL_MEM", > + "BriefDescription": "This event counts write transactions from measured CMG to measured CMG local memory." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > new file mode 100644 > index 000000000000..2e341a951a10 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > @@ -0,0 +1,128 @@ > +[ > + { > + "ArchStdEvent": "L1I_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L1I_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L1D_CACHE" > + }, > + { > + "ArchStdEvent": "L1D_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L1I_CACHE" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB" > + }, > + { > + "ArchStdEvent": "L2D_CACHE" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_WB" > + }, > + { > + "ArchStdEvent": "L2D_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L2I_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L2D_TLB" > + }, > + { > + "ArchStdEvent": "L2I_TLB" > + }, > + { > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", > + "EventCode": "0x49", > + "EventName": "L1D_CACHE_REFILL_PRF", > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", > + "EventCode": "0x59", > + "EventName": "L2D_CACHE_REFILL_PRF", > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.", > + "EventCode": "0x200", > + "EventName": "L1D_CACHE_REFILL_DM", > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." > + }, > + { > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", > + "EventCode": "0x202", > + "EventName": "L1D_CACHE_REFILL_HWPRF", > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", > + "EventCode": "0x208", > + "EventName": "L1_MISS_WAIT", > + "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." > + }, > + { > + "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.", > + "EventCode": "0x209", > + "EventName": "L1I_MISS_WAIT", > + "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle." > + }, > + { > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by demand access.", > + "EventCode": "0x300", > + "EventName": "L2D_CACHE_REFILL_DM", > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access." > + }, > + { > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch.", > + "EventCode": "0x302", > + "EventName": "L2D_CACHE_REFILL_HWPRF", > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.", > + "EventCode": "0x308", > + "EventName": "L2_MISS_WAIT", > + "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle." > + }, > + { > + "PublicDescription": "This event counts the number of times of L2 cache miss.", > + "EventCode": "0x309", > + "EventName": "L2_MISS_COUNT", > + "BriefDescription": "This event counts the number of times of L2 cache miss." > + }, > + { > + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", > + "EventCode": "0x325", > + "EventName": "L2D_SWAP_DM", > + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", > + "EventCode": "0x326", > + "EventName": "L2D_CACHE_MIBMCH_PRF", > + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." > + }, > + { > + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", > + "EventCode": "0x396", > + "EventName": "L2D_CACHE_SWAP_LOCAL", > + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts energy consumption per cycle of L2 cache.", > + "EventCode": "0x3E0", > + "EventName": "EA_L2", > + "BriefDescription": "This event counts energy consumption per cycle of L2 cache." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > new file mode 100644 > index 000000000000..b16484628290 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > @@ -0,0 +1,5 @@ > +[ > + { > + "ArchStdEvent": "CPU_CYCLES" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > new file mode 100644 > index 000000000000..348749c154c0 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > @@ -0,0 +1,29 @@ > +[ > + { > + "ArchStdEvent": "EXC_TAKEN" > + }, > + { > + "ArchStdEvent": "EXC_UNDEF" > + }, > + { > + "ArchStdEvent": "EXC_SVC" > + }, > + { > + "ArchStdEvent": "EXC_PABORT" > + }, > + { > + "ArchStdEvent": "EXC_DABORT" > + }, > + { > + "ArchStdEvent": "EXC_IRQ" > + }, > + { > + "ArchStdEvent": "EXC_FIQ" > + }, > + { > + "ArchStdEvent": "EXC_SMC" > + }, > + { > + "ArchStdEvent": "EXC_HVC" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > new file mode 100644 > index 000000000000..6d258b1080cf > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > @@ -0,0 +1,131 @@ > +[ > + { > + "ArchStdEvent": "SW_INCR" > + }, > + { > + "ArchStdEvent": "INST_RETIRED" > + }, > + { > + "ArchStdEvent": "EXC_RETURN" > + }, > + { > + "ArchStdEvent": "CID_WRITE_RETIRED" > + }, > + { > + "ArchStdEvent": "INST_SPEC" > + }, > + { > + "ArchStdEvent": "LDREX_SPEC" > + }, > + { > + "ArchStdEvent": "STREX_SPEC" > + }, > + { > + "ArchStdEvent": "LD_SPEC" > + }, > + { > + "ArchStdEvent": "ST_SPEC" > + }, > + { > + "ArchStdEvent": "LDST_SPEC" > + }, > + { > + "ArchStdEvent": "DP_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SPEC" > + }, > + { > + "ArchStdEvent": "VFP_SPEC" > + }, > + { > + "ArchStdEvent": "PC_WRITE_SPEC" > + }, > + { > + "ArchStdEvent": "CRYPTO_SPEC" > + }, > + { > + "ArchStdEvent": "BR_IMMED_SPEC" > + }, > + { > + "ArchStdEvent": "BR_RETURN_SPEC" > + }, > + { > + "ArchStdEvent": "BR_INDIRECT_SPEC" > + }, > + { > + "ArchStdEvent": "ISB_SPEC" > + }, > + { > + "ArchStdEvent": "DSB_SPEC" > + }, > + { > + "ArchStdEvent": "DMB_SPEC" > + }, > + { > + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", > + "EventCode": "0x9F", > + "EventName": "DCZVA_SPEC", > + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." > + }, > + { > + "PublicDescription": "This event counts architecturally executed floating-point move operations.", > + "EventCode": "0x105", > + "EventName": "FP_MV_SPEC", > + "BriefDescription": "This event counts architecturally executed floating-point move operations." > + }, > + { > + "PublicDescription": "This event counts architecturally executed operations that using predicate register.", > + "EventCode": "0x108", > + "EventName": "PRD_SPEC", > + "BriefDescription": "This event counts architecturally executed operations that using predicate register." > + }, > + { > + "PublicDescription": "This event counts architecturally executed inter-element manipulation operations.", > + "EventCode": "0x109", > + "EventName": "IEL_SPEC", > + "BriefDescription": "This event counts architecturally executed inter-element manipulation operations." > + }, > + { > + "PublicDescription": "This event counts architecturally executed inter-register manipulation operations.", > + "EventCode": "0x10A", > + "EventName": "IREG_SPEC", > + "BriefDescription": "This event counts architecturally executed inter-register manipulation operations." > + }, > + { > + "PublicDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.", > + "EventCode": "0x112", > + "EventName": "FP_LD_SPEC", > + "BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers." > + }, > + { > + "PublicDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.", > + "EventCode": "0x113", > + "EventName": "FP_ST_SPEC", > + "BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers." > + }, > + { > + "PublicDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations.", > + "EventCode": "0x11A", > + "EventName": "BC_LD_SPEC", > + "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations." > + }, > + { > + "PublicDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.", > + "EventCode": "0x121", > + "EventName": "EFFECTIVE_INST_SPEC", > + "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction." > + }, > + { > + "PublicDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.", > + "EventCode": "0x123", > + "EventName": "PRE_INDEX_SPEC", > + "BriefDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode." > + }, > + { > + "PublicDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode.", > + "EventCode": "0x124", > + "EventName": "POST_INDEX_SPEC", > + "BriefDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > new file mode 100644 > index 000000000000..c1f6479e92b4 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > @@ -0,0 +1,8 @@ > +[ > + { > + "PublicDescription": "This event counts energy consumption per cycle of CMG local memory.", > + "EventCode": "0x3E8", > + "EventName": "EA_MEMORY", > + "BriefDescription": "This event counts energy consumption per cycle of CMG local memory." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > new file mode 100644 > index 000000000000..10c823ac26cc > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > @@ -0,0 +1,188 @@ > +[ > + { > + "PublicDescription": "This event counts the occurrence count of the micro-operation split.", > + "EventCode": "0x139", > + "EventName": "UOP_SPLIT", > + "BriefDescription": "This event counts the occurrence count of the micro-operation split." > + }, > + { > + "PublicDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access.", > + "EventCode": "0x180", > + "EventName": "LD_COMP_WAIT_L2_MISS", > + "BriefDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access.", > + "EventCode": "0x181", > + "EventName": "LD_COMP_WAIT_L2_MISS_EX", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.", > + "EventCode": "0x182", > + "EventName": "LD_COMP_WAIT_L1_MISS", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.", > + "EventCode": "0x183", > + "EventName": "LD_COMP_WAIT_L1_MISS_EX", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", > + "EventCode": "0x184", > + "EventName": "LD_COMP_WAIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", > + "EventCode": "0x185", > + "EventName": "LD_COMP_WAIT_EX", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.", > + "EventCode": "0x186", > + "EventName": "LD_COMP_WAIT_PFP_BUSY", > + "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port." > + }, > + { > + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.", > + "EventCode": "0x187", > + "EventName": "LD_COMP_WAIT_PFP_BUSY_EX", > + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation." > + }, > + { > + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.", > + "EventCode": "0x188", > + "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF", > + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction.", > + "EventCode": "0x189", > + "EventName": "EU_COMP_WAIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.", > + "EventCode": "0x18A", > + "EventName": "FL_COMP_WAIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.", > + "EventCode": "0x18B", > + "EventName": "BR_COMP_WAIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty.", > + "EventCode": "0x18C", > + "EventName": "ROB_EMPTY", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.", > + "EventCode": "0x18D", > + "EventName": "ROB_EMPTY_STQ_BUSY", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full." > + }, > + { > + "PublicDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.", > + "EventCode": "0x18E", > + "EventName": "WFE_WFI_CYCLE", > + "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only.", > + "EventCode": "0x190", > + "EventName": "_0INST_COMMIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only." > + }, > + { > + "PublicDescription": "This event counts every cycle that one instruction is committed.", > + "EventCode": "0x191", > + "EventName": "_1INST_COMMIT", > + "BriefDescription": "This event counts every cycle that one instruction is committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that two instructions are committed.", > + "EventCode": "0x192", > + "EventName": "_2INST_COMMIT", > + "BriefDescription": "This event counts every cycle that two instructions are committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that three instructions are committed.", > + "EventCode": "0x193", > + "EventName": "_3INST_COMMIT", > + "BriefDescription": "This event counts every cycle that three instructions are committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that four instructions are committed.", > + "EventCode": "0x194", > + "EventName": "_4INST_COMMIT", > + "BriefDescription": "This event counts every cycle that four instructions are committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that only any micro-operations are committed.", > + "EventCode": "0x198", > + "EventName": "UOP_ONLY_COMMIT", > + "BriefDescription": "This event counts every cycle that only any micro-operations are committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that only the MOVPRFX instruction is committed.", > + "EventCode": "0x199", > + "EventName": "SINGLE_MOVPRFX_COMMIT", > + "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed." > + }, > + { > + "PublicDescription": "This event counts energy consumption per cycle of core.", > + "EventCode": "0x1E0", > + "EventName": "EA_CORE", > + "BriefDescription": "This event counts energy consumption per cycle of core." > + }, > + { > + "PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.", > + "EventCode": "0x230", > + "EventName": "L1HWPF_STREAM_PF", > + "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", > + "EventCode": "0x231", > + "EventName": "L1HWPF_INJ_ALLOC_PF", > + "BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", > + "EventCode": "0x232", > + "EventName": "L1HWPF_INJ_NOALLOC_PF", > + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.", > + "EventCode": "0x233", > + "EventName": "L2HWPF_STREAM_PF", > + "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher." > + }, > + { > + "PublicDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", > + "EventCode": "0x234", > + "EventName": "L2HWPF_INJ_ALLOC_PF", > + "BriefDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", > + "EventCode": "0x235", > + "EventName": "L2HWPF_INJ_NOALLOC_PF", > + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts prefetch requests to L2 cache generated by the other causes.", > + "EventCode": "0x236", > + "EventName": "L2HWPF_OTHER", > + "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > new file mode 100644 > index 000000000000..dd7c97a9972b > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > @@ -0,0 +1,194 @@ > +[ > + { > + "ArchStdEvent": "STALL_FRONTEND" > + }, > + { > + "ArchStdEvent": "STALL_BACKEND" > + }, > + { > + "PublicDescription": "This event counts valid cycles of EAGA pipeline.", > + "EventCode": "0x1A0", > + "EventName": "EAGA_VAL", > + "BriefDescription": "This event counts valid cycles of EAGA pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of EAGB pipeline.", > + "EventCode": "0x1A1", > + "EventName": "EAGB_VAL", > + "BriefDescription": "This event counts valid cycles of EAGB pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of EXA pipeline.", > + "EventCode": "0x1A2", > + "EventName": "EXA_VAL", > + "BriefDescription": "This event counts valid cycles of EXA pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of EXB pipeline.", > + "EventCode": "0x1A3", > + "EventName": "EXB_VAL", > + "BriefDescription": "This event counts valid cycles of EXB pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of FLA pipeline.", > + "EventCode": "0x1A4", > + "EventName": "FLA_VAL", > + "BriefDescription": "This event counts valid cycles of FLA pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of FLB pipeline.", > + "EventCode": "0x1A5", > + "EventName": "FLB_VAL", > + "BriefDescription": "This event counts valid cycles of FLB pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of PRX pipeline.", > + "EventCode": "0x1A6", > + "EventName": "PRX_VAL", > + "BriefDescription": "This event counts valid cycles of PRX pipeline." > + }, > + { > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1.", > + "EventCode": "0x1B4", > + "EventName": "FLA_VAL_PRD_CNT", > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1." > + }, > + { > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1.", > + "EventCode": "0x1B5", > + "EventName": "FLB_VAL_PRD_CNT", > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1." > + }, > + { > + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#0.", > + "EventCode": "0x240", > + "EventName": "L1_PIPE0_VAL", > + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." > + }, > + { > + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#1.", > + "EventCode": "0x241", > + "EventName": "L1_PIPE1_VAL", > + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.", > + "EventCode": "0x250", > + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1.", > + "EventCode": "0x251", > + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_PFE", > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.", > + "EventCode": "0x252", > + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1.", > + "EventCode": "0x253", > + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_PFE", > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1." > + }, > + { > + "PublicDescription": "This event counts completed requests in L1D cache pipeline#0.", > + "EventCode": "0x260", > + "EventName": "L1_PIPE0_COMP", > + "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." > + }, > + { > + "PublicDescription": "This event counts completed requests in L1D cache pipeline#1.", > + "EventCode": "0x261", > + "EventName": "L1_PIPE1_COMP", > + "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." > + }, > + { > + "PublicDescription": "This event counts completed requests in L1I cache pipeline.", > + "EventCode": "0x268", > + "EventName": "L1I_PIPE_COMP", > + "BriefDescription": "This event counts completed requests in L1I cache pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of L1I cache pipeline.", > + "EventCode": "0x269", > + "EventName": "L1I_PIPE_VAL", > + "BriefDescription": "This event counts valid cycles of L1I cache pipeline." > + }, > + { > + "PublicDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock.", > + "EventCode": "0x274", > + "EventName": "L1_PIPE_ABORT_STLD_INTLK", > + "BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0.", > + "EventCode": "0x2A0", > + "EventName": "L1_PIPE0_VAL_IU_NOT_SEC0", > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0.", > + "EventCode": "0x2A1", > + "EventName": "L1_PIPE1_VAL_IU_NOT_SEC0", > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0." > + }, > + { > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", > + "EventCode": "0x2B0", > + "EventName": "L1_PIPE_COMP_GATHER_2FLOW", > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined." > + }, > + { > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", > + "EventCode": "0x2B1", > + "EventName": "L1_PIPE_COMP_GATHER_1FLOW", > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined." > + }, > + { > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", > + "EventCode": "0x2B2", > + "EventName": "L1_PIPE_COMP_GATHER_0FLOW", > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0." > + }, > + { > + "PublicDescription": "This event counts the number of flows of the scatter instructions.", > + "EventCode": "0x2B3", > + "EventName": "L1_PIPE_COMP_SCATTER_1FLOW", > + "BriefDescription": "This event counts the number of flows of the scatter instructions." > + }, > + { > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1.", > + "EventCode": "0x2B8", > + "EventName": "L1_PIPE0_COMP_PRD_CNT", > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1." > + }, > + { > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1.", > + "EventCode": "0x2B9", > + "EventName": "L1_PIPE1_COMP_PRD_CNT", > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1." > + }, > + { > + "PublicDescription": "This event counts valid cycles of L2 cache pipeline.", > + "EventCode": "0x330", > + "EventName": "L2_PIPE_VAL", > + "BriefDescription": "This event counts valid cycles of L2 cache pipeline." > + }, > + { > + "PublicDescription": "This event counts completed requests in L2 cache pipeline.", > + "EventCode": "0x350", > + "EventName": "L2_PIPE_COMP_ALL", > + "BriefDescription": "This event counts completed requests in L2 cache pipeline." > + }, > + { > + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", > + "EventCode": "0x370", > + "EventName": "L2_PIPE_COMP_PF_L2MIB_MCH", > + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > new file mode 100644 > index 000000000000..dc1b95e42c32 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > @@ -0,0 +1,110 @@ > +[ > + { > + "ArchStdEvent": "SIMD_INST_RETIRED" > + }, > + { > + "ArchStdEvent": "SVE_INST_RETIRED" > + }, > + { > + "ArchStdEvent": "UOP_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_MATH_SPEC" > + }, > + { > + "ArchStdEvent": "FP_SPEC" > + }, > + { > + "ArchStdEvent": "FP_FMA_SPEC" > + }, > + { > + "ArchStdEvent": "FP_RECPE_SPEC" > + }, > + { > + "ArchStdEvent": "FP_CVT_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_INT_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_PRED_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_MOVPRFX_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_MOVPRFX_U_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_LD_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_ST_SPEC" > + }, > + { > + "ArchStdEvent": "PRF_SPEC" > + }, > + { > + "ArchStdEvent": "BASE_LD_REG_SPEC" > + }, > + { > + "ArchStdEvent": "BASE_ST_REG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_LDR_REG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_STR_REG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_LDR_PREG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_STR_PREG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_PRF_CONTIG_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_LD_GATHER_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_ST_SCATTER_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_PRF_GATHER_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_LDFF_SPEC" > + }, > + { > + "ArchStdEvent": "FP_SCALE_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_FIXED_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > index 0d609149b82a..c43591d831b8 100644 > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > @@ -20,5 +20,6 @@ > 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core > 0x00000000420f5160,v1,cavium/thunderx2,core > 0x00000000430f0af0,v1,cavium/thunderx2,core > +0x00000000460f0010,v1,fujitsu/a64fx,core > 0x00000000480fd010,v1,hisilicon/hip08,core > 0x00000000500f0000,v1,ampere/emag,core > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/2] perf vendor events arm64: Add Fujitsu A64FX pmu event @ 2021-03-09 16:59 ` Masayoshi Mizuma 0 siblings, 0 replies; 10+ messages in thread From: Masayoshi Mizuma @ 2021-03-09 16:59 UTC (permalink / raw) To: Shunsuke Nakamura Cc: john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung, linux-arm-kernel, linux-kernel On Mon, Mar 08, 2021 at 07:53:41PM +0900, Shunsuke Nakamura wrote: > Add pmu events for A64FX. > > Documentation source: > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf The PMU events described in above document seems to work well with this patch! Please feel free to add: Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com> Thanks! Masa > > Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com> > Reviewed-by: John Garry <john.garry@huawei.com> > --- > .../arch/arm64/fujitsu/a64fx/branch.json | 8 + > .../arch/arm64/fujitsu/a64fx/bus.json | 62 ++++++ > .../arch/arm64/fujitsu/a64fx/cache.json | 128 ++++++++++++ > .../arch/arm64/fujitsu/a64fx/cycle.json | 5 + > .../arch/arm64/fujitsu/a64fx/exception.json | 29 +++ > .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++++++++++ > .../arch/arm64/fujitsu/a64fx/memory.json | 8 + > .../arch/arm64/fujitsu/a64fx/other.json | 188 +++++++++++++++++ > .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 ++++++++++++++++++ > .../arch/arm64/fujitsu/a64fx/sve.json | 110 ++++++++++ > tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + > 11 files changed, 864 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > new file mode 100644 > index 000000000000..b011af11bf94 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > @@ -0,0 +1,8 @@ > +[ > + { > + "ArchStdEvent": "BR_MIS_PRED" > + }, > + { > + "ArchStdEvent": "BR_PRED" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > new file mode 100644 > index 000000000000..084e88d7df73 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > @@ -0,0 +1,62 @@ > +[ > + { > + "PublicDescription": "This event counts read transactions from tofu controller to measured CMG.", > + "EventCode": "0x314", > + "EventName": "BUS_READ_TOTAL_TOFU", > + "BriefDescription": "This event counts read transactions from tofu controller to measured CMG." > + }, > + { > + "PublicDescription": "This event counts read transactions from PCI controller to measured CMG.", > + "EventCode": "0x315", > + "EventName": "BUS_READ_TOTAL_PCI", > + "BriefDescription": "This event counts read transactions from PCI controller to measured CMG." > + }, > + { > + "PublicDescription": "This event counts read transactions from measured CMG local memory to measured CMG.", > + "EventCode": "0x316", > + "EventName": "BUS_READ_TOTAL_MEM", > + "BriefDescription": "This event counts read transactions from measured CMG local memory to measured CMG." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0.", > + "EventCode": "0x318", > + "EventName": "BUS_WRITE_TOTAL_CMG0", > + "BriefDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1.", > + "EventCode": "0x319", > + "EventName": "BUS_WRITE_TOTAL_CMG1", > + "BriefDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2.", > + "EventCode": "0x31A", > + "EventName": "BUS_WRITE_TOTAL_CMG2", > + "BriefDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3.", > + "EventCode": "0x31B", > + "EventName": "BUS_WRITE_TOTAL_CMG3", > + "BriefDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to tofu controller.", > + "EventCode": "0x31C", > + "EventName": "BUS_WRITE_TOTAL_TOFU", > + "BriefDescription": "This event counts write transactions from measured CMG to tofu controller." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to PCI controller.", > + "EventCode": "0x31D", > + "EventName": "BUS_WRITE_TOTAL_PCI", > + "BriefDescription": "This event counts write transactions from measured CMG to PCI controller." > + }, > + { > + "PublicDescription": "This event counts write transactions from measured CMG to measured CMG local memory.", > + "EventCode": "0x31E", > + "EventName": "BUS_WRITE_TOTAL_MEM", > + "BriefDescription": "This event counts write transactions from measured CMG to measured CMG local memory." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > new file mode 100644 > index 000000000000..2e341a951a10 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > @@ -0,0 +1,128 @@ > +[ > + { > + "ArchStdEvent": "L1I_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L1I_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L1D_CACHE" > + }, > + { > + "ArchStdEvent": "L1D_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L1I_CACHE" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB" > + }, > + { > + "ArchStdEvent": "L2D_CACHE" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_WB" > + }, > + { > + "ArchStdEvent": "L2D_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L2I_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L2D_TLB" > + }, > + { > + "ArchStdEvent": "L2I_TLB" > + }, > + { > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", > + "EventCode": "0x49", > + "EventName": "L1D_CACHE_REFILL_PRF", > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", > + "EventCode": "0x59", > + "EventName": "L2D_CACHE_REFILL_PRF", > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.", > + "EventCode": "0x200", > + "EventName": "L1D_CACHE_REFILL_DM", > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." > + }, > + { > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", > + "EventCode": "0x202", > + "EventName": "L1D_CACHE_REFILL_HWPRF", > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", > + "EventCode": "0x208", > + "EventName": "L1_MISS_WAIT", > + "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." > + }, > + { > + "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.", > + "EventCode": "0x209", > + "EventName": "L1I_MISS_WAIT", > + "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle." > + }, > + { > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by demand access.", > + "EventCode": "0x300", > + "EventName": "L2D_CACHE_REFILL_DM", > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access." > + }, > + { > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch.", > + "EventCode": "0x302", > + "EventName": "L2D_CACHE_REFILL_HWPRF", > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.", > + "EventCode": "0x308", > + "EventName": "L2_MISS_WAIT", > + "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle." > + }, > + { > + "PublicDescription": "This event counts the number of times of L2 cache miss.", > + "EventCode": "0x309", > + "EventName": "L2_MISS_COUNT", > + "BriefDescription": "This event counts the number of times of L2 cache miss." > + }, > + { > + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", > + "EventCode": "0x325", > + "EventName": "L2D_SWAP_DM", > + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", > + "EventCode": "0x326", > + "EventName": "L2D_CACHE_MIBMCH_PRF", > + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." > + }, > + { > + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", > + "EventCode": "0x396", > + "EventName": "L2D_CACHE_SWAP_LOCAL", > + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." > + }, > + { > + "PublicDescription": "This event counts energy consumption per cycle of L2 cache.", > + "EventCode": "0x3E0", > + "EventName": "EA_L2", > + "BriefDescription": "This event counts energy consumption per cycle of L2 cache." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > new file mode 100644 > index 000000000000..b16484628290 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > @@ -0,0 +1,5 @@ > +[ > + { > + "ArchStdEvent": "CPU_CYCLES" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > new file mode 100644 > index 000000000000..348749c154c0 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > @@ -0,0 +1,29 @@ > +[ > + { > + "ArchStdEvent": "EXC_TAKEN" > + }, > + { > + "ArchStdEvent": "EXC_UNDEF" > + }, > + { > + "ArchStdEvent": "EXC_SVC" > + }, > + { > + "ArchStdEvent": "EXC_PABORT" > + }, > + { > + "ArchStdEvent": "EXC_DABORT" > + }, > + { > + "ArchStdEvent": "EXC_IRQ" > + }, > + { > + "ArchStdEvent": "EXC_FIQ" > + }, > + { > + "ArchStdEvent": "EXC_SMC" > + }, > + { > + "ArchStdEvent": "EXC_HVC" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > new file mode 100644 > index 000000000000..6d258b1080cf > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > @@ -0,0 +1,131 @@ > +[ > + { > + "ArchStdEvent": "SW_INCR" > + }, > + { > + "ArchStdEvent": "INST_RETIRED" > + }, > + { > + "ArchStdEvent": "EXC_RETURN" > + }, > + { > + "ArchStdEvent": "CID_WRITE_RETIRED" > + }, > + { > + "ArchStdEvent": "INST_SPEC" > + }, > + { > + "ArchStdEvent": "LDREX_SPEC" > + }, > + { > + "ArchStdEvent": "STREX_SPEC" > + }, > + { > + "ArchStdEvent": "LD_SPEC" > + }, > + { > + "ArchStdEvent": "ST_SPEC" > + }, > + { > + "ArchStdEvent": "LDST_SPEC" > + }, > + { > + "ArchStdEvent": "DP_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SPEC" > + }, > + { > + "ArchStdEvent": "VFP_SPEC" > + }, > + { > + "ArchStdEvent": "PC_WRITE_SPEC" > + }, > + { > + "ArchStdEvent": "CRYPTO_SPEC" > + }, > + { > + "ArchStdEvent": "BR_IMMED_SPEC" > + }, > + { > + "ArchStdEvent": "BR_RETURN_SPEC" > + }, > + { > + "ArchStdEvent": "BR_INDIRECT_SPEC" > + }, > + { > + "ArchStdEvent": "ISB_SPEC" > + }, > + { > + "ArchStdEvent": "DSB_SPEC" > + }, > + { > + "ArchStdEvent": "DMB_SPEC" > + }, > + { > + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", > + "EventCode": "0x9F", > + "EventName": "DCZVA_SPEC", > + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." > + }, > + { > + "PublicDescription": "This event counts architecturally executed floating-point move operations.", > + "EventCode": "0x105", > + "EventName": "FP_MV_SPEC", > + "BriefDescription": "This event counts architecturally executed floating-point move operations." > + }, > + { > + "PublicDescription": "This event counts architecturally executed operations that using predicate register.", > + "EventCode": "0x108", > + "EventName": "PRD_SPEC", > + "BriefDescription": "This event counts architecturally executed operations that using predicate register." > + }, > + { > + "PublicDescription": "This event counts architecturally executed inter-element manipulation operations.", > + "EventCode": "0x109", > + "EventName": "IEL_SPEC", > + "BriefDescription": "This event counts architecturally executed inter-element manipulation operations." > + }, > + { > + "PublicDescription": "This event counts architecturally executed inter-register manipulation operations.", > + "EventCode": "0x10A", > + "EventName": "IREG_SPEC", > + "BriefDescription": "This event counts architecturally executed inter-register manipulation operations." > + }, > + { > + "PublicDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.", > + "EventCode": "0x112", > + "EventName": "FP_LD_SPEC", > + "BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers." > + }, > + { > + "PublicDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.", > + "EventCode": "0x113", > + "EventName": "FP_ST_SPEC", > + "BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers." > + }, > + { > + "PublicDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations.", > + "EventCode": "0x11A", > + "EventName": "BC_LD_SPEC", > + "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations." > + }, > + { > + "PublicDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.", > + "EventCode": "0x121", > + "EventName": "EFFECTIVE_INST_SPEC", > + "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction." > + }, > + { > + "PublicDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.", > + "EventCode": "0x123", > + "EventName": "PRE_INDEX_SPEC", > + "BriefDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode." > + }, > + { > + "PublicDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode.", > + "EventCode": "0x124", > + "EventName": "POST_INDEX_SPEC", > + "BriefDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > new file mode 100644 > index 000000000000..c1f6479e92b4 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > @@ -0,0 +1,8 @@ > +[ > + { > + "PublicDescription": "This event counts energy consumption per cycle of CMG local memory.", > + "EventCode": "0x3E8", > + "EventName": "EA_MEMORY", > + "BriefDescription": "This event counts energy consumption per cycle of CMG local memory." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > new file mode 100644 > index 000000000000..10c823ac26cc > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > @@ -0,0 +1,188 @@ > +[ > + { > + "PublicDescription": "This event counts the occurrence count of the micro-operation split.", > + "EventCode": "0x139", > + "EventName": "UOP_SPLIT", > + "BriefDescription": "This event counts the occurrence count of the micro-operation split." > + }, > + { > + "PublicDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access.", > + "EventCode": "0x180", > + "EventName": "LD_COMP_WAIT_L2_MISS", > + "BriefDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access.", > + "EventCode": "0x181", > + "EventName": "LD_COMP_WAIT_L2_MISS_EX", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.", > + "EventCode": "0x182", > + "EventName": "LD_COMP_WAIT_L1_MISS", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.", > + "EventCode": "0x183", > + "EventName": "LD_COMP_WAIT_L1_MISS_EX", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", > + "EventCode": "0x184", > + "EventName": "LD_COMP_WAIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", > + "EventCode": "0x185", > + "EventName": "LD_COMP_WAIT_EX", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.", > + "EventCode": "0x186", > + "EventName": "LD_COMP_WAIT_PFP_BUSY", > + "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port." > + }, > + { > + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.", > + "EventCode": "0x187", > + "EventName": "LD_COMP_WAIT_PFP_BUSY_EX", > + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation." > + }, > + { > + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.", > + "EventCode": "0x188", > + "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF", > + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction.", > + "EventCode": "0x189", > + "EventName": "EU_COMP_WAIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.", > + "EventCode": "0x18A", > + "EventName": "FL_COMP_WAIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.", > + "EventCode": "0x18B", > + "EventName": "BR_COMP_WAIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty.", > + "EventCode": "0x18C", > + "EventName": "ROB_EMPTY", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.", > + "EventCode": "0x18D", > + "EventName": "ROB_EMPTY_STQ_BUSY", > + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full." > + }, > + { > + "PublicDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.", > + "EventCode": "0x18E", > + "EventName": "WFE_WFI_CYCLE", > + "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction." > + }, > + { > + "PublicDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only.", > + "EventCode": "0x190", > + "EventName": "_0INST_COMMIT", > + "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only." > + }, > + { > + "PublicDescription": "This event counts every cycle that one instruction is committed.", > + "EventCode": "0x191", > + "EventName": "_1INST_COMMIT", > + "BriefDescription": "This event counts every cycle that one instruction is committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that two instructions are committed.", > + "EventCode": "0x192", > + "EventName": "_2INST_COMMIT", > + "BriefDescription": "This event counts every cycle that two instructions are committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that three instructions are committed.", > + "EventCode": "0x193", > + "EventName": "_3INST_COMMIT", > + "BriefDescription": "This event counts every cycle that three instructions are committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that four instructions are committed.", > + "EventCode": "0x194", > + "EventName": "_4INST_COMMIT", > + "BriefDescription": "This event counts every cycle that four instructions are committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that only any micro-operations are committed.", > + "EventCode": "0x198", > + "EventName": "UOP_ONLY_COMMIT", > + "BriefDescription": "This event counts every cycle that only any micro-operations are committed." > + }, > + { > + "PublicDescription": "This event counts every cycle that only the MOVPRFX instruction is committed.", > + "EventCode": "0x199", > + "EventName": "SINGLE_MOVPRFX_COMMIT", > + "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed." > + }, > + { > + "PublicDescription": "This event counts energy consumption per cycle of core.", > + "EventCode": "0x1E0", > + "EventName": "EA_CORE", > + "BriefDescription": "This event counts energy consumption per cycle of core." > + }, > + { > + "PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.", > + "EventCode": "0x230", > + "EventName": "L1HWPF_STREAM_PF", > + "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", > + "EventCode": "0x231", > + "EventName": "L1HWPF_INJ_ALLOC_PF", > + "BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", > + "EventCode": "0x232", > + "EventName": "L1HWPF_INJ_NOALLOC_PF", > + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.", > + "EventCode": "0x233", > + "EventName": "L2HWPF_STREAM_PF", > + "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher." > + }, > + { > + "PublicDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", > + "EventCode": "0x234", > + "EventName": "L2HWPF_INJ_ALLOC_PF", > + "BriefDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", > + "EventCode": "0x235", > + "EventName": "L2HWPF_INJ_NOALLOC_PF", > + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." > + }, > + { > + "PublicDescription": "This event counts prefetch requests to L2 cache generated by the other causes.", > + "EventCode": "0x236", > + "EventName": "L2HWPF_OTHER", > + "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > new file mode 100644 > index 000000000000..dd7c97a9972b > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > @@ -0,0 +1,194 @@ > +[ > + { > + "ArchStdEvent": "STALL_FRONTEND" > + }, > + { > + "ArchStdEvent": "STALL_BACKEND" > + }, > + { > + "PublicDescription": "This event counts valid cycles of EAGA pipeline.", > + "EventCode": "0x1A0", > + "EventName": "EAGA_VAL", > + "BriefDescription": "This event counts valid cycles of EAGA pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of EAGB pipeline.", > + "EventCode": "0x1A1", > + "EventName": "EAGB_VAL", > + "BriefDescription": "This event counts valid cycles of EAGB pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of EXA pipeline.", > + "EventCode": "0x1A2", > + "EventName": "EXA_VAL", > + "BriefDescription": "This event counts valid cycles of EXA pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of EXB pipeline.", > + "EventCode": "0x1A3", > + "EventName": "EXB_VAL", > + "BriefDescription": "This event counts valid cycles of EXB pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of FLA pipeline.", > + "EventCode": "0x1A4", > + "EventName": "FLA_VAL", > + "BriefDescription": "This event counts valid cycles of FLA pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of FLB pipeline.", > + "EventCode": "0x1A5", > + "EventName": "FLB_VAL", > + "BriefDescription": "This event counts valid cycles of FLB pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of PRX pipeline.", > + "EventCode": "0x1A6", > + "EventName": "PRX_VAL", > + "BriefDescription": "This event counts valid cycles of PRX pipeline." > + }, > + { > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1.", > + "EventCode": "0x1B4", > + "EventName": "FLA_VAL_PRD_CNT", > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1." > + }, > + { > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1.", > + "EventCode": "0x1B5", > + "EventName": "FLB_VAL_PRD_CNT", > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1." > + }, > + { > + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#0.", > + "EventCode": "0x240", > + "EventName": "L1_PIPE0_VAL", > + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." > + }, > + { > + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#1.", > + "EventCode": "0x241", > + "EventName": "L1_PIPE1_VAL", > + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.", > + "EventCode": "0x250", > + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1.", > + "EventCode": "0x251", > + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_PFE", > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.", > + "EventCode": "0x252", > + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1.", > + "EventCode": "0x253", > + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_PFE", > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1." > + }, > + { > + "PublicDescription": "This event counts completed requests in L1D cache pipeline#0.", > + "EventCode": "0x260", > + "EventName": "L1_PIPE0_COMP", > + "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." > + }, > + { > + "PublicDescription": "This event counts completed requests in L1D cache pipeline#1.", > + "EventCode": "0x261", > + "EventName": "L1_PIPE1_COMP", > + "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." > + }, > + { > + "PublicDescription": "This event counts completed requests in L1I cache pipeline.", > + "EventCode": "0x268", > + "EventName": "L1I_PIPE_COMP", > + "BriefDescription": "This event counts completed requests in L1I cache pipeline." > + }, > + { > + "PublicDescription": "This event counts valid cycles of L1I cache pipeline.", > + "EventCode": "0x269", > + "EventName": "L1I_PIPE_VAL", > + "BriefDescription": "This event counts valid cycles of L1I cache pipeline." > + }, > + { > + "PublicDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock.", > + "EventCode": "0x274", > + "EventName": "L1_PIPE_ABORT_STLD_INTLK", > + "BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0.", > + "EventCode": "0x2A0", > + "EventName": "L1_PIPE0_VAL_IU_NOT_SEC0", > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0." > + }, > + { > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0.", > + "EventCode": "0x2A1", > + "EventName": "L1_PIPE1_VAL_IU_NOT_SEC0", > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0." > + }, > + { > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", > + "EventCode": "0x2B0", > + "EventName": "L1_PIPE_COMP_GATHER_2FLOW", > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined." > + }, > + { > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", > + "EventCode": "0x2B1", > + "EventName": "L1_PIPE_COMP_GATHER_1FLOW", > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined." > + }, > + { > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", > + "EventCode": "0x2B2", > + "EventName": "L1_PIPE_COMP_GATHER_0FLOW", > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0." > + }, > + { > + "PublicDescription": "This event counts the number of flows of the scatter instructions.", > + "EventCode": "0x2B3", > + "EventName": "L1_PIPE_COMP_SCATTER_1FLOW", > + "BriefDescription": "This event counts the number of flows of the scatter instructions." > + }, > + { > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1.", > + "EventCode": "0x2B8", > + "EventName": "L1_PIPE0_COMP_PRD_CNT", > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1." > + }, > + { > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1.", > + "EventCode": "0x2B9", > + "EventName": "L1_PIPE1_COMP_PRD_CNT", > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1." > + }, > + { > + "PublicDescription": "This event counts valid cycles of L2 cache pipeline.", > + "EventCode": "0x330", > + "EventName": "L2_PIPE_VAL", > + "BriefDescription": "This event counts valid cycles of L2 cache pipeline." > + }, > + { > + "PublicDescription": "This event counts completed requests in L2 cache pipeline.", > + "EventCode": "0x350", > + "EventName": "L2_PIPE_COMP_ALL", > + "BriefDescription": "This event counts completed requests in L2 cache pipeline." > + }, > + { > + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", > + "EventCode": "0x370", > + "EventName": "L2_PIPE_COMP_PF_L2MIB_MCH", > + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > new file mode 100644 > index 000000000000..dc1b95e42c32 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > @@ -0,0 +1,110 @@ > +[ > + { > + "ArchStdEvent": "SIMD_INST_RETIRED" > + }, > + { > + "ArchStdEvent": "SVE_INST_RETIRED" > + }, > + { > + "ArchStdEvent": "UOP_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_MATH_SPEC" > + }, > + { > + "ArchStdEvent": "FP_SPEC" > + }, > + { > + "ArchStdEvent": "FP_FMA_SPEC" > + }, > + { > + "ArchStdEvent": "FP_RECPE_SPEC" > + }, > + { > + "ArchStdEvent": "FP_CVT_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_INT_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_PRED_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_MOVPRFX_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_MOVPRFX_U_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_LD_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_ST_SPEC" > + }, > + { > + "ArchStdEvent": "PRF_SPEC" > + }, > + { > + "ArchStdEvent": "BASE_LD_REG_SPEC" > + }, > + { > + "ArchStdEvent": "BASE_ST_REG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_LDR_REG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_STR_REG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_LDR_PREG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_STR_PREG_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_PRF_CONTIG_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_LD_GATHER_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_ST_SCATTER_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_PRF_GATHER_SPEC" > + }, > + { > + "ArchStdEvent": "SVE_LDFF_SPEC" > + }, > + { > + "ArchStdEvent": "FP_SCALE_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_FIXED_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC" > + }, > + { > + "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > index 0d609149b82a..c43591d831b8 100644 > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > @@ -20,5 +20,6 @@ > 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core > 0x00000000420f5160,v1,cavium/thunderx2,core > 0x00000000430f0af0,v1,cavium/thunderx2,core > +0x00000000460f0010,v1,fujitsu/a64fx,core > 0x00000000480fd010,v1,hisilicon/hip08,core > 0x00000000500f0000,v1,ampere/emag,core > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/2] perf vendor events arm64: Add Fujitsu A64FX pmu event 2021-03-09 16:59 ` Masayoshi Mizuma @ 2021-03-15 13:49 ` Arnaldo Carvalho de Melo -1 siblings, 0 replies; 10+ messages in thread From: Arnaldo Carvalho de Melo @ 2021-03-15 13:49 UTC (permalink / raw) To: Masayoshi Mizuma Cc: Shunsuke Nakamura, john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, mark.rutland, alexander.shishkin, jolsa, namhyung, linux-arm-kernel, linux-kernel Em Tue, Mar 09, 2021 at 11:59:18AM -0500, Masayoshi Mizuma escreveu: > On Mon, Mar 08, 2021 at 07:53:41PM +0900, Shunsuke Nakamura wrote: > > Add pmu events for A64FX. > > > > Documentation source: > > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf > > The PMU events described in above document seems to work well > with this patch! > Please feel free to add: > > Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com> Thanks, applied. - Arnaldo > Thanks! > Masa > > > > > Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com> > > Reviewed-by: John Garry <john.garry@huawei.com> > > --- > > .../arch/arm64/fujitsu/a64fx/branch.json | 8 + > > .../arch/arm64/fujitsu/a64fx/bus.json | 62 ++++++ > > .../arch/arm64/fujitsu/a64fx/cache.json | 128 ++++++++++++ > > .../arch/arm64/fujitsu/a64fx/cycle.json | 5 + > > .../arch/arm64/fujitsu/a64fx/exception.json | 29 +++ > > .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++++++++++ > > .../arch/arm64/fujitsu/a64fx/memory.json | 8 + > > .../arch/arm64/fujitsu/a64fx/other.json | 188 +++++++++++++++++ > > .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 ++++++++++++++++++ > > .../arch/arm64/fujitsu/a64fx/sve.json | 110 ++++++++++ > > tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + > > 11 files changed, 864 insertions(+) > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > > > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > > new file mode 100644 > > index 000000000000..b011af11bf94 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > > @@ -0,0 +1,8 @@ > > +[ > > + { > > + "ArchStdEvent": "BR_MIS_PRED" > > + }, > > + { > > + "ArchStdEvent": "BR_PRED" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > > new file mode 100644 > > index 000000000000..084e88d7df73 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > > @@ -0,0 +1,62 @@ > > +[ > > + { > > + "PublicDescription": "This event counts read transactions from tofu controller to measured CMG.", > > + "EventCode": "0x314", > > + "EventName": "BUS_READ_TOTAL_TOFU", > > + "BriefDescription": "This event counts read transactions from tofu controller to measured CMG." > > + }, > > + { > > + "PublicDescription": "This event counts read transactions from PCI controller to measured CMG.", > > + "EventCode": "0x315", > > + "EventName": "BUS_READ_TOTAL_PCI", > > + "BriefDescription": "This event counts read transactions from PCI controller to measured CMG." > > + }, > > + { > > + "PublicDescription": "This event counts read transactions from measured CMG local memory to measured CMG.", > > + "EventCode": "0x316", > > + "EventName": "BUS_READ_TOTAL_MEM", > > + "BriefDescription": "This event counts read transactions from measured CMG local memory to measured CMG." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0.", > > + "EventCode": "0x318", > > + "EventName": "BUS_WRITE_TOTAL_CMG0", > > + "BriefDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1.", > > + "EventCode": "0x319", > > + "EventName": "BUS_WRITE_TOTAL_CMG1", > > + "BriefDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2.", > > + "EventCode": "0x31A", > > + "EventName": "BUS_WRITE_TOTAL_CMG2", > > + "BriefDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3.", > > + "EventCode": "0x31B", > > + "EventName": "BUS_WRITE_TOTAL_CMG3", > > + "BriefDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to tofu controller.", > > + "EventCode": "0x31C", > > + "EventName": "BUS_WRITE_TOTAL_TOFU", > > + "BriefDescription": "This event counts write transactions from measured CMG to tofu controller." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to PCI controller.", > > + "EventCode": "0x31D", > > + "EventName": "BUS_WRITE_TOTAL_PCI", > > + "BriefDescription": "This event counts write transactions from measured CMG to PCI controller." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to measured CMG local memory.", > > + "EventCode": "0x31E", > > + "EventName": "BUS_WRITE_TOTAL_MEM", > > + "BriefDescription": "This event counts write transactions from measured CMG to measured CMG local memory." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > > new file mode 100644 > > index 000000000000..2e341a951a10 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > > @@ -0,0 +1,128 @@ > > +[ > > + { > > + "ArchStdEvent": "L1I_CACHE_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L1I_TLB_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L1D_CACHE_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L1D_CACHE" > > + }, > > + { > > + "ArchStdEvent": "L1D_TLB_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L1I_CACHE" > > + }, > > + { > > + "ArchStdEvent": "L1D_CACHE_WB" > > + }, > > + { > > + "ArchStdEvent": "L2D_CACHE" > > + }, > > + { > > + "ArchStdEvent": "L2D_CACHE_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L2D_CACHE_WB" > > + }, > > + { > > + "ArchStdEvent": "L2D_TLB_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L2I_TLB_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L2D_TLB" > > + }, > > + { > > + "ArchStdEvent": "L2I_TLB" > > + }, > > + { > > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", > > + "EventCode": "0x49", > > + "EventName": "L1D_CACHE_REFILL_PRF", > > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", > > + "EventCode": "0x59", > > + "EventName": "L2D_CACHE_REFILL_PRF", > > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.", > > + "EventCode": "0x200", > > + "EventName": "L1D_CACHE_REFILL_DM", > > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." > > + }, > > + { > > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", > > + "EventCode": "0x202", > > + "EventName": "L1D_CACHE_REFILL_HWPRF", > > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", > > + "EventCode": "0x208", > > + "EventName": "L1_MISS_WAIT", > > + "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." > > + }, > > + { > > + "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.", > > + "EventCode": "0x209", > > + "EventName": "L1I_MISS_WAIT", > > + "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle." > > + }, > > + { > > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by demand access.", > > + "EventCode": "0x300", > > + "EventName": "L2D_CACHE_REFILL_DM", > > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access." > > + }, > > + { > > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch.", > > + "EventCode": "0x302", > > + "EventName": "L2D_CACHE_REFILL_HWPRF", > > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.", > > + "EventCode": "0x308", > > + "EventName": "L2_MISS_WAIT", > > + "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle." > > + }, > > + { > > + "PublicDescription": "This event counts the number of times of L2 cache miss.", > > + "EventCode": "0x309", > > + "EventName": "L2_MISS_COUNT", > > + "BriefDescription": "This event counts the number of times of L2 cache miss." > > + }, > > + { > > + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", > > + "EventCode": "0x325", > > + "EventName": "L2D_SWAP_DM", > > + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", > > + "EventCode": "0x326", > > + "EventName": "L2D_CACHE_MIBMCH_PRF", > > + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." > > + }, > > + { > > + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", > > + "EventCode": "0x396", > > + "EventName": "L2D_CACHE_SWAP_LOCAL", > > + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts energy consumption per cycle of L2 cache.", > > + "EventCode": "0x3E0", > > + "EventName": "EA_L2", > > + "BriefDescription": "This event counts energy consumption per cycle of L2 cache." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > > new file mode 100644 > > index 000000000000..b16484628290 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > > @@ -0,0 +1,5 @@ > > +[ > > + { > > + "ArchStdEvent": "CPU_CYCLES" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > > new file mode 100644 > > index 000000000000..348749c154c0 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > > @@ -0,0 +1,29 @@ > > +[ > > + { > > + "ArchStdEvent": "EXC_TAKEN" > > + }, > > + { > > + "ArchStdEvent": "EXC_UNDEF" > > + }, > > + { > > + "ArchStdEvent": "EXC_SVC" > > + }, > > + { > > + "ArchStdEvent": "EXC_PABORT" > > + }, > > + { > > + "ArchStdEvent": "EXC_DABORT" > > + }, > > + { > > + "ArchStdEvent": "EXC_IRQ" > > + }, > > + { > > + "ArchStdEvent": "EXC_FIQ" > > + }, > > + { > > + "ArchStdEvent": "EXC_SMC" > > + }, > > + { > > + "ArchStdEvent": "EXC_HVC" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > > new file mode 100644 > > index 000000000000..6d258b1080cf > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > > @@ -0,0 +1,131 @@ > > +[ > > + { > > + "ArchStdEvent": "SW_INCR" > > + }, > > + { > > + "ArchStdEvent": "INST_RETIRED" > > + }, > > + { > > + "ArchStdEvent": "EXC_RETURN" > > + }, > > + { > > + "ArchStdEvent": "CID_WRITE_RETIRED" > > + }, > > + { > > + "ArchStdEvent": "INST_SPEC" > > + }, > > + { > > + "ArchStdEvent": "LDREX_SPEC" > > + }, > > + { > > + "ArchStdEvent": "STREX_SPEC" > > + }, > > + { > > + "ArchStdEvent": "LD_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ST_SPEC" > > + }, > > + { > > + "ArchStdEvent": "LDST_SPEC" > > + }, > > + { > > + "ArchStdEvent": "DP_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SPEC" > > + }, > > + { > > + "ArchStdEvent": "VFP_SPEC" > > + }, > > + { > > + "ArchStdEvent": "PC_WRITE_SPEC" > > + }, > > + { > > + "ArchStdEvent": "CRYPTO_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BR_IMMED_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BR_RETURN_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BR_INDIRECT_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ISB_SPEC" > > + }, > > + { > > + "ArchStdEvent": "DSB_SPEC" > > + }, > > + { > > + "ArchStdEvent": "DMB_SPEC" > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", > > + "EventCode": "0x9F", > > + "EventName": "DCZVA_SPEC", > > + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed floating-point move operations.", > > + "EventCode": "0x105", > > + "EventName": "FP_MV_SPEC", > > + "BriefDescription": "This event counts architecturally executed floating-point move operations." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed operations that using predicate register.", > > + "EventCode": "0x108", > > + "EventName": "PRD_SPEC", > > + "BriefDescription": "This event counts architecturally executed operations that using predicate register." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed inter-element manipulation operations.", > > + "EventCode": "0x109", > > + "EventName": "IEL_SPEC", > > + "BriefDescription": "This event counts architecturally executed inter-element manipulation operations." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed inter-register manipulation operations.", > > + "EventCode": "0x10A", > > + "EventName": "IREG_SPEC", > > + "BriefDescription": "This event counts architecturally executed inter-register manipulation operations." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.", > > + "EventCode": "0x112", > > + "EventName": "FP_LD_SPEC", > > + "BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.", > > + "EventCode": "0x113", > > + "EventName": "FP_ST_SPEC", > > + "BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations.", > > + "EventCode": "0x11A", > > + "EventName": "BC_LD_SPEC", > > + "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.", > > + "EventCode": "0x121", > > + "EventName": "EFFECTIVE_INST_SPEC", > > + "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.", > > + "EventCode": "0x123", > > + "EventName": "PRE_INDEX_SPEC", > > + "BriefDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode.", > > + "EventCode": "0x124", > > + "EventName": "POST_INDEX_SPEC", > > + "BriefDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > > new file mode 100644 > > index 000000000000..c1f6479e92b4 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > > @@ -0,0 +1,8 @@ > > +[ > > + { > > + "PublicDescription": "This event counts energy consumption per cycle of CMG local memory.", > > + "EventCode": "0x3E8", > > + "EventName": "EA_MEMORY", > > + "BriefDescription": "This event counts energy consumption per cycle of CMG local memory." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > > new file mode 100644 > > index 000000000000..10c823ac26cc > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > > @@ -0,0 +1,188 @@ > > +[ > > + { > > + "PublicDescription": "This event counts the occurrence count of the micro-operation split.", > > + "EventCode": "0x139", > > + "EventName": "UOP_SPLIT", > > + "BriefDescription": "This event counts the occurrence count of the micro-operation split." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access.", > > + "EventCode": "0x180", > > + "EventName": "LD_COMP_WAIT_L2_MISS", > > + "BriefDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access.", > > + "EventCode": "0x181", > > + "EventName": "LD_COMP_WAIT_L2_MISS_EX", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.", > > + "EventCode": "0x182", > > + "EventName": "LD_COMP_WAIT_L1_MISS", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.", > > + "EventCode": "0x183", > > + "EventName": "LD_COMP_WAIT_L1_MISS_EX", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", > > + "EventCode": "0x184", > > + "EventName": "LD_COMP_WAIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", > > + "EventCode": "0x185", > > + "EventName": "LD_COMP_WAIT_EX", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.", > > + "EventCode": "0x186", > > + "EventName": "LD_COMP_WAIT_PFP_BUSY", > > + "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port." > > + }, > > + { > > + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.", > > + "EventCode": "0x187", > > + "EventName": "LD_COMP_WAIT_PFP_BUSY_EX", > > + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation." > > + }, > > + { > > + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.", > > + "EventCode": "0x188", > > + "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF", > > + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction.", > > + "EventCode": "0x189", > > + "EventName": "EU_COMP_WAIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.", > > + "EventCode": "0x18A", > > + "EventName": "FL_COMP_WAIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.", > > + "EventCode": "0x18B", > > + "EventName": "BR_COMP_WAIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty.", > > + "EventCode": "0x18C", > > + "EventName": "ROB_EMPTY", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.", > > + "EventCode": "0x18D", > > + "EventName": "ROB_EMPTY_STQ_BUSY", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.", > > + "EventCode": "0x18E", > > + "EventName": "WFE_WFI_CYCLE", > > + "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only.", > > + "EventCode": "0x190", > > + "EventName": "_0INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that one instruction is committed.", > > + "EventCode": "0x191", > > + "EventName": "_1INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that one instruction is committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that two instructions are committed.", > > + "EventCode": "0x192", > > + "EventName": "_2INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that two instructions are committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that three instructions are committed.", > > + "EventCode": "0x193", > > + "EventName": "_3INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that three instructions are committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that four instructions are committed.", > > + "EventCode": "0x194", > > + "EventName": "_4INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that four instructions are committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that only any micro-operations are committed.", > > + "EventCode": "0x198", > > + "EventName": "UOP_ONLY_COMMIT", > > + "BriefDescription": "This event counts every cycle that only any micro-operations are committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that only the MOVPRFX instruction is committed.", > > + "EventCode": "0x199", > > + "EventName": "SINGLE_MOVPRFX_COMMIT", > > + "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed." > > + }, > > + { > > + "PublicDescription": "This event counts energy consumption per cycle of core.", > > + "EventCode": "0x1E0", > > + "EventName": "EA_CORE", > > + "BriefDescription": "This event counts energy consumption per cycle of core." > > + }, > > + { > > + "PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.", > > + "EventCode": "0x230", > > + "EventName": "L1HWPF_STREAM_PF", > > + "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", > > + "EventCode": "0x231", > > + "EventName": "L1HWPF_INJ_ALLOC_PF", > > + "BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", > > + "EventCode": "0x232", > > + "EventName": "L1HWPF_INJ_NOALLOC_PF", > > + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.", > > + "EventCode": "0x233", > > + "EventName": "L2HWPF_STREAM_PF", > > + "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher." > > + }, > > + { > > + "PublicDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", > > + "EventCode": "0x234", > > + "EventName": "L2HWPF_INJ_ALLOC_PF", > > + "BriefDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", > > + "EventCode": "0x235", > > + "EventName": "L2HWPF_INJ_NOALLOC_PF", > > + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts prefetch requests to L2 cache generated by the other causes.", > > + "EventCode": "0x236", > > + "EventName": "L2HWPF_OTHER", > > + "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > > new file mode 100644 > > index 000000000000..dd7c97a9972b > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > > @@ -0,0 +1,194 @@ > > +[ > > + { > > + "ArchStdEvent": "STALL_FRONTEND" > > + }, > > + { > > + "ArchStdEvent": "STALL_BACKEND" > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of EAGA pipeline.", > > + "EventCode": "0x1A0", > > + "EventName": "EAGA_VAL", > > + "BriefDescription": "This event counts valid cycles of EAGA pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of EAGB pipeline.", > > + "EventCode": "0x1A1", > > + "EventName": "EAGB_VAL", > > + "BriefDescription": "This event counts valid cycles of EAGB pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of EXA pipeline.", > > + "EventCode": "0x1A2", > > + "EventName": "EXA_VAL", > > + "BriefDescription": "This event counts valid cycles of EXA pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of EXB pipeline.", > > + "EventCode": "0x1A3", > > + "EventName": "EXB_VAL", > > + "BriefDescription": "This event counts valid cycles of EXB pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of FLA pipeline.", > > + "EventCode": "0x1A4", > > + "EventName": "FLA_VAL", > > + "BriefDescription": "This event counts valid cycles of FLA pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of FLB pipeline.", > > + "EventCode": "0x1A5", > > + "EventName": "FLB_VAL", > > + "BriefDescription": "This event counts valid cycles of FLB pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of PRX pipeline.", > > + "EventCode": "0x1A6", > > + "EventName": "PRX_VAL", > > + "BriefDescription": "This event counts valid cycles of PRX pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1.", > > + "EventCode": "0x1B4", > > + "EventName": "FLA_VAL_PRD_CNT", > > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1." > > + }, > > + { > > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1.", > > + "EventCode": "0x1B5", > > + "EventName": "FLB_VAL_PRD_CNT", > > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#0.", > > + "EventCode": "0x240", > > + "EventName": "L1_PIPE0_VAL", > > + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#1.", > > + "EventCode": "0x241", > > + "EventName": "L1_PIPE1_VAL", > > + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.", > > + "EventCode": "0x250", > > + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1.", > > + "EventCode": "0x251", > > + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_PFE", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.", > > + "EventCode": "0x252", > > + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1.", > > + "EventCode": "0x253", > > + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_PFE", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1." > > + }, > > + { > > + "PublicDescription": "This event counts completed requests in L1D cache pipeline#0.", > > + "EventCode": "0x260", > > + "EventName": "L1_PIPE0_COMP", > > + "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." > > + }, > > + { > > + "PublicDescription": "This event counts completed requests in L1D cache pipeline#1.", > > + "EventCode": "0x261", > > + "EventName": "L1_PIPE1_COMP", > > + "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." > > + }, > > + { > > + "PublicDescription": "This event counts completed requests in L1I cache pipeline.", > > + "EventCode": "0x268", > > + "EventName": "L1I_PIPE_COMP", > > + "BriefDescription": "This event counts completed requests in L1I cache pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of L1I cache pipeline.", > > + "EventCode": "0x269", > > + "EventName": "L1I_PIPE_VAL", > > + "BriefDescription": "This event counts valid cycles of L1I cache pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock.", > > + "EventCode": "0x274", > > + "EventName": "L1_PIPE_ABORT_STLD_INTLK", > > + "BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0.", > > + "EventCode": "0x2A0", > > + "EventName": "L1_PIPE0_VAL_IU_NOT_SEC0", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0.", > > + "EventCode": "0x2A1", > > + "EventName": "L1_PIPE1_VAL_IU_NOT_SEC0", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0." > > + }, > > + { > > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", > > + "EventCode": "0x2B0", > > + "EventName": "L1_PIPE_COMP_GATHER_2FLOW", > > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined." > > + }, > > + { > > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", > > + "EventCode": "0x2B1", > > + "EventName": "L1_PIPE_COMP_GATHER_1FLOW", > > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined." > > + }, > > + { > > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", > > + "EventCode": "0x2B2", > > + "EventName": "L1_PIPE_COMP_GATHER_0FLOW", > > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0." > > + }, > > + { > > + "PublicDescription": "This event counts the number of flows of the scatter instructions.", > > + "EventCode": "0x2B3", > > + "EventName": "L1_PIPE_COMP_SCATTER_1FLOW", > > + "BriefDescription": "This event counts the number of flows of the scatter instructions." > > + }, > > + { > > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1.", > > + "EventCode": "0x2B8", > > + "EventName": "L1_PIPE0_COMP_PRD_CNT", > > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1." > > + }, > > + { > > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1.", > > + "EventCode": "0x2B9", > > + "EventName": "L1_PIPE1_COMP_PRD_CNT", > > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of L2 cache pipeline.", > > + "EventCode": "0x330", > > + "EventName": "L2_PIPE_VAL", > > + "BriefDescription": "This event counts valid cycles of L2 cache pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts completed requests in L2 cache pipeline.", > > + "EventCode": "0x350", > > + "EventName": "L2_PIPE_COMP_ALL", > > + "BriefDescription": "This event counts completed requests in L2 cache pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", > > + "EventCode": "0x370", > > + "EventName": "L2_PIPE_COMP_PF_L2MIB_MCH", > > + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > > new file mode 100644 > > index 000000000000..dc1b95e42c32 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > > @@ -0,0 +1,110 @@ > > +[ > > + { > > + "ArchStdEvent": "SIMD_INST_RETIRED" > > + }, > > + { > > + "ArchStdEvent": "SVE_INST_RETIRED" > > + }, > > + { > > + "ArchStdEvent": "UOP_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_MATH_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_FMA_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_RECPE_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_CVT_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_INT_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_PRED_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_MOVPRFX_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_MOVPRFX_U_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_LD_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_ST_SPEC" > > + }, > > + { > > + "ArchStdEvent": "PRF_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BASE_LD_REG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BASE_ST_REG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_LDR_REG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_STR_REG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_LDR_PREG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_STR_PREG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_PRF_CONTIG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_LD_GATHER_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_ST_SCATTER_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_PRF_GATHER_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_LDFF_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_SCALE_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_FIXED_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > > index 0d609149b82a..c43591d831b8 100644 > > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv > > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > > @@ -20,5 +20,6 @@ > > 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core > > 0x00000000420f5160,v1,cavium/thunderx2,core > > 0x00000000430f0af0,v1,cavium/thunderx2,core > > +0x00000000460f0010,v1,fujitsu/a64fx,core > > 0x00000000480fd010,v1,hisilicon/hip08,core > > 0x00000000500f0000,v1,ampere/emag,core > > -- > > 2.25.1 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > > > -- - Arnaldo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/2] perf vendor events arm64: Add Fujitsu A64FX pmu event @ 2021-03-15 13:49 ` Arnaldo Carvalho de Melo 0 siblings, 0 replies; 10+ messages in thread From: Arnaldo Carvalho de Melo @ 2021-03-15 13:49 UTC (permalink / raw) To: Masayoshi Mizuma Cc: Shunsuke Nakamura, john.garry, will, mathieu.poirier, leo.yan, peterz, mingo, mark.rutland, alexander.shishkin, jolsa, namhyung, linux-arm-kernel, linux-kernel Em Tue, Mar 09, 2021 at 11:59:18AM -0500, Masayoshi Mizuma escreveu: > On Mon, Mar 08, 2021 at 07:53:41PM +0900, Shunsuke Nakamura wrote: > > Add pmu events for A64FX. > > > > Documentation source: > > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf > > The PMU events described in above document seems to work well > with this patch! > Please feel free to add: > > Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com> Thanks, applied. - Arnaldo > Thanks! > Masa > > > > > Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com> > > Reviewed-by: John Garry <john.garry@huawei.com> > > --- > > .../arch/arm64/fujitsu/a64fx/branch.json | 8 + > > .../arch/arm64/fujitsu/a64fx/bus.json | 62 ++++++ > > .../arch/arm64/fujitsu/a64fx/cache.json | 128 ++++++++++++ > > .../arch/arm64/fujitsu/a64fx/cycle.json | 5 + > > .../arch/arm64/fujitsu/a64fx/exception.json | 29 +++ > > .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++++++++++ > > .../arch/arm64/fujitsu/a64fx/memory.json | 8 + > > .../arch/arm64/fujitsu/a64fx/other.json | 188 +++++++++++++++++ > > .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 ++++++++++++++++++ > > .../arch/arm64/fujitsu/a64fx/sve.json | 110 ++++++++++ > > tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + > > 11 files changed, 864 insertions(+) > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > > > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > > new file mode 100644 > > index 000000000000..b011af11bf94 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/branch.json > > @@ -0,0 +1,8 @@ > > +[ > > + { > > + "ArchStdEvent": "BR_MIS_PRED" > > + }, > > + { > > + "ArchStdEvent": "BR_PRED" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > > new file mode 100644 > > index 000000000000..084e88d7df73 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/bus.json > > @@ -0,0 +1,62 @@ > > +[ > > + { > > + "PublicDescription": "This event counts read transactions from tofu controller to measured CMG.", > > + "EventCode": "0x314", > > + "EventName": "BUS_READ_TOTAL_TOFU", > > + "BriefDescription": "This event counts read transactions from tofu controller to measured CMG." > > + }, > > + { > > + "PublicDescription": "This event counts read transactions from PCI controller to measured CMG.", > > + "EventCode": "0x315", > > + "EventName": "BUS_READ_TOTAL_PCI", > > + "BriefDescription": "This event counts read transactions from PCI controller to measured CMG." > > + }, > > + { > > + "PublicDescription": "This event counts read transactions from measured CMG local memory to measured CMG.", > > + "EventCode": "0x316", > > + "EventName": "BUS_READ_TOTAL_MEM", > > + "BriefDescription": "This event counts read transactions from measured CMG local memory to measured CMG." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0.", > > + "EventCode": "0x318", > > + "EventName": "BUS_WRITE_TOTAL_CMG0", > > + "BriefDescription": "This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1.", > > + "EventCode": "0x319", > > + "EventName": "BUS_WRITE_TOTAL_CMG1", > > + "BriefDescription": "This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2.", > > + "EventCode": "0x31A", > > + "EventName": "BUS_WRITE_TOTAL_CMG2", > > + "BriefDescription": "This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3.", > > + "EventCode": "0x31B", > > + "EventName": "BUS_WRITE_TOTAL_CMG3", > > + "BriefDescription": "This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to tofu controller.", > > + "EventCode": "0x31C", > > + "EventName": "BUS_WRITE_TOTAL_TOFU", > > + "BriefDescription": "This event counts write transactions from measured CMG to tofu controller." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to PCI controller.", > > + "EventCode": "0x31D", > > + "EventName": "BUS_WRITE_TOTAL_PCI", > > + "BriefDescription": "This event counts write transactions from measured CMG to PCI controller." > > + }, > > + { > > + "PublicDescription": "This event counts write transactions from measured CMG to measured CMG local memory.", > > + "EventCode": "0x31E", > > + "EventName": "BUS_WRITE_TOTAL_MEM", > > + "BriefDescription": "This event counts write transactions from measured CMG to measured CMG local memory." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > > new file mode 100644 > > index 000000000000..2e341a951a10 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cache.json > > @@ -0,0 +1,128 @@ > > +[ > > + { > > + "ArchStdEvent": "L1I_CACHE_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L1I_TLB_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L1D_CACHE_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L1D_CACHE" > > + }, > > + { > > + "ArchStdEvent": "L1D_TLB_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L1I_CACHE" > > + }, > > + { > > + "ArchStdEvent": "L1D_CACHE_WB" > > + }, > > + { > > + "ArchStdEvent": "L2D_CACHE" > > + }, > > + { > > + "ArchStdEvent": "L2D_CACHE_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L2D_CACHE_WB" > > + }, > > + { > > + "ArchStdEvent": "L2D_TLB_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L2I_TLB_REFILL" > > + }, > > + { > > + "ArchStdEvent": "L2D_TLB" > > + }, > > + { > > + "ArchStdEvent": "L2I_TLB" > > + }, > > + { > > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", > > + "EventCode": "0x49", > > + "EventName": "L1D_CACHE_REFILL_PRF", > > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", > > + "EventCode": "0x59", > > + "EventName": "L2D_CACHE_REFILL_PRF", > > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.", > > + "EventCode": "0x200", > > + "EventName": "L1D_CACHE_REFILL_DM", > > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." > > + }, > > + { > > + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", > > + "EventCode": "0x202", > > + "EventName": "L1D_CACHE_REFILL_HWPRF", > > + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", > > + "EventCode": "0x208", > > + "EventName": "L1_MISS_WAIT", > > + "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." > > + }, > > + { > > + "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.", > > + "EventCode": "0x209", > > + "EventName": "L1I_MISS_WAIT", > > + "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle." > > + }, > > + { > > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by demand access.", > > + "EventCode": "0x300", > > + "EventName": "L2D_CACHE_REFILL_DM", > > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access." > > + }, > > + { > > + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch.", > > + "EventCode": "0x302", > > + "EventName": "L2D_CACHE_REFILL_HWPRF", > > + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.", > > + "EventCode": "0x308", > > + "EventName": "L2_MISS_WAIT", > > + "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle." > > + }, > > + { > > + "PublicDescription": "This event counts the number of times of L2 cache miss.", > > + "EventCode": "0x309", > > + "EventName": "L2_MISS_COUNT", > > + "BriefDescription": "This event counts the number of times of L2 cache miss." > > + }, > > + { > > + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", > > + "EventCode": "0x325", > > + "EventName": "L2D_SWAP_DM", > > + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", > > + "EventCode": "0x326", > > + "EventName": "L2D_CACHE_MIBMCH_PRF", > > + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." > > + }, > > + { > > + "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.", > > + "EventCode": "0x396", > > + "EventName": "L2D_CACHE_SWAP_LOCAL", > > + "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch." > > + }, > > + { > > + "PublicDescription": "This event counts energy consumption per cycle of L2 cache.", > > + "EventCode": "0x3E0", > > + "EventName": "EA_L2", > > + "BriefDescription": "This event counts energy consumption per cycle of L2 cache." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > > new file mode 100644 > > index 000000000000..b16484628290 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/cycle.json > > @@ -0,0 +1,5 @@ > > +[ > > + { > > + "ArchStdEvent": "CPU_CYCLES" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > > new file mode 100644 > > index 000000000000..348749c154c0 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/exception.json > > @@ -0,0 +1,29 @@ > > +[ > > + { > > + "ArchStdEvent": "EXC_TAKEN" > > + }, > > + { > > + "ArchStdEvent": "EXC_UNDEF" > > + }, > > + { > > + "ArchStdEvent": "EXC_SVC" > > + }, > > + { > > + "ArchStdEvent": "EXC_PABORT" > > + }, > > + { > > + "ArchStdEvent": "EXC_DABORT" > > + }, > > + { > > + "ArchStdEvent": "EXC_IRQ" > > + }, > > + { > > + "ArchStdEvent": "EXC_FIQ" > > + }, > > + { > > + "ArchStdEvent": "EXC_SMC" > > + }, > > + { > > + "ArchStdEvent": "EXC_HVC" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > > new file mode 100644 > > index 000000000000..6d258b1080cf > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json > > @@ -0,0 +1,131 @@ > > +[ > > + { > > + "ArchStdEvent": "SW_INCR" > > + }, > > + { > > + "ArchStdEvent": "INST_RETIRED" > > + }, > > + { > > + "ArchStdEvent": "EXC_RETURN" > > + }, > > + { > > + "ArchStdEvent": "CID_WRITE_RETIRED" > > + }, > > + { > > + "ArchStdEvent": "INST_SPEC" > > + }, > > + { > > + "ArchStdEvent": "LDREX_SPEC" > > + }, > > + { > > + "ArchStdEvent": "STREX_SPEC" > > + }, > > + { > > + "ArchStdEvent": "LD_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ST_SPEC" > > + }, > > + { > > + "ArchStdEvent": "LDST_SPEC" > > + }, > > + { > > + "ArchStdEvent": "DP_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SPEC" > > + }, > > + { > > + "ArchStdEvent": "VFP_SPEC" > > + }, > > + { > > + "ArchStdEvent": "PC_WRITE_SPEC" > > + }, > > + { > > + "ArchStdEvent": "CRYPTO_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BR_IMMED_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BR_RETURN_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BR_INDIRECT_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ISB_SPEC" > > + }, > > + { > > + "ArchStdEvent": "DSB_SPEC" > > + }, > > + { > > + "ArchStdEvent": "DMB_SPEC" > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", > > + "EventCode": "0x9F", > > + "EventName": "DCZVA_SPEC", > > + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed floating-point move operations.", > > + "EventCode": "0x105", > > + "EventName": "FP_MV_SPEC", > > + "BriefDescription": "This event counts architecturally executed floating-point move operations." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed operations that using predicate register.", > > + "EventCode": "0x108", > > + "EventName": "PRD_SPEC", > > + "BriefDescription": "This event counts architecturally executed operations that using predicate register." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed inter-element manipulation operations.", > > + "EventCode": "0x109", > > + "EventName": "IEL_SPEC", > > + "BriefDescription": "This event counts architecturally executed inter-element manipulation operations." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed inter-register manipulation operations.", > > + "EventCode": "0x10A", > > + "EventName": "IREG_SPEC", > > + "BriefDescription": "This event counts architecturally executed inter-register manipulation operations." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.", > > + "EventCode": "0x112", > > + "EventName": "FP_LD_SPEC", > > + "BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.", > > + "EventCode": "0x113", > > + "EventName": "FP_ST_SPEC", > > + "BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations.", > > + "EventCode": "0x11A", > > + "EventName": "BC_LD_SPEC", > > + "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.", > > + "EventCode": "0x121", > > + "EventName": "EFFECTIVE_INST_SPEC", > > + "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.", > > + "EventCode": "0x123", > > + "EventName": "PRE_INDEX_SPEC", > > + "BriefDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode." > > + }, > > + { > > + "PublicDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode.", > > + "EventCode": "0x124", > > + "EventName": "POST_INDEX_SPEC", > > + "BriefDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > > new file mode 100644 > > index 000000000000..c1f6479e92b4 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/memory.json > > @@ -0,0 +1,8 @@ > > +[ > > + { > > + "PublicDescription": "This event counts energy consumption per cycle of CMG local memory.", > > + "EventCode": "0x3E8", > > + "EventName": "EA_MEMORY", > > + "BriefDescription": "This event counts energy consumption per cycle of CMG local memory." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > > new file mode 100644 > > index 000000000000..10c823ac26cc > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/other.json > > @@ -0,0 +1,188 @@ > > +[ > > + { > > + "PublicDescription": "This event counts the occurrence count of the micro-operation split.", > > + "EventCode": "0x139", > > + "EventName": "UOP_SPLIT", > > + "BriefDescription": "This event counts the occurrence count of the micro-operation split." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access.", > > + "EventCode": "0x180", > > + "EventName": "LD_COMP_WAIT_L2_MISS", > > + "BriefDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access.", > > + "EventCode": "0x181", > > + "EventName": "LD_COMP_WAIT_L2_MISS_EX", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.", > > + "EventCode": "0x182", > > + "EventName": "LD_COMP_WAIT_L1_MISS", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.", > > + "EventCode": "0x183", > > + "EventName": "LD_COMP_WAIT_L1_MISS_EX", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", > > + "EventCode": "0x184", > > + "EventName": "LD_COMP_WAIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", > > + "EventCode": "0x185", > > + "EventName": "LD_COMP_WAIT_EX", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.", > > + "EventCode": "0x186", > > + "EventName": "LD_COMP_WAIT_PFP_BUSY", > > + "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port." > > + }, > > + { > > + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.", > > + "EventCode": "0x187", > > + "EventName": "LD_COMP_WAIT_PFP_BUSY_EX", > > + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation." > > + }, > > + { > > + "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.", > > + "EventCode": "0x188", > > + "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF", > > + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction.", > > + "EventCode": "0x189", > > + "EventName": "EU_COMP_WAIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.", > > + "EventCode": "0x18A", > > + "EventName": "FL_COMP_WAIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.", > > + "EventCode": "0x18B", > > + "EventName": "BR_COMP_WAIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty.", > > + "EventCode": "0x18C", > > + "EventName": "ROB_EMPTY", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.", > > + "EventCode": "0x18D", > > + "EventName": "ROB_EMPTY_STQ_BUSY", > > + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.", > > + "EventCode": "0x18E", > > + "EventName": "WFE_WFI_CYCLE", > > + "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only.", > > + "EventCode": "0x190", > > + "EventName": "_0INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that one instruction is committed.", > > + "EventCode": "0x191", > > + "EventName": "_1INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that one instruction is committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that two instructions are committed.", > > + "EventCode": "0x192", > > + "EventName": "_2INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that two instructions are committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that three instructions are committed.", > > + "EventCode": "0x193", > > + "EventName": "_3INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that three instructions are committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that four instructions are committed.", > > + "EventCode": "0x194", > > + "EventName": "_4INST_COMMIT", > > + "BriefDescription": "This event counts every cycle that four instructions are committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that only any micro-operations are committed.", > > + "EventCode": "0x198", > > + "EventName": "UOP_ONLY_COMMIT", > > + "BriefDescription": "This event counts every cycle that only any micro-operations are committed." > > + }, > > + { > > + "PublicDescription": "This event counts every cycle that only the MOVPRFX instruction is committed.", > > + "EventCode": "0x199", > > + "EventName": "SINGLE_MOVPRFX_COMMIT", > > + "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed." > > + }, > > + { > > + "PublicDescription": "This event counts energy consumption per cycle of core.", > > + "EventCode": "0x1E0", > > + "EventName": "EA_CORE", > > + "BriefDescription": "This event counts energy consumption per cycle of core." > > + }, > > + { > > + "PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.", > > + "EventCode": "0x230", > > + "EventName": "L1HWPF_STREAM_PF", > > + "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", > > + "EventCode": "0x231", > > + "EventName": "L1HWPF_INJ_ALLOC_PF", > > + "BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.", > > + "EventCode": "0x232", > > + "EventName": "L1HWPF_INJ_NOALLOC_PF", > > + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.", > > + "EventCode": "0x233", > > + "EventName": "L2HWPF_STREAM_PF", > > + "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher." > > + }, > > + { > > + "PublicDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", > > + "EventCode": "0x234", > > + "EventName": "L2HWPF_INJ_ALLOC_PF", > > + "BriefDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.", > > + "EventCode": "0x235", > > + "EventName": "L2HWPF_INJ_NOALLOC_PF", > > + "BriefDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher." > > + }, > > + { > > + "PublicDescription": "This event counts prefetch requests to L2 cache generated by the other causes.", > > + "EventCode": "0x236", > > + "EventName": "L2HWPF_OTHER", > > + "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > > new file mode 100644 > > index 000000000000..dd7c97a9972b > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/pipeline.json > > @@ -0,0 +1,194 @@ > > +[ > > + { > > + "ArchStdEvent": "STALL_FRONTEND" > > + }, > > + { > > + "ArchStdEvent": "STALL_BACKEND" > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of EAGA pipeline.", > > + "EventCode": "0x1A0", > > + "EventName": "EAGA_VAL", > > + "BriefDescription": "This event counts valid cycles of EAGA pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of EAGB pipeline.", > > + "EventCode": "0x1A1", > > + "EventName": "EAGB_VAL", > > + "BriefDescription": "This event counts valid cycles of EAGB pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of EXA pipeline.", > > + "EventCode": "0x1A2", > > + "EventName": "EXA_VAL", > > + "BriefDescription": "This event counts valid cycles of EXA pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of EXB pipeline.", > > + "EventCode": "0x1A3", > > + "EventName": "EXB_VAL", > > + "BriefDescription": "This event counts valid cycles of EXB pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of FLA pipeline.", > > + "EventCode": "0x1A4", > > + "EventName": "FLA_VAL", > > + "BriefDescription": "This event counts valid cycles of FLA pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of FLB pipeline.", > > + "EventCode": "0x1A5", > > + "EventName": "FLB_VAL", > > + "BriefDescription": "This event counts valid cycles of FLB pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of PRX pipeline.", > > + "EventCode": "0x1A6", > > + "EventName": "PRX_VAL", > > + "BriefDescription": "This event counts valid cycles of PRX pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1.", > > + "EventCode": "0x1B4", > > + "EventName": "FLA_VAL_PRD_CNT", > > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1." > > + }, > > + { > > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1.", > > + "EventCode": "0x1B5", > > + "EventName": "FLB_VAL_PRD_CNT", > > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#0.", > > + "EventCode": "0x240", > > + "EventName": "L1_PIPE0_VAL", > > + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of L1D cache pipeline#1.", > > + "EventCode": "0x241", > > + "EventName": "L1_PIPE1_VAL", > > + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.", > > + "EventCode": "0x250", > > + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1.", > > + "EventCode": "0x251", > > + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_PFE", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.", > > + "EventCode": "0x252", > > + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1.", > > + "EventCode": "0x253", > > + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_PFE", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1." > > + }, > > + { > > + "PublicDescription": "This event counts completed requests in L1D cache pipeline#0.", > > + "EventCode": "0x260", > > + "EventName": "L1_PIPE0_COMP", > > + "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." > > + }, > > + { > > + "PublicDescription": "This event counts completed requests in L1D cache pipeline#1.", > > + "EventCode": "0x261", > > + "EventName": "L1_PIPE1_COMP", > > + "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." > > + }, > > + { > > + "PublicDescription": "This event counts completed requests in L1I cache pipeline.", > > + "EventCode": "0x268", > > + "EventName": "L1I_PIPE_COMP", > > + "BriefDescription": "This event counts completed requests in L1I cache pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of L1I cache pipeline.", > > + "EventCode": "0x269", > > + "EventName": "L1I_PIPE_VAL", > > + "BriefDescription": "This event counts valid cycles of L1I cache pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock.", > > + "EventCode": "0x274", > > + "EventName": "L1_PIPE_ABORT_STLD_INTLK", > > + "BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0.", > > + "EventCode": "0x2A0", > > + "EventName": "L1_PIPE0_VAL_IU_NOT_SEC0", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0." > > + }, > > + { > > + "PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0.", > > + "EventCode": "0x2A1", > > + "EventName": "L1_PIPE1_VAL_IU_NOT_SEC0", > > + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0." > > + }, > > + { > > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", > > + "EventCode": "0x2B0", > > + "EventName": "L1_PIPE_COMP_GATHER_2FLOW", > > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined." > > + }, > > + { > > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", > > + "EventCode": "0x2B1", > > + "EventName": "L1_PIPE_COMP_GATHER_1FLOW", > > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined." > > + }, > > + { > > + "PublicDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", > > + "EventCode": "0x2B2", > > + "EventName": "L1_PIPE_COMP_GATHER_0FLOW", > > + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0." > > + }, > > + { > > + "PublicDescription": "This event counts the number of flows of the scatter instructions.", > > + "EventCode": "0x2B3", > > + "EventName": "L1_PIPE_COMP_SCATTER_1FLOW", > > + "BriefDescription": "This event counts the number of flows of the scatter instructions." > > + }, > > + { > > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1.", > > + "EventCode": "0x2B8", > > + "EventName": "L1_PIPE0_COMP_PRD_CNT", > > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1." > > + }, > > + { > > + "PublicDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1.", > > + "EventCode": "0x2B9", > > + "EventName": "L1_PIPE1_COMP_PRD_CNT", > > + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1." > > + }, > > + { > > + "PublicDescription": "This event counts valid cycles of L2 cache pipeline.", > > + "EventCode": "0x330", > > + "EventName": "L2_PIPE_VAL", > > + "BriefDescription": "This event counts valid cycles of L2 cache pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts completed requests in L2 cache pipeline.", > > + "EventCode": "0x350", > > + "EventName": "L2_PIPE_COMP_ALL", > > + "BriefDescription": "This event counts completed requests in L2 cache pipeline." > > + }, > > + { > > + "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", > > + "EventCode": "0x370", > > + "EventName": "L2_PIPE_COMP_PF_L2MIB_MCH", > > + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > > new file mode 100644 > > index 000000000000..dc1b95e42c32 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/sve.json > > @@ -0,0 +1,110 @@ > > +[ > > + { > > + "ArchStdEvent": "SIMD_INST_RETIRED" > > + }, > > + { > > + "ArchStdEvent": "SVE_INST_RETIRED" > > + }, > > + { > > + "ArchStdEvent": "UOP_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_MATH_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_FMA_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_RECPE_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_CVT_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_INT_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_PRED_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_MOVPRFX_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_MOVPRFX_U_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_LD_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_ST_SPEC" > > + }, > > + { > > + "ArchStdEvent": "PRF_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BASE_LD_REG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "BASE_ST_REG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_LDR_REG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_STR_REG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_LDR_PREG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_STR_PREG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_PRF_CONTIG_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC" > > + }, > > + { > > + "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_LD_GATHER_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_ST_SCATTER_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_PRF_GATHER_SPEC" > > + }, > > + { > > + "ArchStdEvent": "SVE_LDFF_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_SCALE_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_FIXED_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC" > > + }, > > + { > > + "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > > index 0d609149b82a..c43591d831b8 100644 > > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv > > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > > @@ -20,5 +20,6 @@ > > 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core > > 0x00000000420f5160,v1,cavium/thunderx2,core > > 0x00000000430f0af0,v1,cavium/thunderx2,core > > +0x00000000460f0010,v1,fujitsu/a64fx,core > > 0x00000000480fd010,v1,hisilicon/hip08,core > > 0x00000000500f0000,v1,ampere/emag,core > > -- > > 2.25.1 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > > > -- - Arnaldo ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-03-15 13:51 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-03-08 10:53 [PATCH v9 0/2] perf vendor events: Support PMU events for A64FX Shunsuke Nakamura 2021-03-08 10:53 ` Shunsuke Nakamura 2021-03-08 10:53 ` [PATCH v9 1/2] perf vendor events arm64: Add more common and uarch events Shunsuke Nakamura 2021-03-08 10:53 ` Shunsuke Nakamura 2021-03-08 10:53 ` [PATCH v9 2/2] perf vendor events arm64: Add Fujitsu A64FX pmu event Shunsuke Nakamura 2021-03-08 10:53 ` Shunsuke Nakamura 2021-03-09 16:59 ` Masayoshi Mizuma 2021-03-09 16:59 ` Masayoshi Mizuma 2021-03-15 13:49 ` Arnaldo Carvalho de Melo 2021-03-15 13:49 ` Arnaldo Carvalho de Melo
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.