From: Joerg Roedel <joro@8bytes.org>
To: Kyung Min Park <kyung.min.park@intel.com>
Cc: ravi.v.shankar@intel.com, ashok.raj@intel.com,
dwmw2@infradead.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org, will@kernel.org
Subject: Re: [PATCH] iommu/vt-d: Disable SVM when ATS/PRI/PASID are not enabled in the device
Date: Thu, 18 Mar 2021 11:24:19 +0100 [thread overview]
Message-ID: <YFMqU2Rp+9CYVX6s@8bytes.org> (raw)
In-Reply-To: <20210314201534.918-1-kyung.min.park@intel.com>
On Sun, Mar 14, 2021 at 01:15:34PM -0700, Kyung Min Park wrote:
> Currently, the Intel VT-d supports Shared Virtual Memory (SVM) only when
> IO page fault is supported. Otherwise, shared memory pages can not be
> swapped out and need to be pinned. The device needs the Address Translation
> Service (ATS), Page Request Interface (PRI) and Process Address Space
> Identifier (PASID) capabilities to be enabled to support IO page fault.
>
> Disable SVM when ATS, PRI and PASID are not enabled in the device.
>
> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
Applied, thanks.
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WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org>
To: Kyung Min Park <kyung.min.park@intel.com>
Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
baolu.lu@linux.intel.com, dwmw2@infradead.org, will@kernel.org,
jacob.jun.pan@linux.intel.com, ashok.raj@intel.com,
ravi.v.shankar@intel.com, yian.chen@intel.com,
sohil.mehta@intel.com
Subject: Re: [PATCH] iommu/vt-d: Disable SVM when ATS/PRI/PASID are not enabled in the device
Date: Thu, 18 Mar 2021 11:24:19 +0100 [thread overview]
Message-ID: <YFMqU2Rp+9CYVX6s@8bytes.org> (raw)
In-Reply-To: <20210314201534.918-1-kyung.min.park@intel.com>
On Sun, Mar 14, 2021 at 01:15:34PM -0700, Kyung Min Park wrote:
> Currently, the Intel VT-d supports Shared Virtual Memory (SVM) only when
> IO page fault is supported. Otherwise, shared memory pages can not be
> swapped out and need to be pinned. The device needs the Address Translation
> Service (ATS), Page Request Interface (PRI) and Process Address Space
> Identifier (PASID) capabilities to be enabled to support IO page fault.
>
> Disable SVM when ATS, PRI and PASID are not enabled in the device.
>
> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
Applied, thanks.
next prev parent reply other threads:[~2021-03-18 10:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-14 20:15 [PATCH] iommu/vt-d: Disable SVM when ATS/PRI/PASID are not enabled in the device Kyung Min Park
2021-03-14 20:15 ` Kyung Min Park
2021-03-15 0:30 ` Lu Baolu
2021-03-15 0:30 ` Lu Baolu
2021-03-18 10:24 ` Joerg Roedel [this message]
2021-03-18 10:24 ` Joerg Roedel
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