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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: Disable LTTPR support when the LTTPR rev < 1.4
Date: Thu, 18 Mar 2021 20:00:10 +0200	[thread overview]
Message-ID: <YFOVKoReLkmB7ZuQ@intel.com> (raw)
In-Reply-To: <20210317184901.4029798-4-imre.deak@intel.com>

On Wed, Mar 17, 2021 at 08:49:01PM +0200, Imre Deak wrote:
> By the specification the 0xF0000 - 0xF02FF range is only valid if the
> LTTPR revision at 0xF0000 is at least 1.4. Disable the LTTPR support
> otherwise.
> 
> Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training")
> Cc: <stable@vger.kernel.org> # v5.11
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c  | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index d8d90903226f..d92eb192c89d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -100,17 +100,23 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
>  		return false;
>  
>  	if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
> -					  intel_dp->lttpr_common_caps) < 0) {
> -		intel_dp_reset_lttpr_common_caps(intel_dp);
> -		return false;
> -	}
> +					  intel_dp->lttpr_common_caps) < 0)
> +		goto reset_caps;

BTW just noticed this oddball thing in the spec:
"DPTX shall read specific registers within the LTTPR field (DPCD
 Addresses F0000h through F0004h; see Table 2-198) to determine
 whether any LTTPR(s) are present and if so, how many. This read
 shall be in the form of a 5-byte native AUX Read transaction."

Why exactly 5 bytes? I have no idea. Doesn't really make sense.
Just wondering if we really need to respect that and some LTTPRs
would fsck things up if we read more...

Anyways
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
>  		    "LTTPR common capabilities: %*ph\n",
>  		    (int)sizeof(intel_dp->lttpr_common_caps),
>  		    intel_dp->lttpr_common_caps);
>  
> +	/* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
> +	if (intel_dp->lttpr_common_caps[0] < 0x14)
> +		goto reset_caps;
> +
>  	return true;
> +
> +reset_caps:
> +	intel_dp_reset_lttpr_common_caps(intel_dp);
> +	return false;
>  }
>  
>  static bool
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [PATCH v2 3/3] drm/i915: Disable LTTPR support when the LTTPR rev < 1.4
Date: Thu, 18 Mar 2021 20:00:10 +0200	[thread overview]
Message-ID: <YFOVKoReLkmB7ZuQ@intel.com> (raw)
In-Reply-To: <20210317184901.4029798-4-imre.deak@intel.com>

On Wed, Mar 17, 2021 at 08:49:01PM +0200, Imre Deak wrote:
> By the specification the 0xF0000 - 0xF02FF range is only valid if the
> LTTPR revision at 0xF0000 is at least 1.4. Disable the LTTPR support
> otherwise.
> 
> Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training")
> Cc: <stable@vger.kernel.org> # v5.11
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c  | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index d8d90903226f..d92eb192c89d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -100,17 +100,23 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
>  		return false;
>  
>  	if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
> -					  intel_dp->lttpr_common_caps) < 0) {
> -		intel_dp_reset_lttpr_common_caps(intel_dp);
> -		return false;
> -	}
> +					  intel_dp->lttpr_common_caps) < 0)
> +		goto reset_caps;

BTW just noticed this oddball thing in the spec:
"DPTX shall read specific registers within the LTTPR field (DPCD
 Addresses F0000h through F0004h; see Table 2-198) to determine
 whether any LTTPR(s) are present and if so, how many. This read
 shall be in the form of a 5-byte native AUX Read transaction."

Why exactly 5 bytes? I have no idea. Doesn't really make sense.
Just wondering if we really need to respect that and some LTTPRs
would fsck things up if we read more...

Anyways
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
>  		    "LTTPR common capabilities: %*ph\n",
>  		    (int)sizeof(intel_dp->lttpr_common_caps),
>  		    intel_dp->lttpr_common_caps);
>  
> +	/* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
> +	if (intel_dp->lttpr_common_caps[0] < 0x14)
> +		goto reset_caps;
> +
>  	return true;
> +
> +reset_caps:
> +	intel_dp_reset_lttpr_common_caps(intel_dp);
> +	return false;
>  }
>  
>  static bool
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2021-03-18 18:00 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-17 18:48 [Intel-gfx] [PATCH v2 0/3] drm/i915: Fix DP LTTPR link training mode initialization Imre Deak
2021-03-17 18:48 ` Imre Deak
2021-03-17 18:48 ` [Intel-gfx] [PATCH v2 1/3] drm/i915/ilk-glk: Fix link training on links with LTTPRs Imre Deak
2021-03-17 18:48   ` Imre Deak
2021-03-18 17:33   ` [Intel-gfx] " Ville Syrjälä
2021-03-18 17:33     ` Ville Syrjälä
2021-03-18 17:49     ` [Intel-gfx] " Imre Deak
2021-03-18 17:49       ` Imre Deak
2021-03-18 18:06       ` [Intel-gfx] " Imre Deak
2021-03-18 18:06         ` Imre Deak
2021-03-18 22:04         ` [Intel-gfx] " Almahallawy, Khaled
2021-03-18 22:04           ` Almahallawy, Khaled
2021-03-18 23:17           ` [Intel-gfx] " Imre Deak
2021-03-18 23:17             ` Imre Deak
2021-03-19 17:25             ` [Intel-gfx] " Lyude Paul
2021-03-19 17:25               ` Lyude Paul
2021-03-19 17:29               ` [Intel-gfx] " Imre Deak
2021-03-19 17:29                 ` Imre Deak
2021-03-19 20:44                 ` [Intel-gfx] " Lyude Paul
2021-03-19 20:44                   ` Lyude Paul
2021-03-19 21:07                   ` [Intel-gfx] " Imre Deak
2021-03-19 21:07                     ` Imre Deak
2021-03-20  7:15                     ` [Intel-gfx] " Imre Deak
2021-03-20  7:15                       ` Imre Deak
2021-03-20  7:40                       ` [Intel-gfx] " Almahallawy, Khaled
2021-03-20  7:40                         ` Almahallawy, Khaled
2021-03-20  7:45                         ` [Intel-gfx] " Imre Deak
2021-03-20  7:45                           ` Imre Deak
2021-03-17 18:49 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Disable LTTPR support when the DPCD rev < 1.4 Imre Deak
2021-03-17 18:49   ` Imre Deak
2021-03-17 19:01   ` [Intel-gfx] " Imre Deak
2021-03-17 19:01     ` Imre Deak
2021-03-18 17:57     ` [Intel-gfx] " Ville Syrjälä
2021-03-18 17:57       ` Ville Syrjälä
2021-03-18 18:05       ` [Intel-gfx] " Imre Deak
2021-03-18 18:05         ` Imre Deak
2021-03-17 18:49 ` [Intel-gfx] [PATCH v2 3/3] drm/i915: Disable LTTPR support when the LTTPR " Imre Deak
2021-03-17 18:49   ` Imre Deak
2021-03-18 18:00   ` Ville Syrjälä [this message]
2021-03-18 18:00     ` Ville Syrjälä
2021-03-18 18:09     ` [Intel-gfx] " Imre Deak
2021-03-18 18:09       ` Imre Deak
2021-03-17 20:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix DP LTTPR link training mode initialization (rev2) Patchwork
2021-03-17 21:01 ` [Intel-gfx] drm/i915: Fix DP LTTPR link training mode initialization Zephaniah E. Loss-Cutler-Hull
2021-03-17 22:34 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix DP LTTPR link training mode initialization (rev2) Patchwork
2021-03-19 11:16   ` Imre Deak
2021-03-19 11:16     ` Imre Deak
2021-03-22  8:34 ` [Intel-gfx] drm/i915: Fix DP LTTPR link training mode initialization Zephaniah E. Loss-Cutler-Hull

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