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From: Catalin Marinas <catalin.marinas@arm.com>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: "Chatre, Reinette" <reinette.chatre@intel.com>,
	"tan.shaopeng@fujitsu.com" <tan.shaopeng@fujitsu.com>,
	"Yu, Fenghua" <fenghua.yu@intel.com>,
	"'linux-kernel@vger.kernel.org'" <linux-kernel@vger.kernel.org>,
	"'linux-arm-kernel@lists.infradead.org'"
	<linux-arm-kernel@lists.infradead.org>,
	 'James Morse' <james.morse@arm.com>,
	"misono.tomohiro@fujitsu.com" <misono.tomohiro@fujitsu.com>
Subject: Re: About add an A64FX cache control function into resctrl
Date: Fri, 30 Apr 2021 12:46:32 +0100	[thread overview]
Message-ID: <YIvuGLmcJcw2jLT7@arm.com> (raw)
In-Reply-To: <49cdd0b707194148915e2efe2ab5d707@intel.com>

On Thu, Apr 29, 2021 at 05:50:20PM +0000, Luck, Tony wrote:
> >>>> [Sector cache function]
> >>>> The sector cache function split cache into multiple sectors and
> >>>> control them separately. It is implemented on the L1D cache and
> >>>> L2 cache in the A64FX processor and can be controlled individually
> >>>> for L1D cache and L2 cache. A64FX has no L3 cache. Each L1D cache and
> >>>> L2 cache has 4 sectors. Which L1D sector is used is specified by the
> >>>> value of [57:56] bits of address, how many ways of sector are
> >>>> specified by the value of register (IMP_SCCR_L1_EL0).
> >>>> Which L2 sector is used is specified by the value of [56] bits of
> >>>> address, and how many ways of sector are specified by value of
> >>>> register (IMP_SCCR_ASSIGN_EL1, IMP_SCCR_SET0_L2_EL1,
> >>>> IMP_SCCR_SET1_L2_EL1).
> 
> Are A64FX binaries position independent?  I.e. could the OS reassign
> a running task to a different sector by remapping it to different virtual
> addresses during a context switch?

Arm64 supports a maximum of 52-bit of virtual or physical addresses. The
maximum the MMU would produce would be a 52-bit output address. I
presume bits 56, 57 of the address bus are used for some cache affinity
(sector selection) but they don't influence the memory addressing, nor
could the MMU set them.

-- 
Catalin

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WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: "Chatre, Reinette" <reinette.chatre@intel.com>,
	"tan.shaopeng@fujitsu.com" <tan.shaopeng@fujitsu.com>,
	"Yu, Fenghua" <fenghua.yu@intel.com>,
	"'linux-kernel@vger.kernel.org'" <linux-kernel@vger.kernel.org>,
	"'linux-arm-kernel@lists.infradead.org'" 
	<linux-arm-kernel@lists.infradead.org>,
	'James Morse' <james.morse@arm.com>,
	"misono.tomohiro@fujitsu.com" <misono.tomohiro@fujitsu.com>
Subject: Re: About add an A64FX cache control function into resctrl
Date: Fri, 30 Apr 2021 12:46:32 +0100	[thread overview]
Message-ID: <YIvuGLmcJcw2jLT7@arm.com> (raw)
In-Reply-To: <49cdd0b707194148915e2efe2ab5d707@intel.com>

On Thu, Apr 29, 2021 at 05:50:20PM +0000, Luck, Tony wrote:
> >>>> [Sector cache function]
> >>>> The sector cache function split cache into multiple sectors and
> >>>> control them separately. It is implemented on the L1D cache and
> >>>> L2 cache in the A64FX processor and can be controlled individually
> >>>> for L1D cache and L2 cache. A64FX has no L3 cache. Each L1D cache and
> >>>> L2 cache has 4 sectors. Which L1D sector is used is specified by the
> >>>> value of [57:56] bits of address, how many ways of sector are
> >>>> specified by the value of register (IMP_SCCR_L1_EL0).
> >>>> Which L2 sector is used is specified by the value of [56] bits of
> >>>> address, and how many ways of sector are specified by value of
> >>>> register (IMP_SCCR_ASSIGN_EL1, IMP_SCCR_SET0_L2_EL1,
> >>>> IMP_SCCR_SET1_L2_EL1).
> 
> Are A64FX binaries position independent?  I.e. could the OS reassign
> a running task to a different sector by remapping it to different virtual
> addresses during a context switch?

Arm64 supports a maximum of 52-bit of virtual or physical addresses. The
maximum the MMU would produce would be a 52-bit output address. I
presume bits 56, 57 of the address bus are used for some cache affinity
(sector selection) but they don't influence the memory addressing, nor
could the MMU set them.

-- 
Catalin

  reply	other threads:[~2021-04-30 11:48 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09  5:46 About add an A64FX cache control function into resctrl tan.shaopeng
2021-04-09  5:46 ` tan.shaopeng
2021-04-21  8:37 ` tan.shaopeng
2021-04-21  8:37   ` tan.shaopeng
2021-04-21 16:39   ` Reinette Chatre
2021-04-21 16:39     ` Reinette Chatre
2021-04-23  8:10     ` tan.shaopeng
2021-04-23  8:10       ` tan.shaopeng
2021-04-28  8:16     ` tan.shaopeng
2021-04-28  8:16       ` tan.shaopeng
2021-04-29 17:42       ` Reinette Chatre
2021-04-29 17:42         ` Reinette Chatre
2021-04-29 17:50         ` Luck, Tony
2021-04-29 17:50           ` Luck, Tony
2021-04-30 11:46           ` Catalin Marinas [this message]
2021-04-30 11:46             ` Catalin Marinas
2021-05-17  8:29             ` tan.shaopeng
2021-05-17  8:29               ` tan.shaopeng
2021-05-17  8:31         ` tan.shaopeng
2021-05-17  8:31           ` tan.shaopeng
2021-05-21 17:44           ` Reinette Chatre
2021-05-21 17:44             ` Reinette Chatre
2021-05-25  8:45             ` tan.shaopeng
2021-05-25  8:45               ` tan.shaopeng
2021-05-26 17:36               ` Reinette Chatre
2021-05-26 17:36                 ` Reinette Chatre
2021-05-27  8:45                 ` tan.shaopeng
2021-05-27  8:45                   ` tan.shaopeng
2021-07-07 11:26                 ` tan.shaopeng
2021-07-07 11:26                   ` tan.shaopeng
2021-07-16  0:49                   ` tan.shaopeng
2021-07-16  0:49                     ` tan.shaopeng
2021-07-19 23:25                   ` Reinette Chatre
2021-07-19 23:25                     ` Reinette Chatre
2021-07-21  8:10                     ` tan.shaopeng
2021-07-21  8:10                       ` tan.shaopeng
2021-07-21 23:39                       ` Reinette Chatre
2021-07-21 23:39                         ` Reinette Chatre
2021-05-17  8:37     ` tan.shaopeng
2021-05-17  8:37       ` tan.shaopeng

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