From: Tony Lindgren <tony@atomide.com>
To: Sven Peter <sven@svenpeter.dev>
Cc: Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-clk <linux-clk@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Hector Martin <marcan@marcan.st>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Mark Kettenis <mark.kettenis@xs4all.nl>,
Arnd Bergmann <arnd@kernel.org>
Subject: Re: [PATCH 0/3] Apple M1 clock gate driver
Date: Wed, 2 Jun 2021 12:28:06 +0300 [thread overview]
Message-ID: <YLdPJk+RBNmw3zJz@atomide.com> (raw)
In-Reply-To: <6052f2f1-1e3f-474e-a767-e08ca19fbd43@www.fastmail.com>
* Sven Peter <sven@svenpeter.dev> [210530 11:11]:
> The problem with that approach is that to enable e.g. UART_0 we actually need
> to enable its parents as well, e.g. the Apple Device Tree for the M1 has the
> following clock topology:
>
> UART0 (0x23b700270), parent: UART_P
> UART_P (0x23b700220), parent: SIO
> SIO (0x23b7001c0), parent: n/a
>
> The offsets and the parent/child relationship for all of these three clocks
> change between SoCs. If I now use the offset as the clock id I still need
> to specify that if e.g. UART uses <&clk_controller 0x270> I first need
> to enable 0x1c0 and then 0x220 and only then 0x270.
Maybe take a look what I suggested on using assigned-clocks and related
properties in the clock controller node. That might solve the issue in
a generic way for other SoCs too.
Regards,
Tony
WARNING: multiple messages have this Message-ID (diff)
From: Tony Lindgren <tony@atomide.com>
To: Sven Peter <sven@svenpeter.dev>
Cc: Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-clk <linux-clk@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Hector Martin <marcan@marcan.st>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Mark Kettenis <mark.kettenis@xs4all.nl>,
Arnd Bergmann <arnd@kernel.org>
Subject: Re: [PATCH 0/3] Apple M1 clock gate driver
Date: Wed, 2 Jun 2021 12:28:06 +0300 [thread overview]
Message-ID: <YLdPJk+RBNmw3zJz@atomide.com> (raw)
In-Reply-To: <6052f2f1-1e3f-474e-a767-e08ca19fbd43@www.fastmail.com>
* Sven Peter <sven@svenpeter.dev> [210530 11:11]:
> The problem with that approach is that to enable e.g. UART_0 we actually need
> to enable its parents as well, e.g. the Apple Device Tree for the M1 has the
> following clock topology:
>
> UART0 (0x23b700270), parent: UART_P
> UART_P (0x23b700220), parent: SIO
> SIO (0x23b7001c0), parent: n/a
>
> The offsets and the parent/child relationship for all of these three clocks
> change between SoCs. If I now use the offset as the clock id I still need
> to specify that if e.g. UART uses <&clk_controller 0x270> I first need
> to enable 0x1c0 and then 0x220 and only then 0x270.
Maybe take a look what I suggested on using assigned-clocks and related
properties in the clock controller node. That might solve the issue in
a generic way for other SoCs too.
Regards,
Tony
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next prev parent reply other threads:[~2021-06-02 9:28 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-24 18:27 [PATCH 0/3] Apple M1 clock gate driver Sven Peter
2021-05-24 18:27 ` Sven Peter
2021-05-24 18:27 ` [PATCH 1/3] dt-bindings: clock: add DT bindings for apple,gate-clock Sven Peter
2021-05-24 18:27 ` Sven Peter
2021-05-24 18:27 ` [PATCH 2/3] clk: add support for gate clocks on Apple SoCs Sven Peter
2021-05-24 18:27 ` Sven Peter
2021-05-26 3:09 ` Stephen Boyd
2021-05-26 3:09 ` Stephen Boyd
2021-05-30 11:17 ` Sven Peter
2021-05-30 11:17 ` Sven Peter
2021-05-24 18:27 ` [PATCH 3/3] arm64: apple: add uart gate clocks Sven Peter
2021-05-24 18:27 ` Sven Peter
2021-05-26 3:10 ` Stephen Boyd
2021-05-26 3:10 ` Stephen Boyd
2021-05-30 11:11 ` Sven Peter
2021-05-30 11:11 ` Sven Peter
2021-05-25 17:41 ` [PATCH 0/3] Apple M1 clock gate driver Rob Herring
2021-05-25 17:41 ` Rob Herring
2021-05-26 7:18 ` Tony Lindgren
2021-05-26 7:18 ` Tony Lindgren
2021-05-30 11:08 ` Sven Peter
2021-05-30 11:08 ` Sven Peter
2021-06-02 9:26 ` Tony Lindgren
2021-06-02 9:26 ` Tony Lindgren
2021-06-03 12:55 ` Sven Peter
2021-06-03 12:55 ` Sven Peter
2021-06-04 7:43 ` Tony Lindgren
2021-06-04 7:43 ` Tony Lindgren
2021-06-05 12:12 ` Sven Peter
2021-06-05 12:12 ` Sven Peter
2021-06-06 5:59 ` Tony Lindgren
2021-06-06 5:59 ` Tony Lindgren
2021-05-30 11:05 ` Sven Peter
2021-05-30 11:05 ` Sven Peter
2021-06-02 9:28 ` Tony Lindgren [this message]
2021-06-02 9:28 ` Tony Lindgren
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