All of lore.kernel.org
 help / color / mirror / Atom feed
* [Intel-gfx] [PATCH] drm/i915/gen11: use ffs for minconfig slice/subslice
@ 2021-06-11 14:34 Tejas Upadhyay
  2021-06-11 17:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Tejas Upadhyay @ 2021-06-11 14:34 UTC (permalink / raw)
  To: intel-gfx

w/a on gen11 platforms not working as expected and causing
more harm on the RC6 flow. Because of subslice steering
disturbance w/a read is failing. By using ffs we can default
steering of slice/sublice to minconfig hence w/a will pass
and any warns will go away.

Fixes: fb899dd8ea9c ("drm/i915: Apply Wa_1406680159:icl,ehl as an engine workaround")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +++++++++++---
 drivers/gpu/drm/i915/intel_pm.c             | 10 +++++++---
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b62d1e31a645..68b14141088a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -991,13 +991,21 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		l3_en = ~0;
 	}
 
-	slice = fls(sseu->slice_mask) - 1;
-	subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
+	if (GRAPHICS_VER(i915) == 11) {
+		slice = ffs(sseu->slice_mask) - 1;
+		subslice = ffs(l3_en & intel_sseu_get_subslices(sseu, slice));
+	} else {
+		slice = fls(sseu->slice_mask) - 1;
+		subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
+	}
 	if (!subslice) {
 		drm_warn(&i915->drm,
 			 "No common index found between subslice mask %x and L3 bank mask %x!\n",
 			 intel_sseu_get_subslices(sseu, slice), l3_en);
-		subslice = fls(l3_en);
+		if (GRAPHICS_VER(i915) == 11)
+			subslice = ffs(l3_en);
+		else
+			subslice = fls(l3_en);
 		drm_WARN_ON(&i915->drm, !subslice);
 	}
 	subslice--;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 45fefa0ed160..d1352ec3546a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4049,9 +4049,13 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
 		ddb->end = 0;
 		return;
 	}
-
-	ddb->start = (ffs(slice_mask) - 1) * slice_size;
-	ddb->end = fls(slice_mask) * slice_size;
+	if (GRAPHICS_VER(dev_priv) == 11) {
+		ddb->start = (fls(slice_mask) - 1) * slice_size;
+		ddb->end = ffs(slice_mask) * slice_size;
+	} else {
+		ddb->start = (ffs(slice_mask) - 1) * slice_size;
+		ddb->end = fls(slice_mask) * slice_size;
+	}
 
 	WARN_ON(ddb->start >= ddb->end);
 	WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
-- 
2.31.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-06-14 16:33 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-06-11 14:34 [Intel-gfx] [PATCH] drm/i915/gen11: use ffs for minconfig slice/subslice Tejas Upadhyay
2021-06-11 17:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-06-11 18:06 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2021-06-12  9:55   ` Surendrakumar Upadhyay, TejaskumarX
2021-06-14 16:33     ` Matt Roper
2021-06-11 18:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.