Re: [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC

[Rob Herring <robh@kernel.org>]

On Tue, Jul 20, 2021 at 10:52:49AM +0530, kenchappa.demakkanavar@intel.com wrote:
> From: "Demakkanavar, Kenchappa" <kenchappa.demakkanavar@intel.com>
> 
> Add initial device tree for Intel Movidius SoC code-named Thunder Bay.
> 
> This initial DT includes nodes for 4 CPU clusters with 4 Cortex-A53
> cores per cluster, UARTs, GIC, ARM Timer and PSCI.

Make sure you run 'make dtbs_check' on these.

There shouldn't be any dtc warnings and or undocumented compatible 
warnings at a minimum.

> thunderbay-soc.dtsi   - Thunder Bay SoC dtsi file
> hddl_hybrid_4s.dts    - Thunder Bay full configuration board dts
> 			with 4 VPU processors
> hddl_hybrid_2s_02.dts - Thunder Bay prime configuration board dts with
> 			2 VPU processors (slice 0 and slice 2 enabled)
> hddl_hybrid_2s_03.dts - Thunder Bay prime configuration board dts with
> 			2 VPU processors (slice 0 and slice 3 enabled)
> hddl_hybrid_2s_12.dts - Thunder Bay prime configuration board dts with
> 			2 VPU processors (slice 1 and slice 2 enabled)
> hddl_hybrid_2s_13.dts - Thunder Bay prime configuration board dts with
> 			2 VPU processors (slice 1 and slice 3 enabled)
> 
> Signed-off-by: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com>
> ---
>  MAINTAINERS                                     |   2 +
>  arch/arm64/boot/dts/intel/Makefile              |   6 +
>  arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts |  43 +++++
>  arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts |  43 +++++
>  arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts |  43 +++++
>  arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts |  43 +++++
>  arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts    |  54 ++++++
>  arch/arm64/boot/dts/intel/thunderbay-soc.dtsi   | 243 ++++++++++++++++++++++++
>  8 files changed, 477 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts
>  create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts
>  create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts
>  create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts
>  create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts
>  create mode 100644 arch/arm64/boot/dts/intel/thunderbay-soc.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 041f9a0..68317f0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1996,6 +1996,8 @@ ARM/INTEL THUNDERBAY ARCHITECTURE
>  M:	Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com>
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/arm/intel,thunderbay.yaml
> +F:	arch/arm64/boot/dts/intel/hddl*
> +F:	arch/arm64/boot/dts/intel/thunderbay-soc.dtsi
>  
>  ARM/INTEL XSC3 (MANZANO) ARM CORE
>  M:	Lennert Buytenhek <kernel@wantstofly.org>
> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
> index 0b54774..767b74b 100644
> --- a/arch/arm64/boot/dts/intel/Makefile
> +++ b/arch/arm64/boot/dts/intel/Makefile
> @@ -3,3 +3,9 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
>  				socfpga_agilex_socdk_nand.dtb \
>  				socfpga_n5x_socdk.dtb
>  dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
> +
> +dtb-$(CONFIG_ARCH_THUNDERBAY) += hddl_hybrid_4s.dtb \
> +				 hddl_hybrid_2s_02.dtb \
> +				 hddl_hybrid_2s_03.dtb \
> +				 hddl_hybrid_2s_12.dtb \
> +				 hddl_hybrid_2s_13.dtb
> diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts
> new file mode 100644
> index 0000000..f907ddd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2021 Intel Corporation.
> + *
> + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration
> + * board.
> + *
> + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 2
> + */
> +
> +/dts-v1/;
> +
> +#include "thunderbay-soc.dtsi"
> +
> +/ {
> +	model = "Intel Thunder Bay Hybrid HDDL Prime Board";
> +	compatible = "intel,thunderbay";
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;

Why do you have an alias to a disabled node?

> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@100A000000 {

Lowercase hex on unit-addresses.

> +		device_type = "memory";
> +		/* 8GB of DDR memory */
> +		reg = <0x10 0x0A000000 0x2 0x0>;
> +	};
> +
> +	memory@1200000000 {
> +		device_type = "memory";
> +		/* 4GB of DDR memory */
> +		reg = <0x12 0x0 0x1 0x0>;
> +	};
> +
> +};
> diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts
> new file mode 100644
> index 0000000..01a3d4c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2021 Intel Corporation.
> + *
> + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration
> + * board
> + *
> + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 3
> + */
> +
> +/dts-v1/;
> +
> +#include "thunderbay-soc.dtsi"
> +
> +/ {
> +	model = "Intel Thunder Bay Hybrid HDDL Prime Board";
> +	compatible = "intel,thunderbay";

This should have a board specific compatible. Not sure if you need 1 or 
4 though. If the VPU slice stuff is determined elsewhere then 1 is 
enough.

> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@100A000000 {
> +		device_type = "memory";
> +		/* 8GB of DDR memory */
> +		reg = <0x10 0x0A000000 0x2 0x0>;
> +	};
> +
> +	memory@1200000000 {
> +		device_type = "memory";
> +		/* 4GB of DDR memory */
> +		reg = <0x12 0x0 0x1 0x0>;
> +	};
> +
> +};
> diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts
> new file mode 100644
> index 0000000..e31db16
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2021 Intel Corporation.
> + *
> + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration
> + * board
> + *
> + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 2
> + */
> +
> +/dts-v1/;
> +
> +#include "thunderbay-soc.dtsi"
> +
> +/ {
> +	model = "Intel Thunder Bay Hybrid HDDL Prime Board";
> +	compatible = "intel,thunderbay";
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@100A000000 {
> +		device_type = "memory";
> +		/* 8GB of DDR memory */
> +		reg = <0x10 0x0A000000 0x2 0x0>;
> +	};
> +
> +	memory@1200000000 {
> +		device_type = "memory";
> +		/* 4GB of DDR memory */
> +		reg = <0x12 0x0 0x1 0x0>;
> +	};
> +
> +};
> diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts
> new file mode 100644
> index 0000000..6529664
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2021 Intel Corporation.
> + *
> + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration
> + * board
> + *
> + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 3
> + */
> +
> +/dts-v1/;
> +
> +#include "thunderbay-soc.dtsi"
> +
> +/ {
> +	model = "Intel Thunder Bay Hybrid HDDL Prime Board";
> +	compatible = "intel,thunderbay";
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@100A000000 {
> +		device_type = "memory";
> +		/* 8GB of DDR memory */
> +		reg = <0x10 0x0A000000 0x2 0x0>;
> +	};
> +
> +	memory@1200000000 {
> +		device_type = "memory";
> +		/* 4GB of DDR memory */
> +		reg = <0x12 0x0 0x1 0x0>;
> +	};
> +
> +};

These all look the same, why do we need 4 copies?

> diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts
> new file mode 100644
> index 0000000..561ecea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2021 Intel Corporation.
> + *
> + * Device tree describing Intel Thunder Bay Hybrid HDDL Full configuration
> + * board
> + *
> + * DDR 8GB + 8GB + 4GB + 4GB with four vpu slices
> + */
> +
> +/dts-v1/;
> +
> +#include "thunderbay-soc.dtsi"
> +
> +/ {
> +	model = "Intel Thunder Bay Hybrid HDDL Full Board";
> +	compatible = "intel,thunderbay";
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@100A000000 {
> +		device_type = "memory";
> +		/* 8GB of DDR memory */
> +		reg = <0x10 0x0A000000 0x2 0x0>;
> +	};
> +
> +	memory@1200000000 {
> +		device_type = "memory";
> +		/* 8GB of DDR memory */
> +		reg = <0x12 0x0 0x2 0x0>;
> +	};
> +
> +	memory@1400000000 {
> +		device_type = "memory";
> +		/* 4GB of DDR memory */
> +		reg = <0x14 0x0 0x1 0x0>;
> +	};
> +
> +	memory@1500000000 {
> +		device_type = "memory";
> +		/* 4GB of DDR memory */
> +		reg = <0x15 0x0 0x1 0x0>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi
> new file mode 100644
> index 0000000..834200d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi
> @@ -0,0 +1,243 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2021 Intel Corporation.
> + *
> + * Device tree describing Thunder Bay SoC
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +
> +	compatible = "intel,thunderbay";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&CPU0>;
> +				};
> +				core1 {
> +					cpu = <&CPU1>;
> +				};
> +				core2 {
> +					cpu = <&CPU2>;
> +				};
> +				core3 {
> +					cpu = <&CPU3>;
> +				};
> +			};
> +			cluster1 {
> +				core0 {
> +					cpu = <&CPU4>;
> +				};
> +				core1 {
> +					cpu = <&CPU5>;
> +				};
> +				core2 {
> +					cpu = <&CPU6>;
> +				};
> +				core3 {
> +					cpu = <&CPU7>;
> +				};
> +			};
> +			cluster2 {
> +				core0 {
> +					cpu = <&CPU8>;
> +				};
> +				core1 {
> +					cpu = <&CPU9>;
> +				};
> +				core2 {
> +					cpu = <&CPU10>;
> +				};
> +				core3 {
> +					cpu = <&CPU11>;
> +				};
> +			};
> +			cluster3 {
> +				core0 {
> +					cpu = <&CPU12>;
> +				};
> +				core1 {
> +					cpu = <&CPU13>;
> +				};
> +				core2 {
> +					cpu = <&CPU14>;
> +				};
> +				core3 {
> +					cpu = <&CPU15>;
> +				};
> +			};
> +		};
> +
> +		CPU0: cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU1: cpu@1 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x1>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU2: cpu@2 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x2>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU3: cpu@3 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x3>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU4: cpu@100 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x100>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU5: cpu@101 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x101>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU6: cpu@102 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x102>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU7: cpu@103 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x103>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU8: cpu@200 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x200>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU9: cpu@201 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x201>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU10: cpu@202 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x202>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU11: cpu@203 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x203>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU12: cpu@300 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x300>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU13: cpu@301 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x301>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU14: cpu@302 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x302>;
> +			enable-method = "psci";
> +		};
> +
> +		CPU15: cpu@303 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x303>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";

PSCI 1.0 has been out for 6 years...

> +		method = "smc";
> +	};
> +
> +	gic: interrupt-controller@88400000 {
> +		compatible = "arm,gic-v3";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		reg = <0x0 0x88400000 0x0 0x200000>,	/* GICD */
> +		      <0x0 0x88600000 0x0 0x200000>;	/* GICR */
> +		/* VGIC maintenance interrupt */
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		/* Secure, non-secure, virtual, and hypervisor */
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		dma-ranges;
> +
> +		uart0: serial@80460000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x80460000 0x0 0x100>;
> +			interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <50000000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +		};
> +
> +		uart1: serial@80470000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x80470000 0x0 0x100>;
> +			interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <50000000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +	};
> +};
> -- 
> 2.7.4
> 
> 

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