* [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node
2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
@ 2021-08-12 7:41 ` Rajesh Patil
2021-08-12 13:09 ` Matthias Kaehlcke
2021-08-12 7:41 ` [PATCH V5 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil
` (5 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Rajesh Patil @ 2021-08-12 7:41 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: swboyd, linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QSPI DT node and qspi_opp_table for SC7280 SoC.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 ++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d0..f8dd5ff 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -415,6 +415,25 @@
method = "smc";
};
+ qspi_opp_table: qspi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -1318,6 +1337,24 @@
};
};
+ qspi: spi@88dc000 {
+ compatible = "qcom,qspi-v1";
+ reg = <0 0x088dc000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <&gcc GCC_QSPI_CORE_CLK>;
+ clock-names = "iface", "core";
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0
+ &cnoc2 SLAVE_QSPI_0 0>;
+ interconnect-names = "qspi-config";
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qspi_opp_table>;
+ status = "disabled";
+
+ };
+
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
@@ -1513,6 +1550,31 @@
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
+ qspi_clk: qspi-clk {
+ pins = "gpio14";
+ function = "qspi_clk";
+ };
+
+ qspi_cs0: qspi-cs0 {
+ pins = "gpio15";
+ function = "qspi_cs";
+ };
+
+ qspi_cs1: qspi-cs1 {
+ pins = "gpio19";
+ function = "qspi_cs";
+ };
+
+ qspi_data01: qspi-data01 {
+ pins = "gpio12", "gpio13";
+ function = "qspi_data";
+ };
+
+ qspi_data12: qspi-data12 {
+ pins = "gpio16", "gpio17";
+ function = "qspi_data";
+ };
+
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node
2021-08-12 7:41 ` [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node Rajesh Patil
@ 2021-08-12 13:09 ` Matthias Kaehlcke
2021-08-26 12:59 ` rajpat
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-08-12 13:09 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On Thu, Aug 12, 2021 at 01:11:12PM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>
> Add QSPI DT node and qspi_opp_table for SC7280 SoC.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..f8dd5ff 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -415,6 +415,25 @@
> method = "smc";
> };
>
> + qspi_opp_table: qspi-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-75000000 {
> + opp-hz = /bits/ 64 <75000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-150000000 {
> + opp-hz = /bits/ 64 <150000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +
From v3:
roja> Can we move this "qspi_opp_table" to / from /soc?
bjorn> If you have made a proper attempt to convince Rob and Mark that
bjorn> a child "opp-table" in a SPI master is not a SPI device - and the
bjorn> conclusion is that this is not a good idea...then yes it should live
bjorn> outside /soc.
I didn't see a follow up on this, was such an attempt made? Is there a
link to the discussion?
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node
2021-08-12 13:09 ` Matthias Kaehlcke
@ 2021-08-26 12:59 ` rajpat
2021-09-03 15:46 ` Matthias Kaehlcke
0 siblings, 1 reply; 24+ messages in thread
From: rajpat @ 2021-08-26 12:59 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On 2021-08-12 18:39, Matthias Kaehlcke wrote:
> On Thu, Aug 12, 2021 at 01:11:12PM +0530, Rajesh Patil wrote:
>> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>>
>> Add QSPI DT node and qspi_opp_table for SC7280 SoC.
>>
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 62
>> ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 62 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 53a21d0..f8dd5ff 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -415,6 +415,25 @@
>> method = "smc";
>> };
>>
>> + qspi_opp_table: qspi-opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-75000000 {
>> + opp-hz = /bits/ 64 <75000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-150000000 {
>> + opp-hz = /bits/ 64 <150000000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> +
>
> From v3:
>
> roja> Can we move this "qspi_opp_table" to / from /soc?
>
> bjorn> If you have made a proper attempt to convince Rob and Mark that
> bjorn> a child "opp-table" in a SPI master is not a SPI device - and
> the
> bjorn> conclusion is that this is not a good idea...then yes it should
> live
> bjorn> outside /soc.
>
> I didn't see a follow up on this, was such an attempt made? Is there a
> link to the discussion?
For now I am keeping qspi_opp_table and qup_opp_table outside the SoC
and posting V6.
I will continue the discussion with DT folks and once concluded I will
update as required.
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node
2021-08-26 12:59 ` rajpat
@ 2021-09-03 15:46 ` Matthias Kaehlcke
0 siblings, 0 replies; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-09-03 15:46 UTC (permalink / raw)
To: rajpat
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On Thu, Aug 26, 2021 at 06:29:41PM +0530, rajpat@codeaurora.org wrote:
> On 2021-08-12 18:39, Matthias Kaehlcke wrote:
> > On Thu, Aug 12, 2021 at 01:11:12PM +0530, Rajesh Patil wrote:
> > > From: Roja Rani Yarubandi <rojay@codeaurora.org>
> > >
> > > Add QSPI DT node and qspi_opp_table for SC7280 SoC.
> > >
> > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > > ---
> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 62
> > > ++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 62 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > index 53a21d0..f8dd5ff 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > @@ -415,6 +415,25 @@
> > > method = "smc";
> > > };
> > >
> > > + qspi_opp_table: qspi-opp-table {
> > > + compatible = "operating-points-v2";
> > > +
> > > + opp-75000000 {
> > > + opp-hz = /bits/ 64 <75000000>;
> > > + required-opps = <&rpmhpd_opp_low_svs>;
> > > + };
> > > +
> > > + opp-150000000 {
> > > + opp-hz = /bits/ 64 <150000000>;
> > > + required-opps = <&rpmhpd_opp_svs>;
> > > + };
> > > +
> > > + opp-300000000 {
> > > + opp-hz = /bits/ 64 <300000000>;
> > > + required-opps = <&rpmhpd_opp_nom>;
> > > + };
> > > + };
> > > +
> >
> > From v3:
> >
> > roja> Can we move this "qspi_opp_table" to / from /soc?
> >
> > bjorn> If you have made a proper attempt to convince Rob and Mark that
> > bjorn> a child "opp-table" in a SPI master is not a SPI device - and the
> > bjorn> conclusion is that this is not a good idea...then yes it should
> > live
> > bjorn> outside /soc.
> >
> > I didn't see a follow up on this, was such an attempt made? Is there a
> > link to the discussion?
>
> For now I am keeping qspi_opp_table and qup_opp_table outside the SoC and
> posting V6.
> I will continue the discussion with DT folks and once concluded I will
> update as required.
Do you have a link to that discussion so that people can follow along or
chime in?
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH V5 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp
2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-08-12 7:41 ` [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node Rajesh Patil
@ 2021-08-12 7:41 ` Rajesh Patil
2021-08-12 13:15 ` Matthias Kaehlcke
2021-08-12 7:41 ` [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
` (4 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Rajesh Patil @ 2021-08-12 7:41 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: swboyd, linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Rajesh Patil
Add spi-nor flash node and pinctrl configurations for the same.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 371a2a9..c41c2d0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -207,6 +207,20 @@
};
};
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <37500000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -284,6 +298,19 @@
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+&qspi_cs0 {
+ bias-disable;
+};
+
+&qspi_clk {
+ bias-disable;
+};
+
+&qspi_data01 {
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
+};
+
&qup_uart5_default {
tx {
pins = "gpio46";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH V5 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp
2021-08-12 7:41 ` [PATCH V5 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil
@ 2021-08-12 13:15 ` Matthias Kaehlcke
2021-08-23 11:44 ` rajpat
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-08-12 13:15 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On Thu, Aug 12, 2021 at 01:11:13PM +0530, Rajesh Patil wrote:
> Add spi-nor flash node and pinctrl configurations for the same.
nit: better name SC7280 IDP explicitly rather than saying 'the same'.
>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH V5 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp
2021-08-12 13:15 ` Matthias Kaehlcke
@ 2021-08-23 11:44 ` rajpat
0 siblings, 0 replies; 24+ messages in thread
From: rajpat @ 2021-08-23 11:44 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On 2021-08-12 18:45, Matthias Kaehlcke wrote:
> On Thu, Aug 12, 2021 at 01:11:13PM +0530, Rajesh Patil wrote:
>> Add spi-nor flash node and pinctrl configurations for the same.
>
> nit: better name SC7280 IDP explicitly rather than saying 'the same'.
>
ok.I will change it
>>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-08-12 7:41 ` [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node Rajesh Patil
2021-08-12 7:41 ` [PATCH V5 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil
@ 2021-08-12 7:41 ` Rajesh Patil
2021-08-12 14:14 ` Matthias Kaehlcke
2021-08-19 0:04 ` Doug Anderson
2021-08-12 7:41 ` [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node Rajesh Patil
` (3 subsequent siblings)
6 siblings, 2 replies; 24+ messages in thread
From: Rajesh Patil @ 2021-08-12 7:41 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: swboyd, linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 720 +++++++++++++++++++++++++++++++++++
1 file changed, 720 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f8dd5ff..e461395 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -533,6 +533,25 @@
};
+ qup_opp_table: qup-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
@@ -542,8 +561,305 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ iommus = <&apps_smmu 0x123 0x0>;
status = "disabled";
+ i2c0: i2c@980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi0: spi@980000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>, <&qup_spi0_cs_gpio>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart0: serial@980000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c1: i2c@984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>, <&qup_spi1_cs_gpio>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart1: serial@984000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>, <&qup_spi2_cs_gpio>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart2: serial@988000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c3: i2c@98c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0098c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0098c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>, <&qup_spi3_cs_gpio>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart3: serial@98c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0098c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c4: i2c@990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00990000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00990000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>, <&qup_spi4_cs_gpio>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart4: serial@990000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00990000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00994000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00994000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>, <&qup_spi5_cs_gpio>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
uart5: serial@994000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x00994000 0 0x4000>;
@@ -554,6 +870,110 @@
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>, <&qup_spi6_cs_gpio>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart6: serial@998000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c7: i2c@99c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi7: spi@99c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>, <&qup_spi7_cs_gpio>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart7: serial@99c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
};
cnoc2: interconnect@1500000 {
@@ -1575,11 +1995,311 @@
function = "qspi_data";
};
+ qup_i2c0_data_clk:qup-i2c0-data-clk {
+ pins = "gpio0", "gpio1";
+ function = "qup00";
+ };
+
+ qup_i2c1_data_clk:qup-i2c1-data-clk {
+ pins = "gpio4", "gpio5";
+ function = "qup01";
+ };
+
+ qup_i2c2_data_clk:qup-i2c2-data-clk {
+ pins = "gpio8", "gpio9";
+ function = "qup02";
+ };
+
+ qup_i2c3_data_clk:qup-i2c3-data-clk {
+ pins = "gpio12", "gpio13";
+ function = "qup03";
+ };
+
+ qup_i2c4_data_clk:qup-i2c4-data-clk {
+ pins = "gpio16", "gpio17";
+ function = "qup04";
+ };
+
+ qup_i2c5_data_clk:qup-i2c5-data-clk {
+ pins = "gpio20", "gpio21";
+ function = "qup05";
+ };
+
+ qup_i2c6_data_clk:qup-i2c6-data-clk {
+ pins = "gpio24", "gpio25";
+ function = "qup06";
+ };
+
+ qup_i2c7_data_clk:qup-i2c7-data-clk {
+ pins = "gpio28", "gpio29";
+ function = "qup07";
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk {
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup00";
+ };
+
+ qup_spi0_cs: qup-spi0-cs {
+ pins = "gpio3";
+ function = "qup00";
+ };
+
+ qup_spi0_cs_gpio: qup-spi0-cs_gpio {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk {
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup01";
+ };
+
+ qup_spi1_cs: qup-spi1-cs {
+ pins = "gpio7";
+ function = "qup01";
+ };
+
+ qup_spi1_cs_gpio: qup-spi1-cs_gpio {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk {
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup02";
+ };
+
+ qup_spi2_cs: qup-spi2-cs {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qup_spi2_cs_gpio: qup-spi2-cs_gpio {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk {
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup03";
+ };
+
+ qup_spi3_cs: qup-spi3-cs {
+ pins = "gpio15";
+ function = "qup03";
+ };
+
+ qup_spi3_cs_gpio: qup-spi3-cs_gpio {
+ pins = "gpio15";
+ function = "gpio";
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk {
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup04";
+ };
+
+ qup_spi4_cs: qup-spi4-cs {
+ pins = "gpio19";
+ function = "qup04";
+ };
+
+ qup_spi4_cs_gpio: qup-spi4-cs_gpio {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk {
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup05";
+ };
+
+ qup_spi5_cs: qup-spi5-cs {
+ pins = "gpio23";
+ function = "qup05";
+ };
+
+ qup_spi5_cs_gpio: qup-spi5-cs_gpio {
+ pins = "gpio23";
+ function = "gpio";
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk {
+ pins = "gpio24", "gpio25", "gpio26";
+ function = "qup06";
+ };
+
+ qup_spi6_cs: qup-spi6-cs {
+ pins = "gpio27";
+ function = "qup06";
+ };
+
+ qup_spi6_cs_gpio: qup-spi6-cs_gpio {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ qup_spi7_data_clk: qup-spi7-data-clk {
+ pins = "gpio28", "gpio29", "gpio30";
+ function = "qup07";
+ };
+
+ qup_spi7_cs: qup-spi7-cs {
+ pins = "gpio31";
+ function = "qup07";
+ };
+
+ qup_spi7_cs_gpio: qup-spi7-cs_gpio {
+ pins = "gpio31";
+ function = "gpio";
+ };
+
+ qup_uart0_cts: qup-uart0-cts {
+ pins = "gpio0";
+ function = "qup00";
+ };
+
+ qup_uart0_rts: qup-uart0-rts {
+ pins = "gpio1";
+ function = "qup00";
+ };
+
+ qup_uart0_tx: qup-uart0-tx {
+ pins = "gpio2";
+ function = "qup00";
+ };
+
+ qup_uart0_rx: qup-uart0-rx {
+ pins = "gpio3";
+ function = "qup00";
+ };
+
+ qup_uart1_cts: qup-uart1-cts {
+ pins = "gpio4";
+ function = "qup01";
+ };
+
+ qup_uart1_rts: qup-uart1-rts {
+ pins = "gpio5";
+ function = "qup01";
+ };
+
+ qup_uart1_tx: qup-uart1-tx {
+ pins = "gpio6";
+ function = "qup01";
+ };
+
+ qup_uart1_rx: qup-uart1-rx {
+ pins = "gpio7";
+ function = "qup01";
+ };
+
+ qup_uart2_cts: qup-uart2-cts {
+ pins = "gpio8";
+ function = "qup02";
+ };
+
+ qup_uart2_rts: qup-uart2-rts {
+ pins = "gpio9";
+ function = "qup02";
+ };
+
+ qup_uart2_tx: qup-uart2-tx {
+ pins = "gpio10";
+ function = "qup02";
+ };
+
+ qup_uart2_rx: qup-uart2-rx {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qup_uart3_cts: qup-uart3-cts {
+ pins = "gpio12";
+ function = "qup03";
+ };
+
+ qup_uart3_rts: qup-uart3-rts {
+ pins = "gpio13";
+ function = "qup03";
+ };
+
+ qup_uart3_tx: qup-uart3-tx {
+ pins = "gpio14";
+ function = "qup03";
+ };
+
+ qup_uart3_rx: qup-uart3-rx {
+ pins = "gpio15";
+ function = "qup03";
+ };
+
+ qup_uart4_cts: qup-uart4-cts {
+ pins = "gpio16";
+ function = "qup04";
+ };
+
+ qup_uart4_rts: qup-uart4-rts {
+ pins = "gpio17";
+ function = "qup04";
+ };
+
+ qup_uart4_tx: qup-uart4-tx {
+ pins = "gpio18";
+ function = "qup04";
+ };
+
+ qup_uart4_rx: qup-uart4-rx {
+ pins = "gpio19";
+ function = "qup04";
+ };
+
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
};
+ qup_uart6_cts: qup-uart6-cts {
+ pins = "gpio24";
+ function = "qup06";
+ };
+
+ qup_uart6_rts: qup-uart6-rts {
+ pins = "gpio25";
+ function = "qup06";
+ };
+
+ qup_uart6_tx: qup-uart6-tx {
+ pins = "gpio26";
+ function = "qup06";
+ };
+
+ qup_uart6_rx: qup-uart6-rx {
+ pins = "gpio27";
+ function = "qup06";
+ };
+
+ qup_uart7_cts: qup-uart7-cts {
+ pins = "gpio28";
+ function = "qup07";
+ };
+
+ qup_uart7_rts: qup-uart7-rts {
+ pins = "gpio29";
+ function = "qup07";
+ };
+
+ qup_uart7_tx: qup-uart7-tx {
+ pins = "gpio30";
+ function = "qup07";
+ };
+
+ qup_uart7_rx: qup-uart7-rx {
+ pins = "gpio31";
+ function = "qup07";
+ };
+
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-12 7:41 ` [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
@ 2021-08-12 14:14 ` Matthias Kaehlcke
2021-08-12 16:22 ` Matthias Kaehlcke
2021-08-26 13:07 ` rajpat
2021-08-19 0:04 ` Doug Anderson
1 sibling, 2 replies; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-08-12 14:14 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On Thu, Aug 12, 2021 at 01:11:14PM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>
> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 720 +++++++++++++++++++++++++++++++++++
> 1 file changed, 720 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index f8dd5ff..e461395 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -533,6 +533,25 @@
>
> };
>
> + qup_opp_table: qup-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-75000000 {
> + opp-hz = /bits/ 64 <75000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-128000000 {
> + opp-hz = /bits/ 64 <128000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +
Shouldn't the OPP table live outside of /soc, analogous to the discussion
about the QSPI OPP table (https://lkml.org/lkml/2021/7/19/3063)?
> qupv3_id_0: geniqup@9c0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0 0x009c0000 0 0x2000>;
> @@ -542,8 +561,305 @@
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> + iommus = <&apps_smmu 0x123 0x0>;
> status = "disabled";
>
> + i2c0: i2c@980000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00980000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
nit: the general convention seems to be 'clocks' followed by 'clock-names'.
Applicable to all nodes if you decide to change it.
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c0_data_clk>;
> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config",
> + "qup-memory";
> + status = "disabled";
> + };
> +
> + spi0: spi@980000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00980000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>, <&qup_spi0_cs_gpio>;
What is the story behind 'qup_spiN_cs' and 'qup_spiN_cs_gpio'? Both configure
the CS pin with a different function:
qup_spi0_cs: qup-spi0-cs {
pins = "gpio3";
function = "qup00";
};
qup_spi0_cs_gpio: qup-spi0-cs_gpio {
pins = "gpio3";
function = "gpio";
};
> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + uart0: serial@980000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x00980000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@984000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00984000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c1_data_clk>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config",
> + "qup-memory";
> + status = "disabled";
> + };
> +
> + spi1: spi@984000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00984000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>, <&qup_spi1_cs_gpio>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + uart1: serial@984000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x00984000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@988000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00988000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c2_data_clk>;
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config",
> + "qup-memory";
> + status = "disabled";
> + };
> +
> + spi2: spi@988000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00988000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>, <&qup_spi2_cs_gpio>;
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + uart2: serial@988000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x00988000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + i2c3: i2c@98c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0098c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c3_data_clk>;
> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config",
> + "qup-memory";
> + status = "disabled";
> + };
> +
> + spi3: spi@98c000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x0098c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>, <&qup_spi3_cs_gpio>;
> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + uart3: serial@98c000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x0098c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@990000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00990000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c4_data_clk>;
> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config",
> + "qup-memory";
> + status = "disabled";
> + };
> +
> + spi4: spi@990000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00990000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>, <&qup_spi4_cs_gpio>;
> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + uart4: serial@990000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x00990000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + i2c5: i2c@994000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00994000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c5_data_clk>;
> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config",
> + "qup-memory";
> + status = "disabled";
> + };
> +
> + spi5: spi@994000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00994000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>, <&qup_spi5_cs_gpio>;
> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> uart5: serial@994000 {
> compatible = "qcom,geni-debug-uart";
> reg = <0 0x00994000 0 0x4000>;
> @@ -554,6 +870,110 @@
> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
> +
> + i2c6: i2c@998000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00998000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c6_data_clk>;
> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config",
> + "qup-memory";
> + status = "disabled";
> + };
> +
> + spi6: spi@998000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00998000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>, <&qup_spi6_cs_gpio>;
> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + uart6: serial@998000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x00998000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + i2c7: i2c@99c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0099c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c7_data_clk>;
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config",
> + "qup-memory";
> + status = "disabled";
> + };
> +
> + spi7: spi@99c000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x0099c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>, <&qup_spi7_cs_gpio>;
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> +
> + uart7: serial@99c000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x0099c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> + status = "disabled";
> + };
> };
>
> cnoc2: interconnect@1500000 {
> @@ -1575,11 +1995,311 @@
> function = "qspi_data";
> };
>
> + qup_i2c0_data_clk:qup-i2c0-data-clk {
> + pins = "gpio0", "gpio1";
> + function = "qup00";
> + };
> +
> + qup_i2c1_data_clk:qup-i2c1-data-clk {
> + pins = "gpio4", "gpio5";
> + function = "qup01";
> + };
> +
> + qup_i2c2_data_clk:qup-i2c2-data-clk {
> + pins = "gpio8", "gpio9";
> + function = "qup02";
> + };
> +
> + qup_i2c3_data_clk:qup-i2c3-data-clk {
> + pins = "gpio12", "gpio13";
> + function = "qup03";
> + };
> +
> + qup_i2c4_data_clk:qup-i2c4-data-clk {
> + pins = "gpio16", "gpio17";
> + function = "qup04";
> + };
> +
> + qup_i2c5_data_clk:qup-i2c5-data-clk {
> + pins = "gpio20", "gpio21";
> + function = "qup05";
> + };
> +
> + qup_i2c6_data_clk:qup-i2c6-data-clk {
> + pins = "gpio24", "gpio25";
> + function = "qup06";
> + };
> +
> + qup_i2c7_data_clk:qup-i2c7-data-clk {
> + pins = "gpio28", "gpio29";
> + function = "qup07";
> + };
> +
> + qup_spi0_data_clk: qup-spi0-data-clk {
> + pins = "gpio0", "gpio1", "gpio2";
> + function = "qup00";
> + };
> +
> + qup_spi0_cs: qup-spi0-cs {
> + pins = "gpio3";
> + function = "qup00";
> + };
> +
> + qup_spi0_cs_gpio: qup-spi0-cs_gpio {
> + pins = "gpio3";
> + function = "gpio";
> + };
> +
> + qup_spi1_data_clk: qup-spi1-data-clk {
> + pins = "gpio4", "gpio5", "gpio6";
> + function = "qup01";
> + };
> +
> + qup_spi1_cs: qup-spi1-cs {
> + pins = "gpio7";
> + function = "qup01";
> + };
> +
> + qup_spi1_cs_gpio: qup-spi1-cs_gpio {
> + pins = "gpio7";
> + function = "gpio";
> + };
> +
> + qup_spi2_data_clk: qup-spi2-data-clk {
> + pins = "gpio8", "gpio9", "gpio10";
> + function = "qup02";
> + };
> +
> + qup_spi2_cs: qup-spi2-cs {
> + pins = "gpio11";
> + function = "qup02";
> + };
> +
> + qup_spi2_cs_gpio: qup-spi2-cs_gpio {
> + pins = "gpio11";
> + function = "gpio";
> + };
> +
> + qup_spi3_data_clk: qup-spi3-data-clk {
> + pins = "gpio12", "gpio13", "gpio14";
> + function = "qup03";
> + };
> +
> + qup_spi3_cs: qup-spi3-cs {
> + pins = "gpio15";
> + function = "qup03";
> + };
> +
> + qup_spi3_cs_gpio: qup-spi3-cs_gpio {
> + pins = "gpio15";
> + function = "gpio";
> + };
> +
> + qup_spi4_data_clk: qup-spi4-data-clk {
> + pins = "gpio16", "gpio17", "gpio18";
> + function = "qup04";
> + };
> +
> + qup_spi4_cs: qup-spi4-cs {
> + pins = "gpio19";
> + function = "qup04";
> + };
> +
> + qup_spi4_cs_gpio: qup-spi4-cs_gpio {
> + pins = "gpio19";
> + function = "gpio";
> + };
> +
> + qup_spi5_data_clk: qup-spi5-data-clk {
> + pins = "gpio20", "gpio21", "gpio22";
> + function = "qup05";
> + };
> +
> + qup_spi5_cs: qup-spi5-cs {
> + pins = "gpio23";
> + function = "qup05";
> + };
> +
> + qup_spi5_cs_gpio: qup-spi5-cs_gpio {
> + pins = "gpio23";
> + function = "gpio";
> + };
> +
> + qup_spi6_data_clk: qup-spi6-data-clk {
> + pins = "gpio24", "gpio25", "gpio26";
> + function = "qup06";
> + };
> +
> + qup_spi6_cs: qup-spi6-cs {
> + pins = "gpio27";
> + function = "qup06";
> + };
> +
> + qup_spi6_cs_gpio: qup-spi6-cs_gpio {
> + pins = "gpio27";
> + function = "gpio";
> + };
> +
> + qup_spi7_data_clk: qup-spi7-data-clk {
> + pins = "gpio28", "gpio29", "gpio30";
> + function = "qup07";
> + };
> +
> + qup_spi7_cs: qup-spi7-cs {
> + pins = "gpio31";
> + function = "qup07";
> + };
> +
> + qup_spi7_cs_gpio: qup-spi7-cs_gpio {
> + pins = "gpio31";
> + function = "gpio";
> + };
> +
> + qup_uart0_cts: qup-uart0-cts {
> + pins = "gpio0";
> + function = "qup00";
> + };
> +
> + qup_uart0_rts: qup-uart0-rts {
> + pins = "gpio1";
> + function = "qup00";
> + };
> +
> + qup_uart0_tx: qup-uart0-tx {
> + pins = "gpio2";
> + function = "qup00";
> + };
> +
> + qup_uart0_rx: qup-uart0-rx {
> + pins = "gpio3";
> + function = "qup00";
> + };
> +
> + qup_uart1_cts: qup-uart1-cts {
> + pins = "gpio4";
> + function = "qup01";
> + };
> +
> + qup_uart1_rts: qup-uart1-rts {
> + pins = "gpio5";
> + function = "qup01";
> + };
> +
> + qup_uart1_tx: qup-uart1-tx {
> + pins = "gpio6";
> + function = "qup01";
> + };
> +
> + qup_uart1_rx: qup-uart1-rx {
> + pins = "gpio7";
> + function = "qup01";
> + };
> +
> + qup_uart2_cts: qup-uart2-cts {
> + pins = "gpio8";
> + function = "qup02";
> + };
> +
> + qup_uart2_rts: qup-uart2-rts {
> + pins = "gpio9";
> + function = "qup02";
> + };
> +
> + qup_uart2_tx: qup-uart2-tx {
> + pins = "gpio10";
> + function = "qup02";
> + };
> +
> + qup_uart2_rx: qup-uart2-rx {
> + pins = "gpio11";
> + function = "qup02";
> + };
> +
> + qup_uart3_cts: qup-uart3-cts {
> + pins = "gpio12";
> + function = "qup03";
> + };
> +
> + qup_uart3_rts: qup-uart3-rts {
> + pins = "gpio13";
> + function = "qup03";
> + };
> +
> + qup_uart3_tx: qup-uart3-tx {
> + pins = "gpio14";
> + function = "qup03";
> + };
> +
> + qup_uart3_rx: qup-uart3-rx {
> + pins = "gpio15";
> + function = "qup03";
> + };
> +
> + qup_uart4_cts: qup-uart4-cts {
> + pins = "gpio16";
> + function = "qup04";
> + };
> +
> + qup_uart4_rts: qup-uart4-rts {
> + pins = "gpio17";
> + function = "qup04";
> + };
> +
> + qup_uart4_tx: qup-uart4-tx {
> + pins = "gpio18";
> + function = "qup04";
> + };
> +
> + qup_uart4_rx: qup-uart4-rx {
> + pins = "gpio19";
> + function = "qup04";
> + };
> +
> qup_uart5_default: qup-uart5-default {
> pins = "gpio46", "gpio47";
> function = "qup13";
> };
Wait, why does uart5 use the pins of qup13? Is see this is
'fixed' by '[4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT
node' but I'm still surprised ...
Doesn't 'fixing' this break devices that are currently using
'uart5'? It seems those devices would need to change from
'uart5' to 'uart11'.
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-12 14:14 ` Matthias Kaehlcke
@ 2021-08-12 16:22 ` Matthias Kaehlcke
2021-08-26 13:07 ` rajpat
1 sibling, 0 replies; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-08-12 16:22 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On Thu, Aug 12, 2021 at 07:14:07AM -0700, Matthias Kaehlcke wrote:
> On Thu, Aug 12, 2021 at 01:11:14PM +0530, Rajesh Patil wrote:
> > qup_uart5_default: qup-uart5-default {
> > pins = "gpio46", "gpio47";
> > function = "qup13";
> > };
>
> Wait, why does uart5 use the pins of qup13? Is see this is
> 'fixed' by '[4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT
> node' but I'm still surprised ...
>
> Doesn't 'fixing' this break devices that are currently using
> 'uart5'? It seems those devices would need to change from
> 'uart5' to 'uart11'.
Apparently the above configuration is bogus. I checked the schematic
of the IDP which uses uart5, the debug UART is on pins 22 and 23, aka
qup05. It seems uart5 works in spite of the bogus pinconf because the
default for the pins is their QUP function.
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-12 14:14 ` Matthias Kaehlcke
2021-08-12 16:22 ` Matthias Kaehlcke
@ 2021-08-26 13:07 ` rajpat
2021-08-26 19:51 ` Matthias Kaehlcke
1 sibling, 1 reply; 24+ messages in thread
From: rajpat @ 2021-08-26 13:07 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On 2021-08-12 19:44, Matthias Kaehlcke wrote:
> On Thu, Aug 12, 2021 at 01:11:14PM +0530, Rajesh Patil wrote:
>> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>>
>> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>>
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 720
>> +++++++++++++++++++++++++++++++++++
>> 1 file changed, 720 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index f8dd5ff..e461395 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -533,6 +533,25 @@
>>
>> };
>>
>> + qup_opp_table: qup-opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-75000000 {
>> + opp-hz = /bits/ 64 <75000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-100000000 {
>> + opp-hz = /bits/ 64 <100000000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-128000000 {
>> + opp-hz = /bits/ 64 <128000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> +
>
> Shouldn't the OPP table live outside of /soc, analogous to the
> discussion
> about the QSPI OPP table (https://lkml.org/lkml/2021/7/19/3063)?
Ok
>
>
>> qupv3_id_0: geniqup@9c0000 {
>> compatible = "qcom,geni-se-qup";
>> reg = <0 0x009c0000 0 0x2000>;
>> @@ -542,8 +561,305 @@
>> #address-cells = <2>;
>> #size-cells = <2>;
>> ranges;
>> + iommus = <&apps_smmu 0x123 0x0>;
>> status = "disabled";
>>
>> + i2c0: i2c@980000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00980000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
>
> nit: the general convention seems to be 'clocks' followed by
> 'clock-names'.
> Applicable to all nodes if you decide to change it.
Ok
>
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c0_data_clk>;
>> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi0: spi@980000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x00980000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>,
>> <&qup_spi0_cs_gpio>;
>
> What is the story behind 'qup_spiN_cs' and 'qup_spiN_cs_gpio'? Both
> configure
> the CS pin with a different function:
>
As per discussion here [1], we have split like this.
[1] https://lore.kernel.org/patchwork/patch/1393353/#1591826
> qup_spi0_cs: qup-spi0-cs {
> pins = "gpio3";
> function = "qup00";
> };
>
> qup_spi0_cs_gpio: qup-spi0-cs_gpio {
> pins = "gpio3";
> function = "gpio";
> };
>
>> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + uart0: serial@980000 {
>> + compatible = "qcom,geni-uart";
>> + reg = <0 0x00980000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>,
>> <&qup_uart0_rx>;
>> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + i2c1: i2c@984000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00984000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c1_data_clk>;
>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi1: spi@984000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x00984000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>,
>> <&qup_spi1_cs_gpio>;
>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@984000 {
>> + compatible = "qcom,geni-uart";
>> + reg = <0 0x00984000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>,
>> <&qup_uart1_rx>;
>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + i2c2: i2c@988000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00988000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c2_data_clk>;
>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi2: spi@988000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x00988000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>,
>> <&qup_spi2_cs_gpio>;
>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@988000 {
>> + compatible = "qcom,geni-uart";
>> + reg = <0 0x00988000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>,
>> <&qup_uart2_rx>;
>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + i2c3: i2c@98c000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x0098c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c3_data_clk>;
>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi3: spi@98c000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x0098c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>,
>> <&qup_spi3_cs_gpio>;
>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@98c000 {
>> + compatible = "qcom,geni-uart";
>> + reg = <0 0x0098c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>,
>> <&qup_uart3_rx>;
>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + i2c4: i2c@990000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00990000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c4_data_clk>;
>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi4: spi@990000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x00990000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>,
>> <&qup_spi4_cs_gpio>;
>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@990000 {
>> + compatible = "qcom,geni-uart";
>> + reg = <0 0x00990000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>,
>> <&qup_uart4_rx>;
>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + i2c5: i2c@994000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00994000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c5_data_clk>;
>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi5: spi@994000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x00994000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>,
>> <&qup_spi5_cs_gpio>;
>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> uart5: serial@994000 {
>> compatible = "qcom,geni-debug-uart";
>> reg = <0 0x00994000 0 0x4000>;
>> @@ -554,6 +870,110 @@
>> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
>> status = "disabled";
>> };
>> +
>> + i2c6: i2c@998000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00998000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c6_data_clk>;
>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi6: spi@998000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x00998000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>,
>> <&qup_spi6_cs_gpio>;
>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + uart6: serial@998000 {
>> + compatible = "qcom,geni-uart";
>> + reg = <0 0x00998000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>,
>> <&qup_uart6_rx>;
>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + i2c7: i2c@99c000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x0099c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c7_data_clk>;
>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
>> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config",
>> + "qup-memory";
>> + status = "disabled";
>> + };
>> +
>> + spi7: spi@99c000 {
>> + compatible = "qcom,geni-spi";
>> + reg = <0 0x0099c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>,
>> <&qup_spi7_cs_gpio>;
>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> +
>> + uart7: serial@99c000 {
>> + compatible = "qcom,geni-uart";
>> + reg = <0 0x0099c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>,
>> <&qup_uart7_rx>;
>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + status = "disabled";
>> + };
>> };
>>
>> cnoc2: interconnect@1500000 {
>> @@ -1575,11 +1995,311 @@
>> function = "qspi_data";
>> };
>>
>> + qup_i2c0_data_clk:qup-i2c0-data-clk {
>> + pins = "gpio0", "gpio1";
>> + function = "qup00";
>> + };
>> +
>> + qup_i2c1_data_clk:qup-i2c1-data-clk {
>> + pins = "gpio4", "gpio5";
>> + function = "qup01";
>> + };
>> +
>> + qup_i2c2_data_clk:qup-i2c2-data-clk {
>> + pins = "gpio8", "gpio9";
>> + function = "qup02";
>> + };
>> +
> > + qup_i2c3_data_clk:qup-i2c3-data-clk {
>> + pins = "gpio12", "gpio13";
>> + function = "qup03";
>> + };
>> +
>> + qup_i2c4_data_clk:qup-i2c4-data-clk {
>> + pins = "gpio16", "gpio17";
>> + function = "qup04";
>> + };
>> +
>> + qup_i2c5_data_clk:qup-i2c5-data-clk {
>> + pins = "gpio20", "gpio21";
>> + function = "qup05";
>> + };
>> +
>> + qup_i2c6_data_clk:qup-i2c6-data-clk {
>> + pins = "gpio24", "gpio25";
>> + function = "qup06";
>> + };
>> +
>> + qup_i2c7_data_clk:qup-i2c7-data-clk {
>> + pins = "gpio28", "gpio29";
>> + function = "qup07";
>> + };
>> +
>> + qup_spi0_data_clk: qup-spi0-data-clk {
>> + pins = "gpio0", "gpio1", "gpio2";
>> + function = "qup00";
>> + };
>> +
>> + qup_spi0_cs: qup-spi0-cs {
>> + pins = "gpio3";
>> + function = "qup00";
>> + };
>> +
>> + qup_spi0_cs_gpio: qup-spi0-cs_gpio {
>> + pins = "gpio3";
>> + function = "gpio";
>> + };
>> +
>> + qup_spi1_data_clk: qup-spi1-data-clk {
>> + pins = "gpio4", "gpio5", "gpio6";
>> + function = "qup01";
>> + };
>> +
>> + qup_spi1_cs: qup-spi1-cs {
>> + pins = "gpio7";
>> + function = "qup01";
>> + };
>> +
>> + qup_spi1_cs_gpio: qup-spi1-cs_gpio {
>> + pins = "gpio7";
>> + function = "gpio";
>> + };
>> +
>> + qup_spi2_data_clk: qup-spi2-data-clk {
>> + pins = "gpio8", "gpio9", "gpio10";
>> + function = "qup02";
>> + };
>> +
>> + qup_spi2_cs: qup-spi2-cs {
>> + pins = "gpio11";
>> + function = "qup02";
>> + };
>> +
>> + qup_spi2_cs_gpio: qup-spi2-cs_gpio {
>> + pins = "gpio11";
>> + function = "gpio";
>> + };
>> +
>> + qup_spi3_data_clk: qup-spi3-data-clk {
>> + pins = "gpio12", "gpio13", "gpio14";
>> + function = "qup03";
>> + };
>> +
>> + qup_spi3_cs: qup-spi3-cs {
>> + pins = "gpio15";
>> + function = "qup03";
>> + };
>> +
>> + qup_spi3_cs_gpio: qup-spi3-cs_gpio {
>> + pins = "gpio15";
>> + function = "gpio";
>> + };
>> +
>> + qup_spi4_data_clk: qup-spi4-data-clk {
>> + pins = "gpio16", "gpio17", "gpio18";
>> + function = "qup04";
>> + };
>> +
>> + qup_spi4_cs: qup-spi4-cs {
>> + pins = "gpio19";
>> + function = "qup04";
>> + };
>> +
>> + qup_spi4_cs_gpio: qup-spi4-cs_gpio {
>> + pins = "gpio19";
>> + function = "gpio";
>> + };
>> +
>> + qup_spi5_data_clk: qup-spi5-data-clk {
>> + pins = "gpio20", "gpio21", "gpio22";
>> + function = "qup05";
>> + };
>> +
>> + qup_spi5_cs: qup-spi5-cs {
>> + pins = "gpio23";
>> + function = "qup05";
>> + };
>> +
>> + qup_spi5_cs_gpio: qup-spi5-cs_gpio {
>> + pins = "gpio23";
>> + function = "gpio";
>> + };
>> +
>> + qup_spi6_data_clk: qup-spi6-data-clk {
>> + pins = "gpio24", "gpio25", "gpio26";
>> + function = "qup06";
>> + };
>> +
>> + qup_spi6_cs: qup-spi6-cs {
>> + pins = "gpio27";
>> + function = "qup06";
>> + };
>> +
>> + qup_spi6_cs_gpio: qup-spi6-cs_gpio {
>> + pins = "gpio27";
>> + function = "gpio";
>> + };
>> +
>> + qup_spi7_data_clk: qup-spi7-data-clk {
>> + pins = "gpio28", "gpio29", "gpio30";
>> + function = "qup07";
>> + };
>> +
>> + qup_spi7_cs: qup-spi7-cs {
>> + pins = "gpio31";
>> + function = "qup07";
>> + };
>> +
>> + qup_spi7_cs_gpio: qup-spi7-cs_gpio {
>> + pins = "gpio31";
>> + function = "gpio";
>> + };
>> +
>> + qup_uart0_cts: qup-uart0-cts {
>> + pins = "gpio0";
>> + function = "qup00";
>> + };
>> +
>> + qup_uart0_rts: qup-uart0-rts {
>> + pins = "gpio1";
>> + function = "qup00";
>> + };
>> +
>> + qup_uart0_tx: qup-uart0-tx {
>> + pins = "gpio2";
>> + function = "qup00";
>> + };
>> +
>> + qup_uart0_rx: qup-uart0-rx {
>> + pins = "gpio3";
>> + function = "qup00";
>> + };
>> +
>> + qup_uart1_cts: qup-uart1-cts {
>> + pins = "gpio4";
>> + function = "qup01";
>> + };
>> +
>> + qup_uart1_rts: qup-uart1-rts {
>> + pins = "gpio5";
>> + function = "qup01";
>> + };
>> +
>> + qup_uart1_tx: qup-uart1-tx {
>> + pins = "gpio6";
>> + function = "qup01";
>> + };
>> +
>> + qup_uart1_rx: qup-uart1-rx {
>> + pins = "gpio7";
>> + function = "qup01";
>> + };
>> +
>> + qup_uart2_cts: qup-uart2-cts {
>> + pins = "gpio8";
>> + function = "qup02";
>> + };
>> +
>> + qup_uart2_rts: qup-uart2-rts {
>> + pins = "gpio9";
>> + function = "qup02";
>> + };
>> +
>> + qup_uart2_tx: qup-uart2-tx {
>> + pins = "gpio10";
>> + function = "qup02";
>> + };
>> +
>> + qup_uart2_rx: qup-uart2-rx {
>> + pins = "gpio11";
>> + function = "qup02";
>> + };
>> +
>> + qup_uart3_cts: qup-uart3-cts {
>> + pins = "gpio12";
>> + function = "qup03";
>> + };
>> +
>> + qup_uart3_rts: qup-uart3-rts {
>> + pins = "gpio13";
>> + function = "qup03";
>> + };
>> +
>> + qup_uart3_tx: qup-uart3-tx {
>> + pins = "gpio14";
>> + function = "qup03";
>> + };
>> +
>> + qup_uart3_rx: qup-uart3-rx {
>> + pins = "gpio15";
>> + function = "qup03";
>> + };
>> +
>> + qup_uart4_cts: qup-uart4-cts {
>> + pins = "gpio16";
>> + function = "qup04";
>> + };
>> +
>> + qup_uart4_rts: qup-uart4-rts {
>> + pins = "gpio17";
>> + function = "qup04";
>> + };
>> +
>> + qup_uart4_tx: qup-uart4-tx {
>> + pins = "gpio18";
>> + function = "qup04";
>> + };
>> +
>> + qup_uart4_rx: qup-uart4-rx {
>> + pins = "gpio19";
>> + function = "qup04";
>> + };
>> +
>> qup_uart5_default: qup-uart5-default {
>> pins = "gpio46", "gpio47";
>> function = "qup13";
>> };
>
> Wait, why does uart5 use the pins of qup13? Is see this is
> 'fixed' by '[4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT
> node' but I'm still surprised ...
>
> Doesn't 'fixing' this break devices that are currently using
> 'uart5'? It seems those devices would need to change from
> 'uart5' to 'uart11'.
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-26 13:07 ` rajpat
@ 2021-08-26 19:51 ` Matthias Kaehlcke
2021-09-01 7:06 ` rajpat
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-08-26 19:51 UTC (permalink / raw)
To: rajpat
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On Thu, Aug 26, 2021 at 06:37:02PM +0530, rajpat@codeaurora.org wrote:
> On 2021-08-12 19:44, Matthias Kaehlcke wrote:
> > On Thu, Aug 12, 2021 at 01:11:14PM +0530, Rajesh Patil wrote:
> > > From: Roja Rani Yarubandi <rojay@codeaurora.org>
> > >
> > > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
> > >
> > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > > ---
> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 720
> > > +++++++++++++++++++++++++++++++++++
> > > 1 file changed, 720 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > index f8dd5ff..e461395 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > >
> > > ...
> > >
> > > + spi0: spi@980000 {
> > > + compatible = "qcom,geni-spi";
> > > + reg = <0 0x00980000 0 0x4000>;
> > > + clock-names = "se";
> > > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>,
> > > <&qup_spi0_cs_gpio>;
> >
> > What is the story behind 'qup_spiN_cs' and 'qup_spiN_cs_gpio'? Both
> > configure
> > the CS pin with a different function:
> >
>
> As per discussion here [1], we have split like this.
>
> [1] https://lore.kernel.org/patchwork/patch/1393353/#1591826
IIUC that's only about having separate configs for each pin, instead of
groups like 'qup-spi0-default'. What you are doing above with 'qup_spi0_cs'
and 'qup_spi0_cs_gpio' is to configure the same pin (GPIO 3) both as SPI
chip select and as GPIO. Which one is it?
I imagine we want to have both pinctrl definitions to allow a board to
configure the pin either as SPI CS or GPIO. However it should be only one
of the two at a time, and the SoC .dtsi should provide a reasonable
default, which probably is SPI CS.
Maybe I'm missing something, if so please provide details on why it is
necessary to have this config.
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-26 19:51 ` Matthias Kaehlcke
@ 2021-09-01 7:06 ` rajpat
0 siblings, 0 replies; 24+ messages in thread
From: rajpat @ 2021-09-01 7:06 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, dianders
On 2021-08-27 01:21, Matthias Kaehlcke wrote:
> On Thu, Aug 26, 2021 at 06:37:02PM +0530, rajpat@codeaurora.org wrote:
>> On 2021-08-12 19:44, Matthias Kaehlcke wrote:
>> > On Thu, Aug 12, 2021 at 01:11:14PM +0530, Rajesh Patil wrote:
>> > > From: Roja Rani Yarubandi <rojay@codeaurora.org>
>> > >
>> > > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>> > >
>> > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> > > ---
>> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 720
>> > > +++++++++++++++++++++++++++++++++++
>> > > 1 file changed, 720 insertions(+)
>> > >
>> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > index f8dd5ff..e461395 100644
>> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > >
>> > > ...
>> > >
>> > > + spi0: spi@980000 {
>> > > + compatible = "qcom,geni-spi";
>> > > + reg = <0 0x00980000 0 0x4000>;
>> > > + clock-names = "se";
>> > > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
>> > > + pinctrl-names = "default";
>> > > + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>,
>> > > <&qup_spi0_cs_gpio>;
>> >
>> > What is the story behind 'qup_spiN_cs' and 'qup_spiN_cs_gpio'? Both
>> > configure
>> > the CS pin with a different function:
>> >
>>
>> As per discussion here [1], we have split like this.
>>
>> [1] https://lore.kernel.org/patchwork/patch/1393353/#1591826
>
> IIUC that's only about having separate configs for each pin, instead of
> groups like 'qup-spi0-default'. What you are doing above with
> 'qup_spi0_cs'
> and 'qup_spi0_cs_gpio' is to configure the same pin (GPIO 3) both as
> SPI
> chip select and as GPIO. Which one is it?
>
> I imagine we want to have both pinctrl definitions to allow a board to
> configure the pin either as SPI CS or GPIO. However it should be only
> one
> of the two at a time, and the SoC .dtsi should provide a reasonable
> default, which probably is SPI CS.
>
I agree. Will remove it in next version.
> Maybe I'm missing something, if so please provide details on why it is
> necessary to have this config.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-12 7:41 ` [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
2021-08-12 14:14 ` Matthias Kaehlcke
@ 2021-08-19 0:04 ` Doug Anderson
2021-08-26 12:53 ` rajpat
1 sibling, 1 reply; 24+ messages in thread
From: Doug Anderson @ 2021-08-19 0:04 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
linux-arm-msm, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rajendra Nayak, Sai Prakash Ranjan, msavaliy, satya priya,
Roja Rani Yarubandi
Hi,
On Thu, Aug 12, 2021 at 12:42 AM Rajesh Patil <rajpat@codeaurora.org> wrote:
>
> @@ -542,8 +561,305 @@
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> + iommus = <&apps_smmu 0x123 0x0>;
> status = "disabled";
>
> + i2c0: i2c@980000 {
Not a full review of your patch (I think Matthias has already looked
in a bunch of detail), but can I also request that you add i2c and spi
aliases in your next spin (I think you have to spin this anyway,
right?) Add these under the "aliases" mode before the mmc ones (to
keep sort order good):
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
i2c12 = &i2c12;
i2c13 = &i2c13;
i2c14 = &i2c14;
i2c15 = &i2c15;
...and these after:
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &spi4;
spi5 = &spi5;
spi6 = &spi6;
spi7 = &spi7;
spi8 = &spi8;
spi9 = &spi9;
spi10 = &spi10;
spi11 = &spi11;
spi12 = &spi12;
spi13 = &spi13;
spi14 = &spi14;
spi15 = &spi15;
The "Quad SPI" doesn't get an alias, but that's OK. It doesn't have a
well-defined number in the manual and it's fine to have it be
auto-assigned. It's really just confusing when there's something with
a well-defined number in the manual and it's a _different_ one in the
logs. ;-)
-Doug
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-19 0:04 ` Doug Anderson
@ 2021-08-26 12:53 ` rajpat
0 siblings, 0 replies; 24+ messages in thread
From: rajpat @ 2021-08-26 12:53 UTC (permalink / raw)
To: Doug Anderson
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
linux-arm-msm, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rajendra Nayak, Sai Prakash Ranjan, msavaliy, satya priya,
Roja Rani Yarubandi
On 2021-08-19 05:34, Doug Anderson wrote:
> Hi,
>
> On Thu, Aug 12, 2021 at 12:42 AM Rajesh Patil <rajpat@codeaurora.org>
> wrote:
>>
>> @@ -542,8 +561,305 @@
>> #address-cells = <2>;
>> #size-cells = <2>;
>> ranges;
>> + iommus = <&apps_smmu 0x123 0x0>;
>> status = "disabled";
>>
>> + i2c0: i2c@980000 {
>
> Not a full review of your patch (I think Matthias has already looked
> in a bunch of detail), but can I also request that you add i2c and spi
> aliases in your next spin (I think you have to spin this anyway,
> right?) Add these under the "aliases" mode before the mmc ones (to
> keep sort order good):
>
ok I will add them.
Thanks
Rajesh
> i2c0 = &i2c0;
> i2c1 = &i2c1;
> i2c2 = &i2c2;
> i2c3 = &i2c3;
> i2c4 = &i2c4;
> i2c5 = &i2c5;
> i2c6 = &i2c6;
> i2c7 = &i2c7;
> i2c8 = &i2c8;
> i2c9 = &i2c9;
> i2c10 = &i2c10;
> i2c11 = &i2c11;
> i2c12 = &i2c12;
> i2c13 = &i2c13;
> i2c14 = &i2c14;
> i2c15 = &i2c15;
>
> ...and these after:
>
> spi0 = &spi0;
> spi1 = &spi1;
> spi2 = &spi2;
> spi3 = &spi3;
> spi4 = &spi4;
> spi5 = &spi5;
> spi6 = &spi6;
> spi7 = &spi7;
> spi8 = &spi8;
> spi9 = &spi9;
> spi10 = &spi10;
> spi11 = &spi11;
> spi12 = &spi12;
> spi13 = &spi13;
> spi14 = &spi14;
> spi15 = &spi15;
>
> The "Quad SPI" doesn't get an alias, but that's OK. It doesn't have a
> well-defined number in the manual and it's fine to have it be
> auto-assigned. It's really just confusing when there's something with
> a well-defined number in the manual and it's a _different_ one in the
> logs. ;-)
>
> -Doug
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node
2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (2 preceding siblings ...)
2021-08-12 7:41 ` [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
@ 2021-08-12 7:41 ` Rajesh Patil
2021-08-12 15:46 ` Matthias Kaehlcke
2021-08-12 7:41 ` [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp Rajesh Patil
` (2 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Rajesh Patil @ 2021-08-12 7:41 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: swboyd, linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Update the compatible string as "qcom,geni-uart".
Add interconnects and power-domains. Split the pinctrl
functions and correct the gpio pins.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 30 +++++++++++++++++++++++++-----
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e461395..2dc7e8c 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -861,13 +861,18 @@
};
uart5: serial@994000 {
- compatible = "qcom,geni-debug-uart";
+ compatible = "qcom,geni-uart";
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -2255,9 +2260,24 @@
function = "qup04";
};
- qup_uart5_default: qup-uart5-default {
- pins = "gpio46", "gpio47";
- function = "qup13";
+ qup_uart5_cts: qup-uart5-cts {
+ pins = "gpio20";
+ function = "qup05";
+ };
+
+ qup_uart5_rts: qup-uart5-rts {
+ pins = "gpio21";
+ function = "qup05";
+ };
+
+ qup_uart5_tx: qup-uart5-tx {
+ pins = "gpio22";
+ function = "qup05";
+ };
+
+ qup_uart5_rx: qup-uart5-rx {
+ pins = "gpio23";
+ function = "qup05";
};
qup_uart6_cts: qup-uart6-cts {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node
2021-08-12 7:41 ` [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node Rajesh Patil
@ 2021-08-12 15:46 ` Matthias Kaehlcke
0 siblings, 0 replies; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-08-12 15:46 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On Thu, Aug 12, 2021 at 01:11:15PM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>
> Update the compatible string as "qcom,geni-uart".
> Add interconnects and power-domains. Split the pinctrl
> functions and correct the gpio pins.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 30 +++++++++++++++++++++++++-----
> 1 file changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e461395..2dc7e8c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -861,13 +861,18 @@
> };
>
> uart5: serial@994000 {
> - compatible = "qcom,geni-debug-uart";
> + compatible = "qcom,geni-uart";
> reg = <0 0x00994000 0 0x4000>;
> clock-names = "se";
> clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> pinctrl-names = "default";
> - pinctrl-0 = <&qup_uart5_default>;
> + pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> status = "disabled";
> };
>
> @@ -2255,9 +2260,24 @@
> function = "qup04";
> };
>
> - qup_uart5_default: qup-uart5-default {
> - pins = "gpio46", "gpio47";
> - function = "qup13";
sc7280-idp.dtsi references this node, so if this patch is applied the SC7280
IDP DT would be broken, unless "[5/7] arm64: dts: sc7280: Configure debug
uart for sc7280-idp" is also applied. I think you need to squash the two
patches.
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp
2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (3 preceding siblings ...)
2021-08-12 7:41 ` [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node Rajesh Patil
@ 2021-08-12 7:41 ` Rajesh Patil
2021-08-12 16:05 ` Matthias Kaehlcke
2021-08-12 7:41 ` [PATCH V5 6/7] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil
2021-08-12 7:41 ` [PATCH V5 7/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
6 siblings, 1 reply; 24+ messages in thread
From: Rajesh Patil @ 2021-08-12 7:41 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: swboyd, linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Rajesh Patil
Configure uart5 as debug uart and split the pinctrl functions
to match with SoC dt.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index c41c2d0..53993b3 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -254,6 +254,7 @@
};
&uart5 {
+ compatible = "qcom,geni-debug-uart";
status = "okay";
};
@@ -311,18 +312,14 @@
bias-pull-up;
};
-&qup_uart5_default {
- tx {
- pins = "gpio46";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
- rx {
- pins = "gpio47";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-pull-up;
};
&sdc1_on {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp
2021-08-12 7:41 ` [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp Rajesh Patil
@ 2021-08-12 16:05 ` Matthias Kaehlcke
2021-08-26 13:07 ` rajpat
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-08-12 16:05 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On Thu, Aug 12, 2021 at 01:11:16PM +0530, Rajesh Patil wrote:
> Configure uart5 as debug uart and split the pinctrl functions
> to match with SoC dt.
>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
As I mentioned on '[4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node',
I think you need to squash the two patches to avoid breaking (temporarily)
the SC7280 IDP DT due to the undefined node 'qup_uart5_default'
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp
2021-08-12 16:05 ` Matthias Kaehlcke
@ 2021-08-26 13:07 ` rajpat
0 siblings, 0 replies; 24+ messages in thread
From: rajpat @ 2021-08-26 13:07 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On 2021-08-12 21:35, Matthias Kaehlcke wrote:
> On Thu, Aug 12, 2021 at 01:11:16PM +0530, Rajesh Patil wrote:
>> Configure uart5 as debug uart and split the pinctrl functions
>> to match with SoC dt.
>>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>
> As I mentioned on '[4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT
> node',
> I think you need to squash the two patches to avoid breaking
> (temporarily)
> the SC7280 IDP DT due to the undefined node 'qup_uart5_default'
Okay
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH V5 6/7] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp
2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (4 preceding siblings ...)
2021-08-12 7:41 ` [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp Rajesh Patil
@ 2021-08-12 7:41 ` Rajesh Patil
2021-08-12 19:22 ` Matthias Kaehlcke
2021-08-12 7:41 ` [PATCH V5 7/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
6 siblings, 1 reply; 24+ messages in thread
From: Rajesh Patil @ 2021-08-12 7:41 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: swboyd, linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Rajesh Patil
Add bluetooth uart pin configuration for sc7280-idp.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 85 ++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 53993b3..7c106c0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -297,6 +297,16 @@
vdda18-supply = <&vreg_l1c_1p8>;
};
+&uart7 {
+ status = "okay";
+
+ /delete-property/interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
+};
+
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
&qspi_cs0 {
@@ -322,6 +332,81 @@
bias-pull-up;
};
+&qup_uart7_cts {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+};
+
+&qup_uart7_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
+};
+
+&tlmm {
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
+ };
+
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ bias-pull-up;
+ };
+};
+
&sdc1_on {
clk {
bias-disable;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH V5 6/7] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp
2021-08-12 7:41 ` [PATCH V5 6/7] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil
@ 2021-08-12 19:22 ` Matthias Kaehlcke
0 siblings, 0 replies; 24+ messages in thread
From: Matthias Kaehlcke @ 2021-08-12 19:22 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, swboyd, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On Thu, Aug 12, 2021 at 01:11:17PM +0530, Rajesh Patil wrote:
> Add bluetooth uart pin configuration for sc7280-idp.
>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH V5 7/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (5 preceding siblings ...)
2021-08-12 7:41 ` [PATCH V5 6/7] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil
@ 2021-08-12 7:41 ` Rajesh Patil
6 siblings, 0 replies; 24+ messages in thread
From: Rajesh Patil @ 2021-08-12 7:41 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: swboyd, linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QUPv3 wrapper_1 DT nodes for SC7280 SoC.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 749 +++++++++++++++++++++++++++++++
2 files changed, 753 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 7c106c0..65126a7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -225,6 +225,10 @@
status = "okay";
};
+&qupv3_id_1 {
+ status = "okay";
+};
+
&sdhc_1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2dc7e8c..e29af91 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -981,6 +981,435 @@
};
};
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ iommus = <&apps_smmu 0x43 0x0>;
+ status = "disabled";
+
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi8: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>, <&qup_spi8_cs_gpio>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart8: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>, <&qup_spi9_cs_gpio>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart9: serial@a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>, <&qup_spi10_cs_gpio>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart10: serial@a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>, <&qup_spi11_cs_gpio>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart11: serial@a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>, <&qup_spi12_cs_gpio>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart12: serial@a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>, <&qup_spi13_cs_gpio>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart13: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>, <&qup_spi14_cs_gpio>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart14: serial@a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>, <&qup_spi15_cs_gpio>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart15: serial@a9c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+ };
+
cnoc2: interconnect@1500000 {
reg = <0 0x01500000 0 0x1000>;
compatible = "qcom,sc7280-cnoc2";
@@ -2040,6 +2469,46 @@
function = "qup07";
};
+ qup_i2c8_data_clk:qup-i2c8-data-clk {
+ pins = "gpio32", "gpio33";
+ function = "qup10";
+ };
+
+ qup_i2c9_data_clk:qup-i2c9-data-clk {
+ pins = "gpio36", "gpio37";
+ function = "qup11";
+ };
+
+ qup_i2c10_data_clk:qup-i2c10-data-clk {
+ pins = "gpio40", "gpio41";
+ function = "qup12";
+ };
+
+ qup_i2c11_data_clk:qup-i2c11-data-clk {
+ pins = "gpio44", "gpio45";
+ function = "qup13";
+ };
+
+ qup_i2c12_data_clk:qup-i2c12-data-clk {
+ pins = "gpio48", "gpio49";
+ function = "qup14";
+ };
+
+ qup_i2c13_data_clk:qup-i2c13-data-clk {
+ pins = "gpio52", "gpio53";
+ function = "qup15";
+ };
+
+ qup_i2c14_data_clk:qup-i2c14-data-clk {
+ pins = "gpio56", "gpio57";
+ function = "qup16";
+ };
+
+ qup_i2c15_data_clk:qup-i2c15-data-clk {
+ pins = "gpio60", "gpio61";
+ function = "qup17";
+ };
+
qup_spi0_data_clk: qup-spi0-data-clk {
pins = "gpio0", "gpio1", "gpio2";
function = "qup00";
@@ -2160,6 +2629,126 @@
function = "gpio";
};
+ qup_spi8_data_clk: qup-spi8-data-clk {
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup10";
+ };
+
+ qup_spi8_cs: qup-spi8-cs {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_spi8_cs_gpio: qup-spi8-cs_gpio {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk {
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup11";
+ };
+
+ qup_spi9_cs: qup-spi9-cs {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_spi9_cs_gpio: qup-spi9-cs_gpio {
+ pins = "gpio39";
+ function = "gpio";
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk {
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup12";
+ };
+
+ qup_spi10_cs: qup-spi10-cs {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_spi10_cs_gpio: qup-spi10-cs_gpio {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk {
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup13";
+ };
+
+ qup_spi11_cs: qup-spi11-cs {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs_gpio {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk {
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup14";
+ };
+
+ qup_spi12_cs: qup-spi12-cs {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_spi12_cs_gpio: qup-spi12-cs_gpio {
+ pins = "gpio51";
+ function = "gpio";
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk {
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup15";
+ };
+
+ qup_spi13_cs: qup-spi13-cs {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_spi13_cs_gpio: qup-spi13-cs_gpio {
+ pins = "gpio55";
+ function = "gpio";
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk {
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup16";
+ };
+
+ qup_spi14_cs: qup-spi14-cs {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ qup_spi14_cs_gpio: qup-spi14-cs_gpio {
+ pins = "gpio59";
+ function = "gpio";
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk {
+ pins = "gpio60", "gpio61", "gpio62";
+ function = "qup17";
+ };
+
+ qup_spi15_cs: qup-spi15-cs {
+ pins = "gpio63";
+ function = "qup17";
+ };
+
+ qup_spi15_cs_gpio: qup-spi15-cs_gpio {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
qup_uart0_cts: qup-uart0-cts {
pins = "gpio0";
function = "qup00";
@@ -2400,6 +2989,166 @@
bias-bus-hold;
};
};
+
+ qup_uart8_cts: qup-uart8-cts {
+ pins = "gpio32";
+ function = "qup10";
+ };
+
+ qup_uart8_rts: qup-uart8-rts {
+ pins = "gpio33";
+ function = "qup10";
+ };
+
+ qup_uart8_tx: qup-uart8-tx {
+ pins = "gpio34";
+ function = "qup10";
+ };
+
+ qup_uart8_rx: qup-uart8-rx {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_uart9_cts: qup-uart9-cts {
+ pins = "gpio36";
+ function = "qup11";
+ };
+
+ qup_uart9_rts: qup-uart9-rts {
+ pins = "gpio37";
+ function = "qup11";
+ };
+
+ qup_uart9_tx: qup-uart9-tx {
+ pins = "gpio38";
+ function = "qup11";
+ };
+
+ qup_uart9_rx: qup-uart9-rx {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_uart10_cts: qup-uart10-cts {
+ pins = "gpio40";
+ function = "qup12";
+ };
+
+ qup_uart10_rts: qup-uart10-rts {
+ pins = "gpio41";
+ function = "qup12";
+ };
+
+ qup_uart10_tx: qup-uart10-tx {
+ pins = "gpio42";
+ function = "qup12";
+ };
+
+ qup_uart10_rx: qup-uart10-rx {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_uart11_cts: qup-uart11-cts {
+ pins = "gpio44";
+ function = "qup13";
+ };
+
+ qup_uart11_rts: qup-uart11-rts {
+ pins = "gpio45";
+ function = "qup13";
+ };
+
+ qup_uart11_tx: qup-uart11-tx {
+ pins = "gpio46";
+ function = "qup13";
+ };
+
+ qup_uart11_rx: qup-uart11-rx {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_uart12_cts: qup-uart12-cts {
+ pins = "gpio48";
+ function = "qup14";
+ };
+
+ qup_uart12_rts: qup-uart12-rts {
+ pins = "gpio49";
+ function = "qup14";
+ };
+
+ qup_uart12_tx: qup-uart12-tx {
+ pins = "gpio50";
+ function = "qup14";
+ };
+
+ qup_uart12_rx: qup-uart12-rx {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_uart13_cts: qup-uart13-cts {
+ pins = "gpio52";
+ function = "qup15";
+ };
+
+ qup_uart13_rts: qup-uart13-rts {
+ pins = "gpio53";
+ function = "qup15";
+ };
+
+ qup_uart13_tx: qup-uart13-tx {
+ pins = "gpio54";
+ function = "qup15";
+ };
+
+ qup_uart13_rx: qup-uart13-rx {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_uart14_cts: qup-uart14-cts {
+ pins = "gpio56";
+ function = "qup16";
+ };
+
+ qup_uart14_rts: qup-uart14-rts {
+ pins = "gpio57";
+ function = "qup16";
+ };
+
+ qup_uart14_tx: qup-uart14-tx {
+ pins = "gpio58";
+ function = "qup16";
+ };
+
+ qup_uart14_rx: qup-uart14-rx {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ qup_uart15_cts: qup-uart15-cts {
+ pins = "gpio60";
+ function = "qup17";
+ };
+
+ qup_uart15_rts: qup-uart15-rts {
+ pins = "gpio61";
+ function = "qup17";
+ };
+
+ qup_uart15_tx: qup-uart15-tx {
+ pins = "gpio62";
+ function = "qup17";
+ };
+
+ qup_uart15_rx: qup-uart15-rx {
+ pins = "gpio63";
+ function = "qup17";
+ };
};
apps_smmu: iommu@15000000 {
--
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