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From: Rob Herring <robh@kernel.org>
To: Bharat Bhushan <bbhushan2@marvell.com>
Cc: will@kernel.org, mark.rutland@arm.com,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor
Date: Tue, 17 Aug 2021 15:27:41 -0500	[thread overview]
Message-ID: <YRwbvfCYl94UDseY@robh.at.kernel.org> (raw)
In-Reply-To: <20210810094307.29595-2-bbhushan2@marvell.com>

On Tue, Aug 10, 2021 at 03:13:04PM +0530, Bharat Bhushan wrote:
> Add binding documentation for the Marvell CN10k DDR
> performance monitor unit.
> 
> Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
> ---
> v1->v2:
>  - DT binding changed to new DT Schema
> 
>  .../bindings/perf/marvell-cn10k-ddr.yaml      | 37 +++++++++++++++++++
>  1 file changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> 
> diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> new file mode 100644
> index 000000000000..2a335444cf53
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> @@ -0,0 +1,37 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Marvell CN10K DDR performance monitor
> +
> +maintainers:
> +  - Bharat Bhushan <bbhushan2@marvell.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - marvell,cn10k-ddr-pmu
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    bus {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        ddrcpmu@1 {

pmu@87e1c0000000

> +            compatible = "marvell,cn10k-ddr-pmu";
> +            reg = <0x87e1 0xc0000000 0x0 0x10000>;
> +        };
> +    };
> -- 
> 2.17.1
> 
> 

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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Bharat Bhushan <bbhushan2@marvell.com>
Cc: will@kernel.org, mark.rutland@arm.com,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor
Date: Tue, 17 Aug 2021 15:27:41 -0500	[thread overview]
Message-ID: <YRwbvfCYl94UDseY@robh.at.kernel.org> (raw)
In-Reply-To: <20210810094307.29595-2-bbhushan2@marvell.com>

On Tue, Aug 10, 2021 at 03:13:04PM +0530, Bharat Bhushan wrote:
> Add binding documentation for the Marvell CN10k DDR
> performance monitor unit.
> 
> Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
> ---
> v1->v2:
>  - DT binding changed to new DT Schema
> 
>  .../bindings/perf/marvell-cn10k-ddr.yaml      | 37 +++++++++++++++++++
>  1 file changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> 
> diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> new file mode 100644
> index 000000000000..2a335444cf53
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> @@ -0,0 +1,37 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Marvell CN10K DDR performance monitor
> +
> +maintainers:
> +  - Bharat Bhushan <bbhushan2@marvell.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - marvell,cn10k-ddr-pmu
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    bus {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        ddrcpmu@1 {

pmu@87e1c0000000

> +            compatible = "marvell,cn10k-ddr-pmu";
> +            reg = <0x87e1 0xc0000000 0x0 0x10000>;
> +        };
> +    };
> -- 
> 2.17.1
> 
> 

  reply	other threads:[~2021-08-17 20:29 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-10  9:43 [PATCH v2 0/4] cn10k DDR Performance monitor support Bharat Bhushan
2021-08-10  9:43 ` Bharat Bhushan
2021-08-10  9:43 ` [PATCH v2 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor Bharat Bhushan
2021-08-10  9:43   ` Bharat Bhushan
2021-08-17 20:27   ` Rob Herring [this message]
2021-08-17 20:27     ` Rob Herring
2021-08-10  9:43 ` [PATCH v2 2/4] perf/marvell: CN10k DDR performance monitor support Bharat Bhushan
2021-08-10  9:43   ` Bharat Bhushan
2021-08-18 12:27   ` kajoljain
2021-08-18 12:27     ` kajoljain
2021-08-19 11:52     ` [EXT] " Bharat Bhushan
2021-08-19 11:52       ` Bharat Bhushan
2021-08-18 13:49   ` John Garry
2021-08-18 13:49     ` John Garry
2021-08-19 11:52     ` [EXT] " Bharat Bhushan
2021-08-19 11:52       ` Bharat Bhushan
2021-08-19 13:10       ` John Garry
2021-08-19 13:10         ` John Garry
2021-08-10  9:43 ` [PATCH v2 3/4] perf/marvell: cn10k DDR perfmon event overflow handling Bharat Bhushan
2021-08-10  9:43   ` Bharat Bhushan
2021-08-10  9:43 ` [PATCH v2 4/4] perf/marvell: cn10k DDR perf event core ownership Bharat Bhushan
2021-08-10  9:43   ` Bharat Bhushan

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