From: Abel Vesa <abel.vesa@nxp.com>
To: Marek Vasut <marex@denx.de>
Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,
Shawn Guo <shawnguo@kernel.org>
Subject: Re: [PATCH] clk: imx8mn: Add M7 core clock
Date: Tue, 24 Aug 2021 15:14:01 +0300 [thread overview]
Message-ID: <YSTiid0DyCebErn0@ryzen> (raw)
In-Reply-To: <20210819202036.2084782-1-marex@denx.de>
On 21-08-19 22:20:36, Marek Vasut wrote:
> Add missing M7 core clock entry to the iMX8MN clock driver.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
I'm OK with it.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mn.c | 5 +++++
> include/dt-bindings/clock/imx8mn-clock.h | 4 +++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 212708e9388e2..9dba4eb643ab9 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -40,6 +40,9 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
>
> static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
>
> +static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "vpu_pll_out",
> + "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
> +
> static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
> "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
> "video_pll1_out", "audio_pll2_out", };
> @@ -421,6 +424,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
> hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
> hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
>
> + hws[IMX8MN_CLK_M7_CORE] = imx8m_clk_hw_composite_core("arm_m7_core", imx8mn_m7_sels, base + 0x8080);
> +
> hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
> hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
>
> diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
> index d24b627cb2e71..01e8bab1d767a 100644
> --- a/include/dt-bindings/clock/imx8mn-clock.h
> +++ b/include/dt-bindings/clock/imx8mn-clock.h
> @@ -241,6 +241,8 @@
> #define IMX8MN_CLK_CLKOUT2_DIV 219
> #define IMX8MN_CLK_CLKOUT2 220
>
> -#define IMX8MN_CLK_END 221
> +#define IMX8MN_CLK_M7_CORE 221
> +
> +#define IMX8MN_CLK_END 222
>
> #endif
> --
> 2.30.2
>
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@nxp.com>
To: Marek Vasut <marex@denx.de>
Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,
Shawn Guo <shawnguo@kernel.org>
Subject: Re: [PATCH] clk: imx8mn: Add M7 core clock
Date: Tue, 24 Aug 2021 15:14:01 +0300 [thread overview]
Message-ID: <YSTiid0DyCebErn0@ryzen> (raw)
In-Reply-To: <20210819202036.2084782-1-marex@denx.de>
On 21-08-19 22:20:36, Marek Vasut wrote:
> Add missing M7 core clock entry to the iMX8MN clock driver.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
I'm OK with it.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mn.c | 5 +++++
> include/dt-bindings/clock/imx8mn-clock.h | 4 +++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 212708e9388e2..9dba4eb643ab9 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -40,6 +40,9 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
>
> static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
>
> +static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "vpu_pll_out",
> + "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
> +
> static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
> "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
> "video_pll1_out", "audio_pll2_out", };
> @@ -421,6 +424,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
> hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
> hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
>
> + hws[IMX8MN_CLK_M7_CORE] = imx8m_clk_hw_composite_core("arm_m7_core", imx8mn_m7_sels, base + 0x8080);
> +
> hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
> hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
>
> diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
> index d24b627cb2e71..01e8bab1d767a 100644
> --- a/include/dt-bindings/clock/imx8mn-clock.h
> +++ b/include/dt-bindings/clock/imx8mn-clock.h
> @@ -241,6 +241,8 @@
> #define IMX8MN_CLK_CLKOUT2_DIV 219
> #define IMX8MN_CLK_CLKOUT2 220
>
> -#define IMX8MN_CLK_END 221
> +#define IMX8MN_CLK_M7_CORE 221
> +
> +#define IMX8MN_CLK_END 222
>
> #endif
> --
> 2.30.2
>
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next prev parent reply other threads:[~2021-08-24 12:14 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-19 20:20 [PATCH] clk: imx8mn: Add M7 core clock Marek Vasut
2021-08-19 20:20 ` Marek Vasut
2021-08-24 12:14 ` Abel Vesa [this message]
2021-08-24 12:14 ` Abel Vesa
2021-08-24 12:28 ` Fabio Estevam
2021-08-24 12:28 ` Fabio Estevam
2021-08-24 13:05 ` Abel Vesa
2021-08-24 13:05 ` Abel Vesa
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