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From: Catalin Marinas <catalin.marinas@arm.com>
To: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Cc: mark.rutland@arm.com, will@kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, moyufeng@huawei.com
Subject: Re: [RFC PATCH v2] arm64: barrier: add macro dgh() to control memory accesses merging
Date: Fri, 15 Oct 2021 18:59:58 +0100	[thread overview]
Message-ID: <YWnBngJeIvV2S5IB@arm.com> (raw)
In-Reply-To: <20211015090511.92421-1-wangxiongfeng2@huawei.com>

On Fri, Oct 15, 2021 at 05:05:11PM +0800, Xiongfeng Wang wrote:
> diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
> index 451e11e5fd23..d71a7457d619 100644
> --- a/arch/arm64/include/asm/barrier.h
> +++ b/arch/arm64/include/asm/barrier.h
> @@ -18,6 +18,14 @@
>  #define wfe()		asm volatile("wfe" : : : "memory")
>  #define wfi()		asm volatile("wfi" : : : "memory")
>  
> +/*
> + * Data Gathering Hint:
> + * This instruction prohibits merging memory accesses with Normal-NC or
> + * Device-GRE attributes before the hint instruction with any memory accesses
> + * appearing after the hint instruction.
> + */
> +#define dgh()		asm volatile("hint #6" : : : "memory")

On its own, this patch doesn't do anything. It's more interesting to see
how it will be used and maybe come up with a common name that other
architectures would share (or just implement as no-opp). I'm not sure
there was any conclusion last time we discussed this.

-- 
Catalin

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Cc: mark.rutland@arm.com, will@kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, moyufeng@huawei.com
Subject: Re: [RFC PATCH v2] arm64: barrier: add macro dgh() to control memory accesses merging
Date: Fri, 15 Oct 2021 18:59:58 +0100	[thread overview]
Message-ID: <YWnBngJeIvV2S5IB@arm.com> (raw)
In-Reply-To: <20211015090511.92421-1-wangxiongfeng2@huawei.com>

On Fri, Oct 15, 2021 at 05:05:11PM +0800, Xiongfeng Wang wrote:
> diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
> index 451e11e5fd23..d71a7457d619 100644
> --- a/arch/arm64/include/asm/barrier.h
> +++ b/arch/arm64/include/asm/barrier.h
> @@ -18,6 +18,14 @@
>  #define wfe()		asm volatile("wfe" : : : "memory")
>  #define wfi()		asm volatile("wfi" : : : "memory")
>  
> +/*
> + * Data Gathering Hint:
> + * This instruction prohibits merging memory accesses with Normal-NC or
> + * Device-GRE attributes before the hint instruction with any memory accesses
> + * appearing after the hint instruction.
> + */
> +#define dgh()		asm volatile("hint #6" : : : "memory")

On its own, this patch doesn't do anything. It's more interesting to see
how it will be used and maybe come up with a common name that other
architectures would share (or just implement as no-opp). I'm not sure
there was any conclusion last time we discussed this.

-- 
Catalin

  reply	other threads:[~2021-10-15 18:01 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-15  9:05 [RFC PATCH v2] arm64: barrier: add macro dgh() to control memory accesses merging Xiongfeng Wang
2021-10-15  9:05 ` Xiongfeng Wang
2021-10-15 17:59 ` Catalin Marinas [this message]
2021-10-15 17:59   ` Catalin Marinas
2021-10-22  1:51   ` Xiongfeng Wang
2021-10-22  1:51     ` Xiongfeng Wang
2021-12-03 12:47     ` Catalin Marinas
2021-12-03 12:47       ` Catalin Marinas
2021-12-14 10:46       ` Will Deacon
2021-12-14 10:46         ` Will Deacon
2021-12-14 11:20         ` Catalin Marinas
2021-12-14 11:20           ` Catalin Marinas

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