* [Intel-gfx] [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
@ 2021-10-24 15:50 ` Hans de Goede
0 siblings, 0 replies; 15+ messages in thread
From: Hans de Goede @ 2021-10-24 15:50 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä
Cc: Hans de Goede, intel-gfx, dri-devel, Tsuchiya Yuto
Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
Trail tablet. It deviates from the typical reference design based tablets
in many ways.
The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
as part of its unusual design it also has some supply rail which is only
used for DisplayPort or HDMI not connected.
Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
appears to cause the P-Unit to hang. When booting with a serial-usb console
the following errors are logged before the system freezes:
i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
------------[ cut here ]------------
i915 0000:00:02.0: DPIO read pipe A reg 0x8170 == 0xffffffff
WARNING: CPU: 3 PID: 258 at drivers/gpu/drm/i915/intel_sideband.c:257 vlv_dpio_read+0x95/0xb0 [i915]
...
Call Trace:
chv_dpio_cmn_power_well_enable+0xab/0x210 [i915]
__intel_display_power_get_domain.part.0+0xa0/0xc0 [i915]
intel_power_domains_init_hw+0x26d/0x760 [i915]
intel_modeset_init_noirq+0x5d/0x270 [i915]
i915_driver_probe+0x6b6/0xd10 [i915]
...
If I disable the WARN about the register being 0xffffffff, so that the
system can log some more dmesg output over the serial console before
freezing, the following errors are also logged:
i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fcfff3ff)
i915 0000:00:02.0: [drm] *ERROR* Display PHY 1 is not power up
With this patch to disable the force-enabling of the PHY 0 / dpio-common-bc
powerwell in place, this error for PHY 1 goes away. So it seems that trying
the force-enabling of the PHY 0 / dpio-common-bc powerwell freezes the
P-Unit, causing the subsequent enabling of PHY 1 to also fail (and causing
the entire system to freeze within seconds).
With this patch the PHY 1 error disappears and the entire system works.
Note this change also moves the intel_init_quirks() call a bit up inside
intel_modeset_init_noirq() this is necessary so that the quirk is set
before the intel_power_domains_init_hw() call. This is harmless, all that
intel_init_quirks() does is set some bits in drm_i915_private.quirks and
make some drm_info() log calls.
Reported-by: Tsuchiya Yuto <kitakar@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
.../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++++++++--
drivers/gpu/drm/i915/display/intel_quirks.c | 10 ++++++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 015854b5078c..1fb885cc86c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12467,6 +12467,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_bios;
+ intel_init_quirks(i915);
+
/* FIXME: completely on the wrong abstraction layer */
intel_power_domains_init_hw(i915, false);
@@ -12501,8 +12503,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
INIT_WORK(&i915->atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
- intel_init_quirks(i915);
-
intel_fbc_init(i915);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cce1a926fcc1..eeaba3dc064b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2090,8 +2090,14 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
if (intel_display_power_grab_async_put_ref(dev_priv, domain))
return;
- for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) {
+ if (domain == POWER_DOMAIN_INIT &&
+ (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
+ power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
+ continue;
+
intel_power_well_get(dev_priv, power_well);
+ }
power_domains->domain_use_count[domain]++;
}
@@ -2184,8 +2190,14 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
power_domains->domain_use_count[domain]--;
- for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
+ if (domain == POWER_DOMAIN_INIT &&
+ (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
+ power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
+ continue;
+
intel_power_well_put(dev_priv, power_well);
+ }
}
static void __intel_display_power_put(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index 8a52b7a16774..c377f515bbf4 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -59,6 +59,13 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
}
+/* The Xiaomi Mi Pad 2 CHT tablet hangs on enabling the dpio-common-bc well */
+static void quirk_no_vlv_disp_pw_dpio_cmn_bc_init(struct drm_i915_private *i915)
+{
+ i915->quirks |= QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT;
+ drm_info(&i915->drm, "Applying no dpio-common-bc powerwell init quirk\n");
+}
+
struct intel_quirk {
int device;
int subsystem_vendor;
@@ -190,6 +197,9 @@ static struct intel_quirk intel_quirks[] = {
/* ASRock ITX*/
{ 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
{ 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+
+ /* Xiaomi Mi Pad 2 */
+ { 0x22b0, 0x1d72, 0x1502, quirk_no_vlv_disp_pw_dpio_cmn_bc_init },
};
void intel_init_quirks(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 005b1cec7007..b907b49b4f0e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -524,6 +524,7 @@ struct i915_drrs {
#define QUIRK_INCREASE_T12_DELAY (1<<6)
#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
#define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
+#define QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT (1<<9)
struct intel_fbdev;
struct intel_fbc_work;
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
@ 2021-10-24 15:50 ` Hans de Goede
0 siblings, 0 replies; 15+ messages in thread
From: Hans de Goede @ 2021-10-24 15:50 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä
Cc: Hans de Goede, intel-gfx, dri-devel, Tsuchiya Yuto
Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
Trail tablet. It deviates from the typical reference design based tablets
in many ways.
The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
as part of its unusual design it also has some supply rail which is only
used for DisplayPort or HDMI not connected.
Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
appears to cause the P-Unit to hang. When booting with a serial-usb console
the following errors are logged before the system freezes:
i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
------------[ cut here ]------------
i915 0000:00:02.0: DPIO read pipe A reg 0x8170 == 0xffffffff
WARNING: CPU: 3 PID: 258 at drivers/gpu/drm/i915/intel_sideband.c:257 vlv_dpio_read+0x95/0xb0 [i915]
...
Call Trace:
chv_dpio_cmn_power_well_enable+0xab/0x210 [i915]
__intel_display_power_get_domain.part.0+0xa0/0xc0 [i915]
intel_power_domains_init_hw+0x26d/0x760 [i915]
intel_modeset_init_noirq+0x5d/0x270 [i915]
i915_driver_probe+0x6b6/0xd10 [i915]
...
If I disable the WARN about the register being 0xffffffff, so that the
system can log some more dmesg output over the serial console before
freezing, the following errors are also logged:
i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fcfff3ff)
i915 0000:00:02.0: [drm] *ERROR* Display PHY 1 is not power up
With this patch to disable the force-enabling of the PHY 0 / dpio-common-bc
powerwell in place, this error for PHY 1 goes away. So it seems that trying
the force-enabling of the PHY 0 / dpio-common-bc powerwell freezes the
P-Unit, causing the subsequent enabling of PHY 1 to also fail (and causing
the entire system to freeze within seconds).
With this patch the PHY 1 error disappears and the entire system works.
Note this change also moves the intel_init_quirks() call a bit up inside
intel_modeset_init_noirq() this is necessary so that the quirk is set
before the intel_power_domains_init_hw() call. This is harmless, all that
intel_init_quirks() does is set some bits in drm_i915_private.quirks and
make some drm_info() log calls.
Reported-by: Tsuchiya Yuto <kitakar@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
.../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++++++++--
drivers/gpu/drm/i915/display/intel_quirks.c | 10 ++++++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 015854b5078c..1fb885cc86c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12467,6 +12467,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_bios;
+ intel_init_quirks(i915);
+
/* FIXME: completely on the wrong abstraction layer */
intel_power_domains_init_hw(i915, false);
@@ -12501,8 +12503,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
INIT_WORK(&i915->atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
- intel_init_quirks(i915);
-
intel_fbc_init(i915);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cce1a926fcc1..eeaba3dc064b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2090,8 +2090,14 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
if (intel_display_power_grab_async_put_ref(dev_priv, domain))
return;
- for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) {
+ if (domain == POWER_DOMAIN_INIT &&
+ (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
+ power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
+ continue;
+
intel_power_well_get(dev_priv, power_well);
+ }
power_domains->domain_use_count[domain]++;
}
@@ -2184,8 +2190,14 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
power_domains->domain_use_count[domain]--;
- for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
+ if (domain == POWER_DOMAIN_INIT &&
+ (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
+ power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
+ continue;
+
intel_power_well_put(dev_priv, power_well);
+ }
}
static void __intel_display_power_put(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index 8a52b7a16774..c377f515bbf4 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -59,6 +59,13 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
}
+/* The Xiaomi Mi Pad 2 CHT tablet hangs on enabling the dpio-common-bc well */
+static void quirk_no_vlv_disp_pw_dpio_cmn_bc_init(struct drm_i915_private *i915)
+{
+ i915->quirks |= QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT;
+ drm_info(&i915->drm, "Applying no dpio-common-bc powerwell init quirk\n");
+}
+
struct intel_quirk {
int device;
int subsystem_vendor;
@@ -190,6 +197,9 @@ static struct intel_quirk intel_quirks[] = {
/* ASRock ITX*/
{ 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
{ 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+
+ /* Xiaomi Mi Pad 2 */
+ { 0x22b0, 0x1d72, 0x1502, quirk_no_vlv_disp_pw_dpio_cmn_bc_init },
};
void intel_init_quirks(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 005b1cec7007..b907b49b4f0e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -524,6 +524,7 @@ struct i915_drrs {
#define QUIRK_INCREASE_T12_DELAY (1<<6)
#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
#define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
+#define QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT (1<<9)
struct intel_fbdev;
struct intel_fbc_work;
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
2021-10-24 15:50 ` Hans de Goede
(?)
@ 2021-10-24 15:59 ` Patchwork
-1 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-10-24 15:59 UTC (permalink / raw)
To: Hans de Goede; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
URL : https://patchwork.freedesktop.org/series/96220/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ba397ea89951 drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
-:21: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#21:
i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
-:153: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#153: FILE: drivers/gpu/drm/i915/i915_drv.h:544:
+#define QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT (1<<9)
^
total: 0 errors, 1 warnings, 1 checks, 75 lines checked
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
2021-10-24 15:50 ` Hans de Goede
(?)
(?)
@ 2021-10-24 16:29 ` Patchwork
-1 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-10-24 16:29 UTC (permalink / raw)
To: Hans de Goede; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6282 bytes --]
== Series Details ==
Series: drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
URL : https://patchwork.freedesktop.org/series/96220/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10782 -> Patchwork_21430
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/index.html
Participating hosts (38 -> 35)
------------------------------
Additional (2): fi-tgl-1115g4 fi-pnv-d510
Missing (5): bat-dg1-6 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600
Known issues
------------
Here are the changes found in Patchwork_21430 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([fdo#109315])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315] / [i915#2575]) +16 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#1155])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#4103]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-plain-flip@c-dp1:
- fi-cfl-8109u: [PASS][8] -> [FAIL][9] ([i915#4165])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][11] -> [FAIL][12] ([i915#2546])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#1072]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][14] ([fdo#109271]) +53 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#3301])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][16] ([i915#1602] / [i915#2426] / [i915#4312])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][17] ([i915#3921]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
Build changes
-------------
* Linux: CI_DRM_10782 -> Patchwork_21430
CI-20190529: 20190529
CI_DRM_10782: 6eff63a9b932a4aa1e1f6e521cd919aaf57c058f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6259: 89629f64da9f12b144f913865b08d2c9efcd10d7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21430: ba397ea89951a856ee618c2cde368d2ef8142576 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ba397ea89951 drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/index.html
[-- Attachment #2: Type: text/html, Size: 7378 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
2021-10-24 15:50 ` Hans de Goede
` (2 preceding siblings ...)
(?)
@ 2021-10-24 17:39 ` Patchwork
-1 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-10-24 17:39 UTC (permalink / raw)
To: Hans de Goede; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30274 bytes --]
== Series Details ==
Series: drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
URL : https://patchwork.freedesktop.org/series/96220/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10782_full -> Patchwork_21430_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21430_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21430_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21430_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-kbl4/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl7/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
Known issues
------------
Here are the changes found in Patchwork_21430_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_sseu@engines:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#280])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#2481] / [i915#3070])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb1/igt@gem_eio@unwedge-stress.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-tglb6/igt@gem_exec_fair@basic-pace@vecs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl2/igt@gem_huc_copy@huc-copy.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#4270])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1436] / [i915#716])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-skl10/igt@gen9_exec_parse@allowed-single.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl7/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-large:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#2856])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@gen9_exec_parse@bb-large.html
* igt@i915_module_load@reload-no-display:
- shard-iclb: [PASS][18] -> [DMESG-WARN][19] ([i915#2867])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb1/igt@i915_module_load@reload-no-display.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb4/igt@i915_module_load@reload-no-display.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-glk: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#658])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111644] / [i915#1397] / [i915#2411])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_selftest@live@gem_contexts:
- shard-skl: NOTRUN -> [INCOMPLETE][22] ([i915#198])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl4/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][23] ([i915#2373])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb1/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][24] ([i915#1759])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb1/igt@i915_selftest@live@gt_pm.html
- shard-skl: NOTRUN -> [DMESG-FAIL][25] ([i915#1886] / [i915#2291])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl4/igt@i915_selftest@live@gt_pm.html
* igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a:
- shard-skl: [PASS][26] -> [DMESG-WARN][27] ([i915#1982])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-skl2/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl8/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- shard-glk: [PASS][28] -> [DMESG-WARN][29] ([i915#118])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-glk1/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk1/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][31] ([i915#3743]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +4 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl2/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][36] ([i915#3689] / [i915#3886])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb1/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl5/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278] / [i915#3886])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb7/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3689]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271]) +86 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl1/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +7 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl2/igt@kms_chamelium@vga-hpd.html
* igt@kms_chamelium@vga-hpd-enable-disable-mode:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb1/igt@kms_chamelium@vga-hpd-enable-disable-mode.html
* igt@kms_color_chamelium@pipe-c-ctm-negative:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +10 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl5/igt@kms_color_chamelium@pipe-c-ctm-negative.html
* igt@kms_color_chamelium@pipe-c-gamma:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +7 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl1/igt@kms_color_chamelium@pipe-c-gamma.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][46] ([i915#1319]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl1/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][47] ([i915#1319])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl1/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][48] ([i915#2105])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl2/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#3319]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][50] ([i915#2346] / [i915#533])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3528])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][52] -> [INCOMPLETE][53] ([i915#180] / [i915#636])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][54] -> [FAIL][55] ([i915#79])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-tglb: NOTRUN -> [SKIP][56] ([fdo#111825]) +8 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: NOTRUN -> [FAIL][57] ([i915#79])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-tglb: [PASS][58] -> [DMESG-WARN][59] ([i915#2411] / [i915#2867]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-tglb3/igt@kms_flip@flip-vs-suspend@a-edp1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb1/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: NOTRUN -> [FAIL][60] ([i915#2122])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-ts-check@a-hdmi-a1:
- shard-glk: [PASS][61] -> [FAIL][62] ([i915#2122])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-glk9/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk4/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-skl: NOTRUN -> [INCOMPLETE][63] ([i915#3699])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2672])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2672])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@basic:
- shard-skl: NOTRUN -> [DMESG-WARN][66] ([i915#1982])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl5/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][67] ([fdo#109271]) +162 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271]) +88 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_hdr@static-toggle:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#1187])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@kms_hdr@static-toggle.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl5/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [PASS][72] -> [DMESG-WARN][73] ([i915#180]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_prime@basic-crc@first-to-second:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#1836])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb1/igt@kms_prime@basic-crc@first-to-second.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#2920]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][81] -> [SKIP][82] ([fdo#109441]) +5 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb3/igt@kms_psr@psr2_no_drrs.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][83] ([i915#132] / [i915#3467])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb7/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_psr@sprite_blt:
- shard-glk: NOTRUN -> [SKIP][84] ([fdo#109271]) +6 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk2/igt@kms_psr@sprite_blt.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-tglb: NOTRUN -> [SKIP][85] ([i915#2530])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@nouveau_crc@pipe-a-source-rg.html
* igt@perf@short-reads:
- shard-skl: [PASS][86] -> [FAIL][87] ([i915#51])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-skl9/igt@perf@short-reads.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl1/igt@perf@short-reads.html
* igt@prime_nv_api@nv_self_import:
- shard-tglb: NOTRUN -> [SKIP][88] ([fdo#109291]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@prime_nv_api@nv_self_import.html
* igt@sysfs_clients@pidname:
- shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl5/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@split-25:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl2/igt@sysfs_clients@split-25.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [DMESG-WARN][91] ([i915#180]) -> [PASS][92] +6 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][93] ([i915#2842]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [FAIL][95] ([i915#2842]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][97] ([i915#2842]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-apl: [SKIP][99] ([fdo#109271]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-apl7/igt@gem_exec_fair@basic-none-share@rcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][101] ([i915#2842]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][103] ([i915#2849]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [DMESG-WARN][105] ([i915#118]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-glk9/igt@gem_exec_whisper@basic-queues-forked-all.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk5/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][107] ([i915#644]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +3 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-apl8/igt@i915_suspend@sysfs-reader.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-apl1/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@cursora-vs-flipa-atomic:
- shard-skl: [DMESG-WARN][111] ([i915#1982]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-skl10/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl7/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-kbl: [DMESG-WARN][113] ([i915#62] / [i915#92]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-kbl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [INCOMPLETE][115] ([i915#2411] / [i915#456]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@plain-flip-ts-check@a-edp1:
- shard-skl: [FAIL][117] ([i915#2122]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-skl5/igt@kms_flip@plain-flip-ts-check@a-edp1.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl6/igt@kms_flip@plain-flip-ts-check@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-iclb: [SKIP][119] ([i915#3701]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][121] ([fdo#108145] / [i915#265]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][123] ([fdo#109441]) -> [PASS][124] +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][125] ([i915#198]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [INCOMPLETE][127] ([i915#4221]) -> [DMESG-WARN][128] ([i915#180])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-kbl1/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][129] ([i915#2684]) -> [WARN][130] ([i915#1804] / [i915#2684])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][131] ([i915#1804] / [i915#2684]) -> [WARN][132] ([i915#2684])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-glk: [DMESG-FAIL][133] ([i915#118] / [i915#1888]) -> [FAIL][134] ([i915#1888])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-glk5/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/shard-glk6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][135] ([i915#62] / [i915#92]) -> [DMESG-WARN][136] ([i915#180])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10782/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_2143
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21430/index.html
[-- Attachment #2: Type: text/html, Size: 33520 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
2021-10-24 15:50 ` Hans de Goede
@ 2021-10-25 8:25 ` Jani Nikula
-1 siblings, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2021-10-25 8:25 UTC (permalink / raw)
To: Hans de Goede, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä
Cc: Hans de Goede, intel-gfx, dri-devel, Tsuchiya Yuto, Deak, Imre
On Sun, 24 Oct 2021, Hans de Goede <hdegoede@redhat.com> wrote:
> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>
> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
> Trail tablet. It deviates from the typical reference design based tablets
> in many ways.
>
> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
> as part of its unusual design it also has some supply rail which is only
> used for DisplayPort or HDMI not connected.
>
> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
> appears to cause the P-Unit to hang. When booting with a serial-usb console
> the following errors are logged before the system freezes:
>
> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
> ------------[ cut here ]------------
> i915 0000:00:02.0: DPIO read pipe A reg 0x8170 == 0xffffffff
> WARNING: CPU: 3 PID: 258 at drivers/gpu/drm/i915/intel_sideband.c:257 vlv_dpio_read+0x95/0xb0 [i915]
> ...
> Call Trace:
> chv_dpio_cmn_power_well_enable+0xab/0x210 [i915]
> __intel_display_power_get_domain.part.0+0xa0/0xc0 [i915]
> intel_power_domains_init_hw+0x26d/0x760 [i915]
> intel_modeset_init_noirq+0x5d/0x270 [i915]
> i915_driver_probe+0x6b6/0xd10 [i915]
> ...
>
> If I disable the WARN about the register being 0xffffffff, so that the
> system can log some more dmesg output over the serial console before
> freezing, the following errors are also logged:
>
> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fcfff3ff)
> i915 0000:00:02.0: [drm] *ERROR* Display PHY 1 is not power up
>
> With this patch to disable the force-enabling of the PHY 0 / dpio-common-bc
> powerwell in place, this error for PHY 1 goes away. So it seems that trying
> the force-enabling of the PHY 0 / dpio-common-bc powerwell freezes the
> P-Unit, causing the subsequent enabling of PHY 1 to also fail (and causing
> the entire system to freeze within seconds).
>
> With this patch the PHY 1 error disappears and the entire system works.
>
> Note this change also moves the intel_init_quirks() call a bit up inside
> intel_modeset_init_noirq() this is necessary so that the quirk is set
> before the intel_power_domains_init_hw() call. This is harmless, all that
> intel_init_quirks() does is set some bits in drm_i915_private.quirks and
> make some drm_info() log calls.
>
> Reported-by: Tsuchiya Yuto <kitakar@gmail.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> .../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++++++++--
> drivers/gpu/drm/i915/display/intel_quirks.c | 10 ++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 4 files changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 015854b5078c..1fb885cc86c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12467,6 +12467,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
> if (ret)
> goto cleanup_bios;
>
> + intel_init_quirks(i915);
> +
> /* FIXME: completely on the wrong abstraction layer */
> intel_power_domains_init_hw(i915, false);
>
> @@ -12501,8 +12503,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
> INIT_WORK(&i915->atomic_helper.free_work,
> intel_atomic_helper_free_state_worker);
>
> - intel_init_quirks(i915);
> -
> intel_fbc_init(i915);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cce1a926fcc1..eeaba3dc064b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -2090,8 +2090,14 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
> if (intel_display_power_grab_async_put_ref(dev_priv, domain))
> return;
>
> - for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
> + for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) {
> + if (domain == POWER_DOMAIN_INIT &&
> + (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
> + power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
> + continue;
> +
> intel_power_well_get(dev_priv, power_well);
> + }
Cc: Imre
There has got to be a way to hide this better. Having this here is
unacceptable.
BR,
Jani.
>
> power_domains->domain_use_count[domain]++;
> }
> @@ -2184,8 +2190,14 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
>
> power_domains->domain_use_count[domain]--;
>
> - for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
> + for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
> + if (domain == POWER_DOMAIN_INIT &&
> + (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
> + power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
> + continue;
> +
> intel_power_well_put(dev_priv, power_well);
> + }
> }
>
> static void __intel_display_power_put(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
> index 8a52b7a16774..c377f515bbf4 100644
> --- a/drivers/gpu/drm/i915/display/intel_quirks.c
> +++ b/drivers/gpu/drm/i915/display/intel_quirks.c
> @@ -59,6 +59,13 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
> drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
> }
>
> +/* The Xiaomi Mi Pad 2 CHT tablet hangs on enabling the dpio-common-bc well */
> +static void quirk_no_vlv_disp_pw_dpio_cmn_bc_init(struct drm_i915_private *i915)
> +{
> + i915->quirks |= QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT;
> + drm_info(&i915->drm, "Applying no dpio-common-bc powerwell init quirk\n");
> +}
> +
> struct intel_quirk {
> int device;
> int subsystem_vendor;
> @@ -190,6 +197,9 @@ static struct intel_quirk intel_quirks[] = {
> /* ASRock ITX*/
> { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
> { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
> +
> + /* Xiaomi Mi Pad 2 */
> + { 0x22b0, 0x1d72, 0x1502, quirk_no_vlv_disp_pw_dpio_cmn_bc_init },
> };
>
> void intel_init_quirks(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 005b1cec7007..b907b49b4f0e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -524,6 +524,7 @@ struct i915_drrs {
> #define QUIRK_INCREASE_T12_DELAY (1<<6)
> #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
> #define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
> +#define QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT (1<<9)
>
> struct intel_fbdev;
> struct intel_fbc_work;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
@ 2021-10-25 8:25 ` Jani Nikula
0 siblings, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2021-10-25 8:25 UTC (permalink / raw)
To: Hans de Goede, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä
Cc: Hans de Goede, intel-gfx, dri-devel, Tsuchiya Yuto, Deak, Imre
On Sun, 24 Oct 2021, Hans de Goede <hdegoede@redhat.com> wrote:
> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>
> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
> Trail tablet. It deviates from the typical reference design based tablets
> in many ways.
>
> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
> as part of its unusual design it also has some supply rail which is only
> used for DisplayPort or HDMI not connected.
>
> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
> appears to cause the P-Unit to hang. When booting with a serial-usb console
> the following errors are logged before the system freezes:
>
> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
> ------------[ cut here ]------------
> i915 0000:00:02.0: DPIO read pipe A reg 0x8170 == 0xffffffff
> WARNING: CPU: 3 PID: 258 at drivers/gpu/drm/i915/intel_sideband.c:257 vlv_dpio_read+0x95/0xb0 [i915]
> ...
> Call Trace:
> chv_dpio_cmn_power_well_enable+0xab/0x210 [i915]
> __intel_display_power_get_domain.part.0+0xa0/0xc0 [i915]
> intel_power_domains_init_hw+0x26d/0x760 [i915]
> intel_modeset_init_noirq+0x5d/0x270 [i915]
> i915_driver_probe+0x6b6/0xd10 [i915]
> ...
>
> If I disable the WARN about the register being 0xffffffff, so that the
> system can log some more dmesg output over the serial console before
> freezing, the following errors are also logged:
>
> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fcfff3ff)
> i915 0000:00:02.0: [drm] *ERROR* Display PHY 1 is not power up
>
> With this patch to disable the force-enabling of the PHY 0 / dpio-common-bc
> powerwell in place, this error for PHY 1 goes away. So it seems that trying
> the force-enabling of the PHY 0 / dpio-common-bc powerwell freezes the
> P-Unit, causing the subsequent enabling of PHY 1 to also fail (and causing
> the entire system to freeze within seconds).
>
> With this patch the PHY 1 error disappears and the entire system works.
>
> Note this change also moves the intel_init_quirks() call a bit up inside
> intel_modeset_init_noirq() this is necessary so that the quirk is set
> before the intel_power_domains_init_hw() call. This is harmless, all that
> intel_init_quirks() does is set some bits in drm_i915_private.quirks and
> make some drm_info() log calls.
>
> Reported-by: Tsuchiya Yuto <kitakar@gmail.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> .../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++++++++--
> drivers/gpu/drm/i915/display/intel_quirks.c | 10 ++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 4 files changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 015854b5078c..1fb885cc86c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12467,6 +12467,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
> if (ret)
> goto cleanup_bios;
>
> + intel_init_quirks(i915);
> +
> /* FIXME: completely on the wrong abstraction layer */
> intel_power_domains_init_hw(i915, false);
>
> @@ -12501,8 +12503,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
> INIT_WORK(&i915->atomic_helper.free_work,
> intel_atomic_helper_free_state_worker);
>
> - intel_init_quirks(i915);
> -
> intel_fbc_init(i915);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cce1a926fcc1..eeaba3dc064b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -2090,8 +2090,14 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
> if (intel_display_power_grab_async_put_ref(dev_priv, domain))
> return;
>
> - for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
> + for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) {
> + if (domain == POWER_DOMAIN_INIT &&
> + (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
> + power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
> + continue;
> +
> intel_power_well_get(dev_priv, power_well);
> + }
Cc: Imre
There has got to be a way to hide this better. Having this here is
unacceptable.
BR,
Jani.
>
> power_domains->domain_use_count[domain]++;
> }
> @@ -2184,8 +2190,14 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
>
> power_domains->domain_use_count[domain]--;
>
> - for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
> + for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
> + if (domain == POWER_DOMAIN_INIT &&
> + (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
> + power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
> + continue;
> +
> intel_power_well_put(dev_priv, power_well);
> + }
> }
>
> static void __intel_display_power_put(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
> index 8a52b7a16774..c377f515bbf4 100644
> --- a/drivers/gpu/drm/i915/display/intel_quirks.c
> +++ b/drivers/gpu/drm/i915/display/intel_quirks.c
> @@ -59,6 +59,13 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
> drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
> }
>
> +/* The Xiaomi Mi Pad 2 CHT tablet hangs on enabling the dpio-common-bc well */
> +static void quirk_no_vlv_disp_pw_dpio_cmn_bc_init(struct drm_i915_private *i915)
> +{
> + i915->quirks |= QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT;
> + drm_info(&i915->drm, "Applying no dpio-common-bc powerwell init quirk\n");
> +}
> +
> struct intel_quirk {
> int device;
> int subsystem_vendor;
> @@ -190,6 +197,9 @@ static struct intel_quirk intel_quirks[] = {
> /* ASRock ITX*/
> { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
> { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
> +
> + /* Xiaomi Mi Pad 2 */
> + { 0x22b0, 0x1d72, 0x1502, quirk_no_vlv_disp_pw_dpio_cmn_bc_init },
> };
>
> void intel_init_quirks(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 005b1cec7007..b907b49b4f0e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -524,6 +524,7 @@ struct i915_drrs {
> #define QUIRK_INCREASE_T12_DELAY (1<<6)
> #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
> #define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
> +#define QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT (1<<9)
>
> struct intel_fbdev;
> struct intel_fbc_work;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
2021-10-25 8:25 ` Jani Nikula
@ 2021-10-25 9:15 ` Hans de Goede
-1 siblings, 0 replies; 15+ messages in thread
From: Hans de Goede @ 2021-10-25 9:15 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä
Cc: intel-gfx, dri-devel, Tsuchiya Yuto, Deak, Imre
Hi,
On 10/25/21 10:25, Jani Nikula wrote:
> On Sun, 24 Oct 2021, Hans de Goede <hdegoede@redhat.com> wrote:
>> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
>> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>>
>> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
>> Trail tablet. It deviates from the typical reference design based tablets
>> in many ways.
>>
>> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
>> as part of its unusual design it also has some supply rail which is only
>> used for DisplayPort or HDMI not connected.
>>
>> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
>> appears to cause the P-Unit to hang. When booting with a serial-usb console
>> the following errors are logged before the system freezes:
>>
>> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
>> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
>> ------------[ cut here ]------------
>> i915 0000:00:02.0: DPIO read pipe A reg 0x8170 == 0xffffffff
>> WARNING: CPU: 3 PID: 258 at drivers/gpu/drm/i915/intel_sideband.c:257 vlv_dpio_read+0x95/0xb0 [i915]
>> ...
>> Call Trace:
>> chv_dpio_cmn_power_well_enable+0xab/0x210 [i915]
>> __intel_display_power_get_domain.part.0+0xa0/0xc0 [i915]
>> intel_power_domains_init_hw+0x26d/0x760 [i915]
>> intel_modeset_init_noirq+0x5d/0x270 [i915]
>> i915_driver_probe+0x6b6/0xd10 [i915]
>> ...
>>
>> If I disable the WARN about the register being 0xffffffff, so that the
>> system can log some more dmesg output over the serial console before
>> freezing, the following errors are also logged:
>>
>> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fcfff3ff)
>> i915 0000:00:02.0: [drm] *ERROR* Display PHY 1 is not power up
>>
>> With this patch to disable the force-enabling of the PHY 0 / dpio-common-bc
>> powerwell in place, this error for PHY 1 goes away. So it seems that trying
>> the force-enabling of the PHY 0 / dpio-common-bc powerwell freezes the
>> P-Unit, causing the subsequent enabling of PHY 1 to also fail (and causing
>> the entire system to freeze within seconds).
>>
>> With this patch the PHY 1 error disappears and the entire system works.
>>
>> Note this change also moves the intel_init_quirks() call a bit up inside
>> intel_modeset_init_noirq() this is necessary so that the quirk is set
>> before the intel_power_domains_init_hw() call. This is harmless, all that
>> intel_init_quirks() does is set some bits in drm_i915_private.quirks and
>> make some drm_info() log calls.
>>
>> Reported-by: Tsuchiya Yuto <kitakar@gmail.com>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>> .../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++++++++--
>> drivers/gpu/drm/i915/display/intel_quirks.c | 10 ++++++++++
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> 4 files changed, 27 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 015854b5078c..1fb885cc86c9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -12467,6 +12467,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
>> if (ret)
>> goto cleanup_bios;
>>
>> + intel_init_quirks(i915);
>> +
>> /* FIXME: completely on the wrong abstraction layer */
>> intel_power_domains_init_hw(i915, false);
>>
>> @@ -12501,8 +12503,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
>> INIT_WORK(&i915->atomic_helper.free_work,
>> intel_atomic_helper_free_state_worker);
>>
>> - intel_init_quirks(i915);
>> -
>> intel_fbc_init(i915);
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index cce1a926fcc1..eeaba3dc064b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -2090,8 +2090,14 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
>> if (intel_display_power_grab_async_put_ref(dev_priv, domain))
>> return;
>>
>> - for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
>> + for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) {
>> + if (domain == POWER_DOMAIN_INIT &&
>> + (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
>> + power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
>> + continue;
>> +
>> intel_power_well_get(dev_priv, power_well);
>> + }
>
> Cc: Imre
>
> There has got to be a way to hide this better. Having this here is
> unacceptable.
Thank you for your quick review.
For a first quick hack I just removed POWER_DOMAIN_INIT from
CHV_DPIO_CMN_BC_POWER_DOMAINS.
Some alternative ideas:
1. Mask out the POWER_DOMAIN_INIT bit from desc->domains
But that requires making the desc struct non const; Or storing a
copy of the domains field in struct i915_power_well and masking it
out in the copy (and make for_each_power_domain_well use the copy).
2. Have a separate desc without POWER_DOMAIN_INIT and patch up the
power_well->desc pointer in intel_power_domains_init().
I believe that 1. will be slightly cleaner (with the domains
mask copy added to struct i915_power_well).
If this sounds like it might be acceptable I can give 1. a shot
(or 2 if that is preferred). So does 1. sound acceptable ?
Regards,
Hans
>> power_domains->domain_use_count[domain]++;
>> }
>> @@ -2184,8 +2190,14 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
>>
>> power_domains->domain_use_count[domain]--;
>>
>> - for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
>> + for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
>> + if (domain == POWER_DOMAIN_INIT &&
>> + (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
>> + power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
>> + continue;
>> +
>> intel_power_well_put(dev_priv, power_well);
>> + }
>> }
>>
>> static void __intel_display_power_put(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
>> index 8a52b7a16774..c377f515bbf4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_quirks.c
>> +++ b/drivers/gpu/drm/i915/display/intel_quirks.c
>> @@ -59,6 +59,13 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
>> drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
>> }
>>
>> +/* The Xiaomi Mi Pad 2 CHT tablet hangs on enabling the dpio-common-bc well */
>> +static void quirk_no_vlv_disp_pw_dpio_cmn_bc_init(struct drm_i915_private *i915)
>> +{
>> + i915->quirks |= QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT;
>> + drm_info(&i915->drm, "Applying no dpio-common-bc powerwell init quirk\n");
>> +}
>> +
>> struct intel_quirk {
>> int device;
>> int subsystem_vendor;
>> @@ -190,6 +197,9 @@ static struct intel_quirk intel_quirks[] = {
>> /* ASRock ITX*/
>> { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
>> { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
>> +
>> + /* Xiaomi Mi Pad 2 */
>> + { 0x22b0, 0x1d72, 0x1502, quirk_no_vlv_disp_pw_dpio_cmn_bc_init },
>> };
>>
>> void intel_init_quirks(struct drm_i915_private *i915)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 005b1cec7007..b907b49b4f0e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -524,6 +524,7 @@ struct i915_drrs {
>> #define QUIRK_INCREASE_T12_DELAY (1<<6)
>> #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
>> #define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
>> +#define QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT (1<<9)
>>
>> struct intel_fbdev;
>> struct intel_fbc_work;
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
@ 2021-10-25 9:15 ` Hans de Goede
0 siblings, 0 replies; 15+ messages in thread
From: Hans de Goede @ 2021-10-25 9:15 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä
Cc: intel-gfx, dri-devel, Tsuchiya Yuto, Deak, Imre
Hi,
On 10/25/21 10:25, Jani Nikula wrote:
> On Sun, 24 Oct 2021, Hans de Goede <hdegoede@redhat.com> wrote:
>> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
>> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>>
>> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
>> Trail tablet. It deviates from the typical reference design based tablets
>> in many ways.
>>
>> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
>> as part of its unusual design it also has some supply rail which is only
>> used for DisplayPort or HDMI not connected.
>>
>> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
>> appears to cause the P-Unit to hang. When booting with a serial-usb console
>> the following errors are logged before the system freezes:
>>
>> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
>> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
>> ------------[ cut here ]------------
>> i915 0000:00:02.0: DPIO read pipe A reg 0x8170 == 0xffffffff
>> WARNING: CPU: 3 PID: 258 at drivers/gpu/drm/i915/intel_sideband.c:257 vlv_dpio_read+0x95/0xb0 [i915]
>> ...
>> Call Trace:
>> chv_dpio_cmn_power_well_enable+0xab/0x210 [i915]
>> __intel_display_power_get_domain.part.0+0xa0/0xc0 [i915]
>> intel_power_domains_init_hw+0x26d/0x760 [i915]
>> intel_modeset_init_noirq+0x5d/0x270 [i915]
>> i915_driver_probe+0x6b6/0xd10 [i915]
>> ...
>>
>> If I disable the WARN about the register being 0xffffffff, so that the
>> system can log some more dmesg output over the serial console before
>> freezing, the following errors are also logged:
>>
>> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fcfff3ff)
>> i915 0000:00:02.0: [drm] *ERROR* Display PHY 1 is not power up
>>
>> With this patch to disable the force-enabling of the PHY 0 / dpio-common-bc
>> powerwell in place, this error for PHY 1 goes away. So it seems that trying
>> the force-enabling of the PHY 0 / dpio-common-bc powerwell freezes the
>> P-Unit, causing the subsequent enabling of PHY 1 to also fail (and causing
>> the entire system to freeze within seconds).
>>
>> With this patch the PHY 1 error disappears and the entire system works.
>>
>> Note this change also moves the intel_init_quirks() call a bit up inside
>> intel_modeset_init_noirq() this is necessary so that the quirk is set
>> before the intel_power_domains_init_hw() call. This is harmless, all that
>> intel_init_quirks() does is set some bits in drm_i915_private.quirks and
>> make some drm_info() log calls.
>>
>> Reported-by: Tsuchiya Yuto <kitakar@gmail.com>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>> .../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++++++++--
>> drivers/gpu/drm/i915/display/intel_quirks.c | 10 ++++++++++
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> 4 files changed, 27 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 015854b5078c..1fb885cc86c9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -12467,6 +12467,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
>> if (ret)
>> goto cleanup_bios;
>>
>> + intel_init_quirks(i915);
>> +
>> /* FIXME: completely on the wrong abstraction layer */
>> intel_power_domains_init_hw(i915, false);
>>
>> @@ -12501,8 +12503,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
>> INIT_WORK(&i915->atomic_helper.free_work,
>> intel_atomic_helper_free_state_worker);
>>
>> - intel_init_quirks(i915);
>> -
>> intel_fbc_init(i915);
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index cce1a926fcc1..eeaba3dc064b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -2090,8 +2090,14 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
>> if (intel_display_power_grab_async_put_ref(dev_priv, domain))
>> return;
>>
>> - for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
>> + for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) {
>> + if (domain == POWER_DOMAIN_INIT &&
>> + (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
>> + power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
>> + continue;
>> +
>> intel_power_well_get(dev_priv, power_well);
>> + }
>
> Cc: Imre
>
> There has got to be a way to hide this better. Having this here is
> unacceptable.
Thank you for your quick review.
For a first quick hack I just removed POWER_DOMAIN_INIT from
CHV_DPIO_CMN_BC_POWER_DOMAINS.
Some alternative ideas:
1. Mask out the POWER_DOMAIN_INIT bit from desc->domains
But that requires making the desc struct non const; Or storing a
copy of the domains field in struct i915_power_well and masking it
out in the copy (and make for_each_power_domain_well use the copy).
2. Have a separate desc without POWER_DOMAIN_INIT and patch up the
power_well->desc pointer in intel_power_domains_init().
I believe that 1. will be slightly cleaner (with the domains
mask copy added to struct i915_power_well).
If this sounds like it might be acceptable I can give 1. a shot
(or 2 if that is preferred). So does 1. sound acceptable ?
Regards,
Hans
>> power_domains->domain_use_count[domain]++;
>> }
>> @@ -2184,8 +2190,14 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
>>
>> power_domains->domain_use_count[domain]--;
>>
>> - for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
>> + for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
>> + if (domain == POWER_DOMAIN_INIT &&
>> + (dev_priv->quirks & QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT) &&
>> + power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC)
>> + continue;
>> +
>> intel_power_well_put(dev_priv, power_well);
>> + }
>> }
>>
>> static void __intel_display_power_put(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
>> index 8a52b7a16774..c377f515bbf4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_quirks.c
>> +++ b/drivers/gpu/drm/i915/display/intel_quirks.c
>> @@ -59,6 +59,13 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
>> drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
>> }
>>
>> +/* The Xiaomi Mi Pad 2 CHT tablet hangs on enabling the dpio-common-bc well */
>> +static void quirk_no_vlv_disp_pw_dpio_cmn_bc_init(struct drm_i915_private *i915)
>> +{
>> + i915->quirks |= QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT;
>> + drm_info(&i915->drm, "Applying no dpio-common-bc powerwell init quirk\n");
>> +}
>> +
>> struct intel_quirk {
>> int device;
>> int subsystem_vendor;
>> @@ -190,6 +197,9 @@ static struct intel_quirk intel_quirks[] = {
>> /* ASRock ITX*/
>> { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
>> { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
>> +
>> + /* Xiaomi Mi Pad 2 */
>> + { 0x22b0, 0x1d72, 0x1502, quirk_no_vlv_disp_pw_dpio_cmn_bc_init },
>> };
>>
>> void intel_init_quirks(struct drm_i915_private *i915)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 005b1cec7007..b907b49b4f0e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -524,6 +524,7 @@ struct i915_drrs {
>> #define QUIRK_INCREASE_T12_DELAY (1<<6)
>> #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
>> #define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
>> +#define QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT (1<<9)
>>
>> struct intel_fbdev;
>> struct intel_fbc_work;
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
2021-10-24 15:50 ` Hans de Goede
@ 2021-10-27 13:38 ` Ville Syrjälä
-1 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2021-10-27 13:38 UTC (permalink / raw)
To: Hans de Goede
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, intel-gfx, dri-devel,
Tsuchiya Yuto
On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>
> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
> Trail tablet. It deviates from the typical reference design based tablets
> in many ways.
>
> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
> as part of its unusual design it also has some supply rail which is only
> used for DisplayPort or HDMI not connected.
Do we have the VBT somewhere (preferable attached to a bug report)?
Maybe we can avoid an ugly quirk.
>
> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
> appears to cause the P-Unit to hang. When booting with a serial-usb console
> the following errors are logged before the system freezes:
>
> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
Hmm. I wonder if we're missing a clock or something...
Either of these do anything different?
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1419,6 +1419,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
for_each_pipe(dev_priv, pipe) {
u32 val = intel_de_read(dev_priv, DPLL(pipe));
+ val |= DPLL_SSC_REF_CLK_CHV;
or
+ val &= ~DPLL_SSC_REF_CLK_CHV;
val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
@ 2021-10-27 13:38 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2021-10-27 13:38 UTC (permalink / raw)
To: Hans de Goede
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, intel-gfx, dri-devel,
Tsuchiya Yuto
On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>
> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
> Trail tablet. It deviates from the typical reference design based tablets
> in many ways.
>
> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
> as part of its unusual design it also has some supply rail which is only
> used for DisplayPort or HDMI not connected.
Do we have the VBT somewhere (preferable attached to a bug report)?
Maybe we can avoid an ugly quirk.
>
> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
> appears to cause the P-Unit to hang. When booting with a serial-usb console
> the following errors are logged before the system freezes:
>
> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
Hmm. I wonder if we're missing a clock or something...
Either of these do anything different?
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1419,6 +1419,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
for_each_pipe(dev_priv, pipe) {
u32 val = intel_de_read(dev_priv, DPLL(pipe));
+ val |= DPLL_SSC_REF_CLK_CHV;
or
+ val &= ~DPLL_SSC_REF_CLK_CHV;
val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
2021-10-27 13:38 ` Ville Syrjälä
@ 2021-10-27 18:39 ` Hans de Goede
-1 siblings, 0 replies; 15+ messages in thread
From: Hans de Goede @ 2021-10-27 18:39 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, intel-gfx, dri-devel,
Tsuchiya Yuto
Hi,
On 10/27/21 15:38, Ville Syrjälä wrote:
> On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
>> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
>> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>>
>> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
>> Trail tablet. It deviates from the typical reference design based tablets
>> in many ways.
>>
>> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
>> as part of its unusual design it also has some supply rail which is only
>> used for DisplayPort or HDMI not connected.
>
> Do we have the VBT somewhere (preferable attached to a bug report)?
> Maybe we can avoid an ugly quirk.
I agree that solving this in a way where we can avoid the quirk would be great.
I've filed an issue for this here now:
https://gitlab.freedesktop.org/drm/intel/-/issues/4385
This has a dump of /sys/kernel/debug/dri/0/i915_vbt as well as
dmesg output from a boot with drm.debug=0x1e attached (from a boot
with this patch, since otherwise the system hangs).
>>
>> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
>> appears to cause the P-Unit to hang. When booting with a serial-usb console
>> the following errors are logged before the system freezes:
>>
>> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
>> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
>
> Hmm. I wonder if we're missing a clock or something...
>
> Either of these do anything different?
>
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1419,6 +1419,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
> for_each_pipe(dev_priv, pipe) {
> u32 val = intel_de_read(dev_priv, DPLL(pipe));
>
> + val |= DPLL_SSC_REF_CLK_CHV;
> or
> + val &= ~DPLL_SSC_REF_CLK_CHV;
>
> val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> if (pipe != PIPE_A)
> val |= DPLL_INTEGRATED_CRI_CLK_VLV;
>
The hang gets triggered from chv_dpio_cmn_power_well_enable() which does not
call vlv_display_power_well_init() at all, it directly calls vlv_set_power_well()
without first calling vlv_display_power_well_init() .
Note the same goes for vlv_dpio_cmn_power_well_enable(). Only the
vlv_display_power_well_enable() / chv_pipe_power_well_enable() call
vlv_display_power_well_init().
Note I can still give the suggested change a try if you want,
the "display" powerwell is listed first and has DOMAIN_INIT set,
so assuming for_each_power_domain_well() goes through the domains in
the order they are listed, then vlv_display_power_well_init() will
still run first. But it would seem to be wrong if enabling one domain
depends on things setup by another domain ?
Regards,
Hans
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
@ 2021-10-27 18:39 ` Hans de Goede
0 siblings, 0 replies; 15+ messages in thread
From: Hans de Goede @ 2021-10-27 18:39 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, intel-gfx, dri-devel,
Tsuchiya Yuto
Hi,
On 10/27/21 15:38, Ville Syrjälä wrote:
> On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
>> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
>> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>>
>> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
>> Trail tablet. It deviates from the typical reference design based tablets
>> in many ways.
>>
>> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
>> as part of its unusual design it also has some supply rail which is only
>> used for DisplayPort or HDMI not connected.
>
> Do we have the VBT somewhere (preferable attached to a bug report)?
> Maybe we can avoid an ugly quirk.
I agree that solving this in a way where we can avoid the quirk would be great.
I've filed an issue for this here now:
https://gitlab.freedesktop.org/drm/intel/-/issues/4385
This has a dump of /sys/kernel/debug/dri/0/i915_vbt as well as
dmesg output from a boot with drm.debug=0x1e attached (from a boot
with this patch, since otherwise the system hangs).
>>
>> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
>> appears to cause the P-Unit to hang. When booting with a serial-usb console
>> the following errors are logged before the system freezes:
>>
>> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
>> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
>
> Hmm. I wonder if we're missing a clock or something...
>
> Either of these do anything different?
>
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1419,6 +1419,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
> for_each_pipe(dev_priv, pipe) {
> u32 val = intel_de_read(dev_priv, DPLL(pipe));
>
> + val |= DPLL_SSC_REF_CLK_CHV;
> or
> + val &= ~DPLL_SSC_REF_CLK_CHV;
>
> val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> if (pipe != PIPE_A)
> val |= DPLL_INTEGRATED_CRI_CLK_VLV;
>
The hang gets triggered from chv_dpio_cmn_power_well_enable() which does not
call vlv_display_power_well_init() at all, it directly calls vlv_set_power_well()
without first calling vlv_display_power_well_init() .
Note the same goes for vlv_dpio_cmn_power_well_enable(). Only the
vlv_display_power_well_enable() / chv_pipe_power_well_enable() call
vlv_display_power_well_init().
Note I can still give the suggested change a try if you want,
the "display" powerwell is listed first and has DOMAIN_INIT set,
so assuming for_each_power_domain_well() goes through the domains in
the order they are listed, then vlv_display_power_well_init() will
still run first. But it would seem to be wrong if enabling one domain
depends on things setup by another domain ?
Regards,
Hans
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
2021-10-27 18:39 ` Hans de Goede
@ 2021-10-28 13:08 ` Ville Syrjälä
-1 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2021-10-28 13:08 UTC (permalink / raw)
To: Hans de Goede
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, intel-gfx, dri-devel,
Tsuchiya Yuto
On Wed, Oct 27, 2021 at 08:39:57PM +0200, Hans de Goede wrote:
> Hi,
>
> On 10/27/21 15:38, Ville Syrjälä wrote:
> > On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
> >> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
> >> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
> >>
> >> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
> >> Trail tablet. It deviates from the typical reference design based tablets
> >> in many ways.
> >>
> >> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
> >> as part of its unusual design it also has some supply rail which is only
> >> used for DisplayPort or HDMI not connected.
> >
> > Do we have the VBT somewhere (preferable attached to a bug report)?
> > Maybe we can avoid an ugly quirk.
>
> I agree that solving this in a way where we can avoid the quirk would be great.
>
> I've filed an issue for this here now:
>
> https://gitlab.freedesktop.org/drm/intel/-/issues/4385
>
> This has a dump of /sys/kernel/debug/dri/0/i915_vbt as well as
> dmesg output from a boot with drm.debug=0x1e attached (from a boot
> with this patch, since otherwise the system hangs).
>
> >>
> >> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
> >> appears to cause the P-Unit to hang. When booting with a serial-usb console
> >> the following errors are logged before the system freezes:
> >>
> >> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
> >> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
> >
> > Hmm. I wonder if we're missing a clock or something...
> >
> > Either of these do anything different?
> >
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1419,6 +1419,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
> > for_each_pipe(dev_priv, pipe) {
> > u32 val = intel_de_read(dev_priv, DPLL(pipe));
> >
> > + val |= DPLL_SSC_REF_CLK_CHV;
> > or
> > + val &= ~DPLL_SSC_REF_CLK_CHV;
> >
> > val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > if (pipe != PIPE_A)
> > val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> >
>
> The hang gets triggered from chv_dpio_cmn_power_well_enable() which does not
> call vlv_display_power_well_init() at all, it directly calls vlv_set_power_well()
> without first calling vlv_display_power_well_init() .
>
> Note the same goes for vlv_dpio_cmn_power_well_enable(). Only the
> vlv_display_power_well_enable() / chv_pipe_power_well_enable() call
> vlv_display_power_well_init().
>
> Note I can still give the suggested change a try if you want,
> the "display" powerwell is listed first and has DOMAIN_INIT set,
> so assuming for_each_power_domain_well() goes through the domains in
> the order they are listed, then vlv_display_power_well_init() will
> still run first. But it would seem to be wrong if enabling one domain
> depends on things setup by another domain ?
The power wells are hierarchical. Also power wells != power domains.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk
@ 2021-10-28 13:08 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2021-10-28 13:08 UTC (permalink / raw)
To: Hans de Goede
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, intel-gfx, dri-devel,
Tsuchiya Yuto
On Wed, Oct 27, 2021 at 08:39:57PM +0200, Hans de Goede wrote:
> Hi,
>
> On 10/27/21 15:38, Ville Syrjälä wrote:
> > On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
> >> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
> >> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
> >>
> >> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
> >> Trail tablet. It deviates from the typical reference design based tablets
> >> in many ways.
> >>
> >> The Mi Pad 2 does not have any DisplayPort or HDMI outouts. I suspect that
> >> as part of its unusual design it also has some supply rail which is only
> >> used for DisplayPort or HDMI not connected.
> >
> > Do we have the VBT somewhere (preferable attached to a bug report)?
> > Maybe we can avoid an ugly quirk.
>
> I agree that solving this in a way where we can avoid the quirk would be great.
>
> I've filed an issue for this here now:
>
> https://gitlab.freedesktop.org/drm/intel/-/issues/4385
>
> This has a dump of /sys/kernel/debug/dri/0/i915_vbt as well as
> dmesg output from a boot with drm.debug=0x1e attached (from a boot
> with this patch, since otherwise the system hangs).
>
> >>
> >> Force-enabling the dpio-common-bc powerwell as the i915 normal does at boot
> >> appears to cause the P-Unit to hang. When booting with a serial-usb console
> >> the following errors are logged before the system freezes:
> >>
> >> i915 0000:00:02.0: [drm] *ERROR* timeout setting power well state 00000000 (fffff3ff)
> >> i915 0000:00:02.0: [drm] *ERROR* Display PHY 0 is not power up
> >
> > Hmm. I wonder if we're missing a clock or something...
> >
> > Either of these do anything different?
> >
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1419,6 +1419,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
> > for_each_pipe(dev_priv, pipe) {
> > u32 val = intel_de_read(dev_priv, DPLL(pipe));
> >
> > + val |= DPLL_SSC_REF_CLK_CHV;
> > or
> > + val &= ~DPLL_SSC_REF_CLK_CHV;
> >
> > val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > if (pipe != PIPE_A)
> > val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> >
>
> The hang gets triggered from chv_dpio_cmn_power_well_enable() which does not
> call vlv_display_power_well_init() at all, it directly calls vlv_set_power_well()
> without first calling vlv_display_power_well_init() .
>
> Note the same goes for vlv_dpio_cmn_power_well_enable(). Only the
> vlv_display_power_well_enable() / chv_pipe_power_well_enable() call
> vlv_display_power_well_init().
>
> Note I can still give the suggested change a try if you want,
> the "display" powerwell is listed first and has DOMAIN_INIT set,
> so assuming for_each_power_domain_well() goes through the domains in
> the order they are listed, then vlv_display_power_well_init() will
> still run first. But it would seem to be wrong if enabling one domain
> depends on things setup by another domain ?
The power wells are hierarchical. Also power wells != power domains.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2021-10-28 13:08 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-10-24 15:50 [Intel-gfx] [PATCH] drm/i915: Add NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk Hans de Goede
2021-10-24 15:50 ` Hans de Goede
2021-10-24 15:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-10-24 16:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-24 17:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-25 8:25 ` [Intel-gfx] [PATCH] " Jani Nikula
2021-10-25 8:25 ` Jani Nikula
2021-10-25 9:15 ` [Intel-gfx] " Hans de Goede
2021-10-25 9:15 ` Hans de Goede
2021-10-27 13:38 ` [Intel-gfx] " Ville Syrjälä
2021-10-27 13:38 ` Ville Syrjälä
2021-10-27 18:39 ` [Intel-gfx] " Hans de Goede
2021-10-27 18:39 ` Hans de Goede
2021-10-28 13:08 ` [Intel-gfx] " Ville Syrjälä
2021-10-28 13:08 ` Ville Syrjälä
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.