[PATCH v3 0/2] Add PCIe clock DT entries for SC7280

[PATCH v3 0/2] Add PCIe clock DT entries for SC7280

[Prasad Malisetty]

Changes Added in v3:
	
	* Seperated v2 patch as two patches. One patch is for 
	  Fixing incorrect clock name and another patch is for
	  Adding PCIe clock handle for SC7280.

	* Added fixes patch for interrup-map parent address cells 
	  For SC7280.

Prasad Malisetty (2):
  arm64: dts: qcom: sc7280: Fix incorrect clock name
  arm64: dts: qcom: sc7280: Add pcie clock support

 arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 1/3] arm64: dts: qcom: sc7280: Fix incorrect clock name

[Prasad Malisetty]

Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk
To match with dt binding.

Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node")

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reported-by: kernel test robot <lkp@intel.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 365a2e0..cb94b87 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -576,7 +576,7 @@
 				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 				 <0>, <0>, <0>, <0>, <0>, <0>;
 			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
-				      "pcie_0_pipe_clk", "pcie_1_pipe-clk",
+				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
 				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 				      "ufs_phy_tx_symbol_0_clk",
 				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 1/3] arm64: dts: qcom: sc7280: Fix incorrect clock name

[Stephen Boyd]

Quoting Prasad Malisetty (2021-11-16 03:01:46)
> Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk
> To match with dt binding.
>
> Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node")
>
> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
> Reported-by: kernel test robot <lkp@intel.com>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH v3 1/3] arm64: dts: qcom: sc7280: Fix incorrect clock name

[Bjorn Andersson]

On Tue 16 Nov 05:01 CST 2021, Prasad Malisetty wrote:

> Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk
> To match with dt binding.
> 
> Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node")
> 
> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
> Reported-by: kernel test robot <lkp@intel.com>

This says "lkp reported an issue and this patch fixes that issue", but
looking back I think you picked up this tag because lkp had problems
building v1 of this patch.

I will drop it while applying the patch and I will remove the empty line
between Fixes and your S-o-b.

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 365a2e0..cb94b87 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -576,7 +576,7 @@
>  				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
>  				 <0>, <0>, <0>, <0>, <0>, <0>;
>  			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> -				      "pcie_0_pipe_clk", "pcie_1_pipe-clk",
> +				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
>  				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
>  				      "ufs_phy_tx_symbol_0_clk",
>  				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

[PATCH v3 2/3] arm64: dts: qcom: sc7280: Add pcie clock support

[Prasad Malisetty]

Add pcie clock phandle for sc7280 SoC.

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index cb94b87..3fb9338 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -574,7 +574,8 @@
 			reg = <0 0x00100000 0 0x1f0000>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
-				 <0>, <0>, <0>, <0>, <0>, <0>;
+				 <0>, <&pcie1_lane 0>,
+				 <0>, <0>, <0>, <0>;
 			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
 				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 2/3] arm64: dts: qcom: sc7280: Add pcie clock support

[Stephen Boyd]

Quoting Prasad Malisetty (2021-11-16 03:01:47)
> Add pcie clock phandle for sc7280 SoC.
>
> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

[PATCH v3 3/3] arm64: dts: qcom: Fix 'interrupt-map' parent address cells

[Prasad Malisetty]

Update interrupt-map parent address cells for sc7280
Similar to existing Qcom SoCs.

Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes")

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 3fb9338..9ca9c31 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1593,10 +1593,10 @@
 			interrupt-names = "msi";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>,
-					<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
 
 			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
 				 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 3/3] arm64: dts: qcom: Fix 'interrupt-map' parent address cells

[Stephen Boyd]

Quoting Prasad Malisetty (2021-11-16 03:01:48)
> Update interrupt-map parent address cells for sc7280
> Similar to existing Qcom SoCs.
>
> Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes")
>

There shouldn't be a newline between Fixes and SoB

> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH v3 0/2] Add PCIe clock DT entries for SC7280

[Bjorn Andersson]

On Tue, 16 Nov 2021 16:31:45 +0530, Prasad Malisetty wrote:
> Changes Added in v3:
> 
> 	* Seperated v2 patch as two patches. One patch is for
> 	  Fixing incorrect clock name and another patch is for
> 	  Adding PCIe clock handle for SC7280.
> 
> 	* Added fixes patch for interrup-map parent address cells
> 	  For SC7280.
> 
> [...]

Applied, thanks!

[1/3] arm64: dts: qcom: sc7280: Fix incorrect clock name
      commit: fa09b2248714c64644576d8064e9bd292a504a0e
[2/3] arm64: dts: qcom: sc7280: Add pcie clock support
      commit: bd7d507935ca73fba6b6f0f52a3d08d77b143c58
[3/3] arm64: dts: qcom: Fix 'interrupt-map' parent address cells
      commit: 66b788133030f0c69a0ecc7f72f7939b119c9a69

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@linaro.org>