* [PATCH v3 0/2] arm/arm64: dts: Enable more network hardware
@ 2021-12-05 22:56 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-12-05 22:56 UTC (permalink / raw)
To: andrew, gregory.clement, sebastian.hesselbarth, robh+dt, kabel,
linux
Cc: linux-arm-kernel, devicetree, linux-kernel, Chris Packham
This series enables the Switch on the CN9130-CRB. The changes are based on the
Marvell SDK.
Note that if anyone tries out the SFP+ port on a complete CRB shipped from
Marvell the chassis prevents the ejector from working so the SFP will get
stuck. Taking the board out of the chassis allows the SFP to be
insterted/removed.
Chris Packham (2):
arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB
arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 140 ++++++++++++++++++++
1 file changed, 140 insertions(+)
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 0/2] arm/arm64: dts: Enable more network hardware
@ 2021-12-05 22:56 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-12-05 22:56 UTC (permalink / raw)
To: andrew, gregory.clement, sebastian.hesselbarth, robh+dt, kabel,
linux
Cc: linux-arm-kernel, devicetree, linux-kernel, Chris Packham
This series enables the Switch on the CN9130-CRB. The changes are based on the
Marvell SDK.
Note that if anyone tries out the SFP+ port on a complete CRB shipped from
Marvell the chassis prevents the ejector from working so the SFP will get
stuck. Taking the board out of the chassis allows the SFP to be
insterted/removed.
Chris Packham (2):
arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB
arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 140 ++++++++++++++++++++
1 file changed, 140 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 1/2] arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB
2021-12-05 22:56 ` Chris Packham
@ 2021-12-05 22:56 ` Chris Packham
-1 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-12-05 22:56 UTC (permalink / raw)
To: andrew, gregory.clement, sebastian.hesselbarth, robh+dt, kabel,
linux
Cc: linux-arm-kernel, devicetree, linux-kernel, Chris Packham
Enable the CP0 GPIO devices for the CN9130-CRB. This is needed for a
number of the peripheral devices to function.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Changes in v3:
- None
Changes in v2:
- New
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
index e7918f325646..0885c6339d1b 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -17,6 +17,8 @@ aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
};
memory@0 {
@@ -114,6 +116,14 @@ cp0_spi0_pins: cp0-spi-pins-0 {
};
};
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 1/2] arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB
@ 2021-12-05 22:56 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-12-05 22:56 UTC (permalink / raw)
To: andrew, gregory.clement, sebastian.hesselbarth, robh+dt, kabel,
linux
Cc: linux-arm-kernel, devicetree, linux-kernel, Chris Packham
Enable the CP0 GPIO devices for the CN9130-CRB. This is needed for a
number of the peripheral devices to function.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Changes in v3:
- None
Changes in v2:
- New
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
index e7918f325646..0885c6339d1b 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -17,6 +17,8 @@ aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
};
memory@0 {
@@ -114,6 +116,14 @@ cp0_spi0_pins: cp0-spi-pins-0 {
};
};
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 1/2] arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB
2021-12-05 22:56 ` Chris Packham
@ 2021-12-06 2:03 ` Andrew Lunn
-1 siblings, 0 replies; 10+ messages in thread
From: Andrew Lunn @ 2021-12-06 2:03 UTC (permalink / raw)
To: Chris Packham
Cc: gregory.clement, sebastian.hesselbarth, robh+dt, kabel, linux,
linux-arm-kernel, devicetree, linux-kernel
On Mon, Dec 06, 2021 at 11:56:17AM +1300, Chris Packham wrote:
> Enable the CP0 GPIO devices for the CN9130-CRB. This is needed for a
> number of the peripheral devices to function.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v3 1/2] arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB
@ 2021-12-06 2:03 ` Andrew Lunn
0 siblings, 0 replies; 10+ messages in thread
From: Andrew Lunn @ 2021-12-06 2:03 UTC (permalink / raw)
To: Chris Packham
Cc: gregory.clement, sebastian.hesselbarth, robh+dt, kabel, linux,
linux-arm-kernel, devicetree, linux-kernel
On Mon, Dec 06, 2021 at 11:56:17AM +1300, Chris Packham wrote:
> Enable the CP0 GPIO devices for the CN9130-CRB. This is needed for a
> number of the peripheral devices to function.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 2/2] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree
2021-12-05 22:56 ` Chris Packham
@ 2021-12-05 22:56 ` Chris Packham
-1 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-12-05 22:56 UTC (permalink / raw)
To: andrew, gregory.clement, sebastian.hesselbarth, robh+dt, kabel,
linux
Cc: linux-arm-kernel, devicetree, linux-kernel, Chris Packham
The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add
the necessary dts nodes and properties for this.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
This is based on the Marvell SDK. I've re-ordered the port entries to
be in ascending order renamed the wan ports and connected the SFP+.
Change in v3:
- Add review from Russell
- Change port@10 to port@a
- Add maximum-power-milliwatt property to SFP
Changes in v2:
- Remove unused port0
- Label all ports "pN"
- Add interrupt connections
- Add SFP
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 130 ++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
index 0885c6339d1b..87cec0944e23 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -73,6 +73,17 @@ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
enable-active-high;
regulator-always-on;
};
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_i2c1>;
+ mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
+ los-gpio = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <3000>;
+ status = "okay";
+ };
};
&uart0 {
@@ -195,6 +206,125 @@ &cp0_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
+
+ switch6: switch0@6 {
+ /* Actual device is MV88E6393X */
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ interrupt-parent = <&cp0_gpio1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ label = "p1";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "p2";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "p3";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "p4";
+ phy-handle = <&switch0phy4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "p5";
+ phy-handle = <&switch0phy5>;
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "p6";
+ phy-handle = <&switch0phy6>;
+ };
+
+ port@7 {
+ reg = <7>;
+ label = "p7";
+ phy-handle = <&switch0phy7>;
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "p8";
+ phy-handle = <&switch0phy8>;
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "p9";
+ phy-mode = "10gbase-r";
+ sfp = <&sfp>;
+ managed = "in-band-status";
+ };
+
+ port@a {
+ reg = <10>;
+ label = "cpu";
+ ethernet = <&cp0_eth0>;
+ };
+
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy1: switch0phy1@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy2: switch0phy2@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy3: switch0phy3@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy4: switch0phy4@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy5: switch0phy5@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy6: switch0phy6@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy7: switch0phy7@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy8: switch0phy8@8 {
+ reg = <0x8>;
+ };
+ };
+ };
};
&cp0_xmdio {
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 2/2] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree
@ 2021-12-05 22:56 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-12-05 22:56 UTC (permalink / raw)
To: andrew, gregory.clement, sebastian.hesselbarth, robh+dt, kabel,
linux
Cc: linux-arm-kernel, devicetree, linux-kernel, Chris Packham
The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add
the necessary dts nodes and properties for this.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
This is based on the Marvell SDK. I've re-ordered the port entries to
be in ascending order renamed the wan ports and connected the SFP+.
Change in v3:
- Add review from Russell
- Change port@10 to port@a
- Add maximum-power-milliwatt property to SFP
Changes in v2:
- Remove unused port0
- Label all ports "pN"
- Add interrupt connections
- Add SFP
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 130 ++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
index 0885c6339d1b..87cec0944e23 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -73,6 +73,17 @@ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
enable-active-high;
regulator-always-on;
};
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_i2c1>;
+ mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
+ los-gpio = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <3000>;
+ status = "okay";
+ };
};
&uart0 {
@@ -195,6 +206,125 @@ &cp0_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
+
+ switch6: switch0@6 {
+ /* Actual device is MV88E6393X */
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ interrupt-parent = <&cp0_gpio1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ label = "p1";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "p2";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "p3";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "p4";
+ phy-handle = <&switch0phy4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "p5";
+ phy-handle = <&switch0phy5>;
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "p6";
+ phy-handle = <&switch0phy6>;
+ };
+
+ port@7 {
+ reg = <7>;
+ label = "p7";
+ phy-handle = <&switch0phy7>;
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "p8";
+ phy-handle = <&switch0phy8>;
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "p9";
+ phy-mode = "10gbase-r";
+ sfp = <&sfp>;
+ managed = "in-band-status";
+ };
+
+ port@a {
+ reg = <10>;
+ label = "cpu";
+ ethernet = <&cp0_eth0>;
+ };
+
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy1: switch0phy1@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy2: switch0phy2@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy3: switch0phy3@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy4: switch0phy4@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy5: switch0phy5@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy6: switch0phy6@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy7: switch0phy7@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy8: switch0phy8@8 {
+ reg = <0x8>;
+ };
+ };
+ };
};
&cp0_xmdio {
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 2/2] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree
2021-12-05 22:56 ` Chris Packham
@ 2021-12-06 2:04 ` Andrew Lunn
-1 siblings, 0 replies; 10+ messages in thread
From: Andrew Lunn @ 2021-12-06 2:04 UTC (permalink / raw)
To: Chris Packham
Cc: gregory.clement, sebastian.hesselbarth, robh+dt, kabel, linux,
linux-arm-kernel, devicetree, linux-kernel
On Mon, Dec 06, 2021 at 11:56:18AM +1300, Chris Packham wrote:
> The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add
> the necessary dts nodes and properties for this.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v3 2/2] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree
@ 2021-12-06 2:04 ` Andrew Lunn
0 siblings, 0 replies; 10+ messages in thread
From: Andrew Lunn @ 2021-12-06 2:04 UTC (permalink / raw)
To: Chris Packham
Cc: gregory.clement, sebastian.hesselbarth, robh+dt, kabel, linux,
linux-arm-kernel, devicetree, linux-kernel
On Mon, Dec 06, 2021 at 11:56:18AM +1300, Chris Packham wrote:
> The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add
> the necessary dts nodes and properties for this.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-12-06 2:05 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-12-05 22:56 [PATCH v3 0/2] arm/arm64: dts: Enable more network hardware Chris Packham
2021-12-05 22:56 ` Chris Packham
2021-12-05 22:56 ` [PATCH v3 1/2] arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB Chris Packham
2021-12-05 22:56 ` Chris Packham
2021-12-06 2:03 ` Andrew Lunn
2021-12-06 2:03 ` Andrew Lunn
2021-12-05 22:56 ` [PATCH v3 2/2] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree Chris Packham
2021-12-05 22:56 ` Chris Packham
2021-12-06 2:04 ` Andrew Lunn
2021-12-06 2:04 ` Andrew Lunn
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