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From: Wolfram Sang <wsa@kernel.org>
To: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Jaewon Kim <jaewon02.kim@samsung.com>,
	Chanho Park <chanho61.park@samsung.com>,
	David Virag <virag.david003@gmail.com>,
	Youngmin Nam <youngmin.nam@samsung.com>,
	Arnd Bergmann <arnd@arndb.de>,
	linux-i2c@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v3] i2c: exynos5: Add bus clock support
Date: Thu, 9 Dec 2021 15:49:06 +0100	[thread overview]
Message-ID: <YbIXYinx3J9cfYrr@ninjato> (raw)
In-Reply-To: <20211209140313.14926-1-semen.protsenko@linaro.org>

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On Thu, Dec 09, 2021 at 04:03:13PM +0200, Sam Protsenko wrote:
> In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a
> part of USIv2 block, there are two clocks provided to HSI2C controller:
>   - PCLK: bus clock (APB), provides access to register interface
>   - IPCLK: operating IP-core clock; SCL is derived from this one
> 
> Both clocks have to be asserted for HSI2C to be functional in that case.
> 
> Add code to obtain and enable/disable PCLK in addition to already
> handled operating clock. Make it optional though, as older Exynos SoC
> variants only have one HSI2C clock.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Reviewed-by: Chanho Park <chanho61.park@samsung.com>

Applied to for-next, thanks!


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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa@kernel.org>
To: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Jaewon Kim <jaewon02.kim@samsung.com>,
	Chanho Park <chanho61.park@samsung.com>,
	David Virag <virag.david003@gmail.com>,
	Youngmin Nam <youngmin.nam@samsung.com>,
	Arnd Bergmann <arnd@arndb.de>,
	linux-i2c@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v3] i2c: exynos5: Add bus clock support
Date: Thu, 9 Dec 2021 15:49:06 +0100	[thread overview]
Message-ID: <YbIXYinx3J9cfYrr@ninjato> (raw)
In-Reply-To: <20211209140313.14926-1-semen.protsenko@linaro.org>


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On Thu, Dec 09, 2021 at 04:03:13PM +0200, Sam Protsenko wrote:
> In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a
> part of USIv2 block, there are two clocks provided to HSI2C controller:
>   - PCLK: bus clock (APB), provides access to register interface
>   - IPCLK: operating IP-core clock; SCL is derived from this one
> 
> Both clocks have to be asserted for HSI2C to be functional in that case.
> 
> Add code to obtain and enable/disable PCLK in addition to already
> handled operating clock. Make it optional though, as older Exynos SoC
> variants only have one HSI2C clock.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Reviewed-by: Chanho Park <chanho61.park@samsung.com>

Applied to for-next, thanks!


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  reply	other threads:[~2021-12-09 14:49 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-09 14:03 [PATCH v3] i2c: exynos5: Add bus clock support Sam Protsenko
2021-12-09 14:03 ` Sam Protsenko
2021-12-09 14:49 ` Wolfram Sang [this message]
2021-12-09 14:49   ` Wolfram Sang

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