From: Thierry Reding <thierry.reding@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Rob Herring <robh@kernel.org>, Jon Hunter <jonathanh@nvidia.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy
Date: Tue, 14 Dec 2021 13:27:16 +0100 [thread overview]
Message-ID: <YbiNpJP53FV2rksq@orome> (raw)
In-Reply-To: <8ea071d7-a8ff-813a-6268-7445dbbf0c1a@arm.com>
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On Mon, Nov 29, 2021 at 10:53:37PM +0000, Robin Murphy wrote:
> On 2021-11-29 21:06, Rob Herring wrote:
> > On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
> > > for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
> > > with each cluster having an additional 256 KiB unified L2 cache and a 2
> > > MiB L3 cache.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++-
> > > 1 file changed, 363 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > index 104e5fdd5f8a..db24f48edc9f 100644
> > > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > @@ -736,12 +736,373 @@ cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > - cpu@0 {
> > > + cpu0_0: cpu@0 {
> > > + compatible = "arm,cortex-a78";
> > > device_type = "cpu";
> > > - reg = <0x000>;
> > > + reg = <0x00000>;
> > > enable-method = "psci";
> > > +
> >
> > > + i-cache-size = <65536>;
> > > + i-cache-line-size = <64>;
> > > + i-cache-sets = <256>;
> > > + d-cache-size = <65536>;
> > > + d-cache-line-size = <64>;
> > > + d-cache-sets = <256>;
> >
> > Isn't all this discoverable?
>
> No. The required parameters for cache maintenance by set/way are
> discoverable from the CTR, and if you're particularly lucky they might even
> happen to reflect the underlying physical cache structures, but there's
> absolutely no guarantee of that, and there definitely exist cases where they
> don't.
>
> [...]
> > > + pmu {
> > > + compatible = "arm,armv8-pmuv3";
>
> Oh, I'd missed this - per the current state of things, we should really have
> a proper compatible for the PMU as well.
Good catch! I've changed this to arm,cortex-a78-pmu since that's what
Tegra234 has.
Thanks,
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Rob Herring <robh@kernel.org>, Jon Hunter <jonathanh@nvidia.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy
Date: Tue, 14 Dec 2021 13:27:16 +0100 [thread overview]
Message-ID: <YbiNpJP53FV2rksq@orome> (raw)
In-Reply-To: <8ea071d7-a8ff-813a-6268-7445dbbf0c1a@arm.com>
[-- Attachment #1.1: Type: text/plain, Size: 2170 bytes --]
On Mon, Nov 29, 2021 at 10:53:37PM +0000, Robin Murphy wrote:
> On 2021-11-29 21:06, Rob Herring wrote:
> > On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
> > > for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
> > > with each cluster having an additional 256 KiB unified L2 cache and a 2
> > > MiB L3 cache.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++-
> > > 1 file changed, 363 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > index 104e5fdd5f8a..db24f48edc9f 100644
> > > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > @@ -736,12 +736,373 @@ cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > - cpu@0 {
> > > + cpu0_0: cpu@0 {
> > > + compatible = "arm,cortex-a78";
> > > device_type = "cpu";
> > > - reg = <0x000>;
> > > + reg = <0x00000>;
> > > enable-method = "psci";
> > > +
> >
> > > + i-cache-size = <65536>;
> > > + i-cache-line-size = <64>;
> > > + i-cache-sets = <256>;
> > > + d-cache-size = <65536>;
> > > + d-cache-line-size = <64>;
> > > + d-cache-sets = <256>;
> >
> > Isn't all this discoverable?
>
> No. The required parameters for cache maintenance by set/way are
> discoverable from the CTR, and if you're particularly lucky they might even
> happen to reflect the underlying physical cache structures, but there's
> absolutely no guarantee of that, and there definitely exist cases where they
> don't.
>
> [...]
> > > + pmu {
> > > + compatible = "arm,armv8-pmuv3";
>
> Oh, I'd missed this - per the current state of things, we should really have
> a proper compatible for the PMU as well.
Good catch! I've changed this to arm,cortex-a78-pmu since that's what
Tegra234 has.
Thanks,
Thierry
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next prev parent reply other threads:[~2021-12-14 12:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 13:19 [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Thierry Reding
2021-11-12 13:19 ` Thierry Reding
2021-11-12 13:19 ` [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Thierry Reding
2021-11-12 13:19 ` Thierry Reding
2021-11-29 21:06 ` Rob Herring
2021-11-29 21:06 ` Rob Herring
2021-11-29 22:53 ` Robin Murphy
2021-11-29 22:53 ` Robin Murphy
2021-12-14 12:27 ` Thierry Reding [this message]
2021-12-14 12:27 ` Thierry Reding
2021-11-12 13:39 ` [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Robin Murphy
2021-11-12 13:39 ` Robin Murphy
2021-11-29 21:06 ` Rob Herring
2021-11-29 21:06 ` Rob Herring
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