From: Patrick Williams <patrick@stwcx.xyz>
To: linux-aspeed@lists.ozlabs.org
Subject: [PATCH] ARM: dts: aspeed: update dts of Bletchley platform
Date: Tue, 4 Jan 2022 17:18:22 -0600 [thread overview]
Message-ID: <YdTVvuXiPPRaMw99@heinlein> (raw)
In-Reply-To: <20220104093008.624-1-potin.lai@quantatw.com>
Hi Potin,
A few minor comments. You might want to leave more information in the device
tree for a few of these since they seem like non-obvious settings.
On Tue, Jan 04, 2022 at 05:30:08PM +0800, Potin Lai wrote:
> updates:
> * seperate leds into multiple groups
> * switch sled numbering to 1-based
> * disable inchip rtc
> * add flash1 in fmc
> * switch spi2 pnor using spi-gpio
> * update gpio-line-names
>
> Signed-off-by: Potin Lai <potin.lai@quantatw.com>
> ---
> .../dts/aspeed-bmc-facebook-bletchley.dts | 277 +++++++++++-------
> 1 file changed, 163 insertions(+), 114 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
> index f973ea883b97..d617cfebcb18 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
...
>
> &rtc {
> - status = "okay";
> + status = "disabled";
> };
Since it is more atypical to disable the in-chip RTC would you mind leaving a
comment in the DTS as to why? I see we have the nxp,pcf85263 later on.
> &spi2 {
> status = "okay";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_spi2_default>;
> +
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
> + gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
> + gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
> + num-chipselects = <1>;
> + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
>
> flash at 0 {
> status = "okay";
> m25p,fast-read;
> label = "pnor";
> - spi-max-frequency = <100000000>;
> + spi-max-frequency = <12000000>;
> };
> };
Why is this one being changed to spi-gpio? That is significantly worse
performance. Is there another (non-NOR) SPI device on this bus that is missing
from the device tree?
--
Patrick Williams
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WARNING: multiple messages have this Message-ID (diff)
From: Patrick Williams <patrick@stwcx.xyz>
To: Potin Lai <potin.lai@quantatw.com>
Cc: Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@aj.id.au>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: aspeed: update dts of Bletchley platform
Date: Tue, 4 Jan 2022 17:18:22 -0600 [thread overview]
Message-ID: <YdTVvuXiPPRaMw99@heinlein> (raw)
In-Reply-To: <20220104093008.624-1-potin.lai@quantatw.com>
[-- Attachment #1.1: Type: text/plain, Size: 1997 bytes --]
Hi Potin,
A few minor comments. You might want to leave more information in the device
tree for a few of these since they seem like non-obvious settings.
On Tue, Jan 04, 2022 at 05:30:08PM +0800, Potin Lai wrote:
> updates:
> * seperate leds into multiple groups
> * switch sled numbering to 1-based
> * disable inchip rtc
> * add flash1 in fmc
> * switch spi2 pnor using spi-gpio
> * update gpio-line-names
>
> Signed-off-by: Potin Lai <potin.lai@quantatw.com>
> ---
> .../dts/aspeed-bmc-facebook-bletchley.dts | 277 +++++++++++-------
> 1 file changed, 163 insertions(+), 114 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
> index f973ea883b97..d617cfebcb18 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
...
>
> &rtc {
> - status = "okay";
> + status = "disabled";
> };
Since it is more atypical to disable the in-chip RTC would you mind leaving a
comment in the DTS as to why? I see we have the nxp,pcf85263 later on.
> &spi2 {
> status = "okay";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_spi2_default>;
> +
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
> + gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
> + gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
> + num-chipselects = <1>;
> + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
>
> flash@0 {
> status = "okay";
> m25p,fast-read;
> label = "pnor";
> - spi-max-frequency = <100000000>;
> + spi-max-frequency = <12000000>;
> };
> };
Why is this one being changed to spi-gpio? That is significantly worse
performance. Is there another (non-NOR) SPI device on this bus that is missing
from the device tree?
--
Patrick Williams
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WARNING: multiple messages have this Message-ID (diff)
From: Patrick Williams <patrick@stwcx.xyz>
To: Potin Lai <potin.lai@quantatw.com>
Cc: Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@aj.id.au>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: aspeed: update dts of Bletchley platform
Date: Tue, 4 Jan 2022 17:18:22 -0600 [thread overview]
Message-ID: <YdTVvuXiPPRaMw99@heinlein> (raw)
In-Reply-To: <20220104093008.624-1-potin.lai@quantatw.com>
[-- Attachment #1: Type: text/plain, Size: 1997 bytes --]
Hi Potin,
A few minor comments. You might want to leave more information in the device
tree for a few of these since they seem like non-obvious settings.
On Tue, Jan 04, 2022 at 05:30:08PM +0800, Potin Lai wrote:
> updates:
> * seperate leds into multiple groups
> * switch sled numbering to 1-based
> * disable inchip rtc
> * add flash1 in fmc
> * switch spi2 pnor using spi-gpio
> * update gpio-line-names
>
> Signed-off-by: Potin Lai <potin.lai@quantatw.com>
> ---
> .../dts/aspeed-bmc-facebook-bletchley.dts | 277 +++++++++++-------
> 1 file changed, 163 insertions(+), 114 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
> index f973ea883b97..d617cfebcb18 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
...
>
> &rtc {
> - status = "okay";
> + status = "disabled";
> };
Since it is more atypical to disable the in-chip RTC would you mind leaving a
comment in the DTS as to why? I see we have the nxp,pcf85263 later on.
> &spi2 {
> status = "okay";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_spi2_default>;
> +
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
> + gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
> + gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
> + num-chipselects = <1>;
> + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
>
> flash@0 {
> status = "okay";
> m25p,fast-read;
> label = "pnor";
> - spi-max-frequency = <100000000>;
> + spi-max-frequency = <12000000>;
> };
> };
Why is this one being changed to spi-gpio? That is significantly worse
performance. Is there another (non-NOR) SPI device on this bus that is missing
from the device tree?
--
Patrick Williams
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next prev parent reply other threads:[~2022-01-04 23:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-04 9:30 [PATCH] ARM: dts: aspeed: update dts of Bletchley platform Potin Lai
2022-01-04 9:30 ` Potin Lai
2022-01-04 23:18 ` Patrick Williams [this message]
2022-01-04 23:18 ` Patrick Williams
2022-01-04 23:18 ` Patrick Williams
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