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From: Rob Herring <robh@kernel.org>
To: conor.dooley@microchip.com
Cc: linus.walleij@linaro.org, brgl@bgdev.pl,
	jassisinghbrar@gmail.com, thierry.reding@gmail.com,
	u.kleine-koenig@pengutronix.de, lee.jones@linaro.org,
	a.zummo@towertech.it, alexandre.belloni@bootlin.com,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, geert@linux-m68k.org,
	linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org,
	linux-pwm@vger.kernel.org, linux-rtc@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	krzysztof.kozlowski@canonical.com, bin.meng@windriver.com,
	heiko@sntech.de, lewis.hanly@microchip.com,
	daire.mcnamara@microchip.com, ivan.griffin@microchip.com,
	atishp@rivosinc.com
Subject: Re: [PATCH v5 02/12] dt-bindings: soc/microchip: add services as children of sys ctrlr
Date: Fri, 4 Feb 2022 16:42:19 -0600	[thread overview]
Message-ID: <Yf2ry0ATtYnb5TTx@robh.at.kernel.org> (raw)
In-Reply-To: <20220131114726.973690-3-conor.dooley@microchip.com>

On Mon, Jan 31, 2022 at 11:47:17AM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Add mpfs-rng and mpfs-generic-services as children of the system
> controller.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../microchip,mpfs-sys-controller.yaml        | 41 ++++++++++++++++++-
>  1 file changed, 39 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> index f699772fedf3..5e9977bc114e 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> @@ -13,7 +13,6 @@ description: |
>    The PolarFire SoC system controller is communicated with via a mailbox.
>    This document describes the bindings for the client portion of that mailbox.
>  
> -
>  properties:
>    mboxes:
>      maxItems: 1
> @@ -21,6 +20,38 @@ properties:
>    compatible:
>      const: microchip,mpfs-sys-controller
>  
> +  rng:
> +    type: object
> +
> +    description: |
> +      The hardware random number generator on the Polarfire SoC is
> +      accessed via the mailbox interface provided by the system controller
> +
> +    properties:
> +      compatible:
> +        const: microchip,mpfs-rng
> +
> +    required:
> +      - compatible
> +
> +  sysserv:
> +    type: object
> +
> +    description: |
> +      The PolarFire SoC system controller is communicated with via a mailbox.
> +      This binding represents several of the functions provided by the system
> +      controller which do not belong in a specific subsystem, such as reading
> +      the fpga device certificate, all of which follow the same format:
> +        - a command + optional payload sent to the sys controller
> +        - a status + a payload returned to Linux
> +
> +    properties:
> +      compatible:
> +        const: microchip,mpfs-generic-service
> +
> +    required:
> +      - compatible
> +
>  required:
>    - compatible
>    - mboxes
> @@ -29,7 +60,13 @@ additionalProperties: false
>  
>  examples:
>    - |
> -    syscontroller: syscontroller {
> +    syscontroller {
>        compatible = "microchip,mpfs-sys-controller";
>        mboxes = <&mbox 0>;
> +      rng: rng {
> +        compatible = "microchip,mpfs-rng";
> +      };
> +      sysserv: sysserv {
> +        compatible = "microchip,mpfs-generic-service";
> +      };

You don't have any resources for the child nodes, so they don't need to 
be in DT. Just have the driver for "microchip,mpfs-sys-controller" 
create the sub devices you need.

Rob

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: conor.dooley@microchip.com
Cc: linus.walleij@linaro.org, brgl@bgdev.pl,
	jassisinghbrar@gmail.com, thierry.reding@gmail.com,
	u.kleine-koenig@pengutronix.de, lee.jones@linaro.org,
	a.zummo@towertech.it, alexandre.belloni@bootlin.com,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, geert@linux-m68k.org,
	linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org,
	linux-pwm@vger.kernel.org, linux-rtc@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	krzysztof.kozlowski@canonical.com, bin.meng@windriver.com,
	heiko@sntech.de, lewis.hanly@microchip.com,
	daire.mcnamara@microchip.com, ivan.griffin@microchip.com,
	atishp@rivosinc.com
Subject: Re: [PATCH v5 02/12] dt-bindings: soc/microchip: add services as children of sys ctrlr
Date: Fri, 4 Feb 2022 16:42:19 -0600	[thread overview]
Message-ID: <Yf2ry0ATtYnb5TTx@robh.at.kernel.org> (raw)
In-Reply-To: <20220131114726.973690-3-conor.dooley@microchip.com>

On Mon, Jan 31, 2022 at 11:47:17AM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Add mpfs-rng and mpfs-generic-services as children of the system
> controller.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../microchip,mpfs-sys-controller.yaml        | 41 ++++++++++++++++++-
>  1 file changed, 39 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> index f699772fedf3..5e9977bc114e 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> @@ -13,7 +13,6 @@ description: |
>    The PolarFire SoC system controller is communicated with via a mailbox.
>    This document describes the bindings for the client portion of that mailbox.
>  
> -
>  properties:
>    mboxes:
>      maxItems: 1
> @@ -21,6 +20,38 @@ properties:
>    compatible:
>      const: microchip,mpfs-sys-controller
>  
> +  rng:
> +    type: object
> +
> +    description: |
> +      The hardware random number generator on the Polarfire SoC is
> +      accessed via the mailbox interface provided by the system controller
> +
> +    properties:
> +      compatible:
> +        const: microchip,mpfs-rng
> +
> +    required:
> +      - compatible
> +
> +  sysserv:
> +    type: object
> +
> +    description: |
> +      The PolarFire SoC system controller is communicated with via a mailbox.
> +      This binding represents several of the functions provided by the system
> +      controller which do not belong in a specific subsystem, such as reading
> +      the fpga device certificate, all of which follow the same format:
> +        - a command + optional payload sent to the sys controller
> +        - a status + a payload returned to Linux
> +
> +    properties:
> +      compatible:
> +        const: microchip,mpfs-generic-service
> +
> +    required:
> +      - compatible
> +
>  required:
>    - compatible
>    - mboxes
> @@ -29,7 +60,13 @@ additionalProperties: false
>  
>  examples:
>    - |
> -    syscontroller: syscontroller {
> +    syscontroller {
>        compatible = "microchip,mpfs-sys-controller";
>        mboxes = <&mbox 0>;
> +      rng: rng {
> +        compatible = "microchip,mpfs-rng";
> +      };
> +      sysserv: sysserv {
> +        compatible = "microchip,mpfs-generic-service";
> +      };

You don't have any resources for the child nodes, so they don't need to 
be in DT. Just have the driver for "microchip,mpfs-sys-controller" 
create the sub devices you need.

Rob

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-02-04 22:42 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-31 11:47 [PATCH v5 00/12] Update the Icicle Kit device tree conor.dooley
2022-01-31 11:47 ` conor.dooley
2022-01-31 11:47 ` [PATCH v5 01/12] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-02-04 22:39   ` Rob Herring
2022-02-04 22:39     ` Rob Herring
2022-01-31 11:47 ` [PATCH v5 02/12] dt-bindings: soc/microchip: add services as children of sys ctrlr conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-02-04 22:42   ` Rob Herring [this message]
2022-02-04 22:42     ` Rob Herring
2022-01-31 11:47 ` [PATCH v5 03/12] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 13:37   ` Rob Herring
2022-01-31 13:37     ` Rob Herring
2022-01-31 15:39   ` Rob Herring
2022-01-31 15:39     ` Rob Herring
2022-01-31 15:55     ` Conor.Dooley
2022-01-31 15:55       ` Conor.Dooley
2022-02-04 22:45       ` Rob Herring
2022-02-04 22:45         ` Rob Herring
2022-02-05 11:53         ` Conor Dooley
2022-02-05 11:53           ` Conor Dooley
2022-01-31 11:47 ` [PATCH v5 04/12] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 13:37   ` Rob Herring
2022-01-31 13:37     ` Rob Herring
2022-02-04 22:46   ` Rob Herring
2022-02-04 22:46     ` Rob Herring
2022-01-31 11:47 ` [PATCH v5 05/12] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 13:37   ` Rob Herring
2022-01-31 13:37     ` Rob Herring
2022-01-31 11:47 ` [PATCH v5 06/12] dt-bindings: pwm: add microchip corepwm binding conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 13:37   ` Rob Herring
2022-01-31 13:37     ` Rob Herring
2022-02-01  7:58   ` Uwe Kleine-König
2022-02-01  7:58     ` Uwe Kleine-König
2022-02-02 12:35     ` conor.dooley
2022-02-02 12:35       ` conor.dooley
2022-02-02 13:28       ` Geert Uytterhoeven
2022-02-02 13:28         ` Geert Uytterhoeven
2022-02-02 13:46         ` Conor.Dooley
2022-02-02 13:46           ` Conor.Dooley
2022-02-02 14:02           ` Geert Uytterhoeven
2022-02-02 14:02             ` Geert Uytterhoeven
2022-02-02 14:37             ` Conor.Dooley
2022-02-02 14:37               ` Conor.Dooley
2022-02-05 12:48               ` Conor Dooley
2022-02-05 12:48                 ` Conor Dooley
2022-01-31 11:47 ` [PATCH v5 07/12] riscv: dts: microchip: use clk defines for icicle kit conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 11:47 ` [PATCH v5 08/12] riscv: dts: microchip: add fpga fabric section to " conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 11:47 ` [PATCH v5 09/12] riscv: dts: microchip: refactor icicle kit device tree conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 11:47 ` [PATCH v5 10/12] riscv: dts: microchip: update peripherals in " conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 11:47 ` [PATCH v5 11/12] riscv: dts: microchip: add new peripherals to " conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-01-31 11:47 ` [PATCH v5 12/12] MAINTAINERS: update riscv/microchip entry conor.dooley
2022-01-31 11:47   ` conor.dooley
2022-02-04 18:09 ` [PATCH v5 00/12] Update the Icicle Kit device tree Palmer Dabbelt
2022-02-04 18:09   ` Palmer Dabbelt
2022-02-04 18:47   ` Conor Dooley
2022-02-04 18:47     ` Conor Dooley

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