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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Oleksandr Andrushchenko <Oleksandr_Andrushchenko@epam.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	"julien@xen.org" <julien@xen.org>,
	"sstabellini@kernel.org" <sstabellini@kernel.org>,
	Oleksandr Tyshchenko <Oleksandr_Tyshchenko@epam.com>,
	Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>,
	Artem Mygaiev <Artem_Mygaiev@epam.com>,
	"jbeulich@suse.com" <jbeulich@suse.com>,
	"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>,
	"george.dunlap@citrix.com" <george.dunlap@citrix.com>,
	"paul@xen.org" <paul@xen.org>,
	Bertrand Marquis <bertrand.marquis@arm.com>,
	Rahul Singh <rahul.singh@arm.com>
Subject: Re: [PATCH v5 06/14] vpci/header: implement guest BAR register handlers
Date: Mon, 31 Jan 2022 12:31:10 +0100	[thread overview]
Message-ID: <YffIfj2HcxM6x7Mm@Air-de-Roger> (raw)
In-Reply-To: <6d1772b1-25f1-0f63-8b8a-5dfaf94b2953@epam.com>

On Mon, Jan 31, 2022 at 11:23:48AM +0000, Oleksandr Andrushchenko wrote:
> 
> 
> On 31.01.22 13:10, Roger Pau Monné wrote:
> > On Mon, Jan 31, 2022 at 10:40:47AM +0000, Oleksandr Andrushchenko wrote:
> >> On 31.01.22 11:47, Oleksandr Andrushchenko wrote:
> >>> Hi, Roger!
> >>>
> >>> On 12.01.22 14:35, Roger Pau Monné wrote:
> >>>>> +static void guest_rom_write(const struct pci_dev *pdev, unsigned int reg,
> >>>>> +                            uint32_t val, void *data)
> >>>>> +{
> >>>>> +}
> >>>>> +
> >>>>> +static uint32_t guest_rom_read(const struct pci_dev *pdev, unsigned int reg,
> >>>>> +                               void *data)
> >>>>> +{
> >>>>> +    return 0xffffffff;
> >>>>> +}
> >>>> There should be no need for those handlers. As said elsewhere: for
> >>>> guests registers not explicitly handled should return ~0 for reads and
> >>>> drop writes, which is what you are proposing here.
> >>> Yes, you are right: I can see in vpci_read that we end up reading ~0 if no
> >>> handler exists (which is what I do here with guest_rom_read). But I am not that
> >>> sure about the dropped writes:
> >>>
> >>> void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size,
> >>>                    uint32_t data)
> >>> {
> >>>        unsigned int data_offset = 0;
> >>>
> >>> [snip]
> >>>
> >>>        if ( data_offset < size )
> >>>            /* Tailing gap, write the remaining. */
> >>>            vpci_write_hw(sbdf, reg + data_offset, size - data_offset,
> >>>                          data >> (data_offset * 8));
> >>>
> >>> so it looks like for the un-handled writes we still reach the HW register.
> >>> Could you please tell if the code above needs improvement (like checking
> >>> if the write was handled) or I still need to provide a write handler, e.g.
> >>> guest_rom_write here?
> >> Hm, but the same applies to the reads as well... And this is no surprise,
> >> as for the guests I can see that it accesses all the configuration space
> >> registers that I don't handle. Without that I would have guests unable
> >> to properly setup a PCI device being passed through... And this is why
> >> I have a big TODO in this series describing unhandled registers.
> >> So, it seems that I do need to provide those handlers which I need to
> >> drop writes and return ~0 on reads.
> > Right (see my previous reply to this comment). I think it would be
> > easier (and cleaner) if you switched the default behavior regarding
> > unhandled register access for domUs at the start of the series (drop
> > writes, reads returns ~0), and then you won't need to add all those
> > dummy handler to drop writes and return ~0 for reads.
> >
> > It's going to be more work initially as you would need to support
> > passthrough of more registers, but it's the right approach that we
> > need implementation wise.
> While I agree in general, this effectively means that I'll need to provide
> handling for all PCIe registers and capabilities from the very start.

Well, we can only offer handling of the header and the MSI and MSI-X
capabilities right now, because that's all vPCI currently knows about.

> Otherwise no guest be able to properly initialize a PCI device without that.
> Of course, we may want starting from stubs instead of proper emulation,
> which will direct the access to real HW and later on we add proper emulation.
> But, again, this is going to be a rather big piece of code where we need
> to explicitly handle every possible capability.
> 
> At the moment we are not going to claim that vPCI provides all means to
> pass through a PCI device safely with this respect and this is why the feature
> itself won't even be a tech preview yet. For that reason I think we can still
> have implemented only crucial set of handlers and still allow the rest to
> be read/write directly without emulation.

See my other reply, you can probably move the special handlers into a
separate patch at the end of the series in order to test the
functionality without adding code that will need to be removed when
the defaults for domUs are changed.

> Another question is what needs to be done for vendor specific capabilities?
> How these are going to be emulated?

I think you will need some kind of permissive mode in order to allow a
guest to access those, as they shouldn't be exposed by default.

Thanks, Roger.


  reply	other threads:[~2022-01-31 11:31 UTC|newest]

Thread overview: 130+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-25 11:02 [PATCH v5 00/14] PCI devices passthrough on Arm, part 3 Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 01/14] rangeset: add RANGESETF_no_print flag Oleksandr Andrushchenko
2021-11-25 11:06   ` Jan Beulich
2021-11-25 11:08     ` Oleksandr Andrushchenko
2021-12-15  3:20   ` Volodymyr Babchuk
2021-12-15  5:53     ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 02/14] vpci: fix function attributes for vpci_process_pending Oleksandr Andrushchenko
2021-12-10 17:55   ` Julien Grall
2021-12-11  8:20     ` Roger Pau Monné
2021-12-11  8:57       ` Oleksandr Andrushchenko
2022-01-26  8:31         ` Oleksandr Andrushchenko
2022-01-26 10:54           ` Jan Beulich
2021-11-25 11:02 ` [PATCH v5 03/14] vpci: move lock outside of struct vpci Oleksandr Andrushchenko
2022-01-11 15:17   ` Roger Pau Monné
2022-01-12 14:42     ` Jan Beulich
2022-01-26  8:40       ` Oleksandr Andrushchenko
2022-01-26 11:13         ` Roger Pau Monné
2022-01-31  7:41           ` Oleksandr Andrushchenko
2022-01-12 14:57   ` Jan Beulich
2022-01-12 15:42     ` Roger Pau Monné
2022-01-12 15:52       ` Jan Beulich
2022-01-13  8:58         ` Roger Pau Monné
2022-01-28 14:15           ` Oleksandr Andrushchenko
2022-01-31  8:56             ` Roger Pau Monné
2022-01-31  9:00               ` Oleksandr Andrushchenko
2022-01-28 14:12     ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 04/14] vpci: cancel pending map/unmap on vpci removal Oleksandr Andrushchenko
2022-01-11 16:57   ` Roger Pau Monné
2022-01-12 15:27   ` Jan Beulich
2022-01-28 12:21     ` Oleksandr Andrushchenko
2022-01-31  7:53   ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 05/14] vpci: add hooks for PCI device assign/de-assign Oleksandr Andrushchenko
2022-01-12 12:12   ` Roger Pau Monné
2022-01-31  8:43     ` Oleksandr Andrushchenko
2022-01-13 11:40   ` Roger Pau Monné
2022-01-31  8:45     ` Oleksandr Andrushchenko
2022-02-01  8:56       ` Oleksandr Andrushchenko
2022-02-01 10:23         ` Roger Pau Monné
2021-11-25 11:02 ` [PATCH v5 06/14] vpci/header: implement guest BAR register handlers Oleksandr Andrushchenko
2021-11-25 16:28   ` Bertrand Marquis
2021-11-26 12:19     ` Oleksandr Andrushchenko
2022-02-03 12:36       ` Oleksandr Andrushchenko
2022-02-03 12:44         ` Jan Beulich
2022-02-03 12:48           ` Oleksandr Andrushchenko
2022-02-03 12:50             ` Jan Beulich
2022-02-03 12:53               ` Oleksandr Andrushchenko
2022-01-12 12:35   ` Roger Pau Monné
2022-01-31  9:47     ` Oleksandr Andrushchenko
2022-01-31 10:40       ` Oleksandr Andrushchenko
2022-01-31 10:54         ` Jan Beulich
2022-01-31 11:04           ` Oleksandr Andrushchenko
2022-01-31 11:27             ` Roger Pau Monné
2022-01-31 11:30               ` Oleksandr Andrushchenko
2022-01-31 11:10         ` Roger Pau Monné
2022-01-31 11:23           ` Oleksandr Andrushchenko
2022-01-31 11:31             ` Roger Pau Monné [this message]
2022-01-31 11:39             ` Jan Beulich
2022-01-31 13:30               ` Oleksandr Andrushchenko
2022-01-31 13:36                 ` Jan Beulich
2022-01-31 13:41                   ` Oleksandr Andrushchenko
2022-01-31 13:51                     ` Jan Beulich
2022-01-31 13:58                       ` Oleksandr Andrushchenko
2022-01-31 11:04       ` Roger Pau Monné
2022-01-31 14:51         ` Oleksandr Andrushchenko
2022-01-31 15:06     ` Oleksandr Andrushchenko
2022-01-31 15:50       ` Jan Beulich
2022-02-01  7:31         ` Oleksandr Andrushchenko
2022-02-01 10:10           ` Roger Pau Monné
2022-02-01 10:41             ` Oleksandr Andrushchenko
2022-01-12 17:34   ` Roger Pau Monné
2022-01-31  9:53     ` Oleksandr Andrushchenko
2022-01-31 10:56       ` Roger Pau Monné
2022-02-03 12:45       ` Oleksandr Andrushchenko
2022-02-03 12:54         ` Jan Beulich
2022-02-03 13:30           ` Oleksandr Andrushchenko
2022-02-03 14:04             ` Jan Beulich
2022-02-03 14:19               ` Oleksandr Andrushchenko
2022-02-03 14:05             ` Roger Pau Monné
2022-02-03 14:26               ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 07/14] vpci/header: handle p2m range sets per BAR Oleksandr Andrushchenko
2022-01-12 15:15   ` Roger Pau Monné
2022-01-12 15:18     ` Jan Beulich
2022-02-02  6:44     ` Oleksandr Andrushchenko
2022-02-02  9:56       ` Roger Pau Monné
2022-02-02 10:02         ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 08/14] vpci/header: program p2m with guest BAR view Oleksandr Andrushchenko
2022-01-13 10:22   ` Roger Pau Monné
2022-02-02  8:23     ` Oleksandr Andrushchenko
2022-02-02  9:46       ` Oleksandr Andrushchenko
2022-02-02 10:34         ` Roger Pau Monné
2022-02-02 10:44           ` Oleksandr Andrushchenko
2022-02-02 11:11             ` Jan Beulich
2022-02-02 11:14               ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 09/14] vpci/header: emulate PCI_COMMAND register for guests Oleksandr Andrushchenko
2022-01-13 10:50   ` Roger Pau Monné
2022-02-02 12:49     ` Oleksandr Andrushchenko
2022-02-02 13:32       ` Jan Beulich
2022-02-02 13:47         ` Oleksandr Andrushchenko
2022-02-02 14:18           ` Jan Beulich
2022-02-02 14:26             ` Oleksandr Andrushchenko
2022-02-02 14:31               ` Jan Beulich
2022-02-02 15:04                 ` Oleksandr Andrushchenko
2022-02-02 15:08                   ` Jan Beulich
2022-02-02 15:12                     ` Oleksandr Andrushchenko
2022-02-02 15:31                       ` Jan Beulich
2021-11-25 11:02 ` [PATCH v5 10/14] vpci/header: reset the command register when adding devices Oleksandr Andrushchenko
2022-01-13 11:07   ` Roger Pau Monné
2022-02-02 12:58     ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 11/14] vpci: add initial support for virtual PCI bus topology Oleksandr Andrushchenko
2022-01-12 15:39   ` Jan Beulich
2022-02-02 13:15     ` Oleksandr Andrushchenko
2022-01-13 11:35   ` Roger Pau Monné
2022-02-02 13:17     ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 12/14] xen/arm: translate virtual PCI bus topology for guests Oleksandr Andrushchenko
2022-01-13 12:18   ` Roger Pau Monné
2022-02-02 13:58     ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 13/14] xen/arm: account IO handlers for emulated PCI MSI-X Oleksandr Andrushchenko
2022-01-13 13:23   ` Roger Pau Monné
2022-02-02 14:08     ` Oleksandr Andrushchenko
2021-11-25 11:02 ` [PATCH v5 14/14] vpci: add TODO for the registers not explicitly handled Oleksandr Andrushchenko
2021-11-25 11:17   ` Jan Beulich
2021-11-25 11:20     ` Oleksandr Andrushchenko
2022-01-13 13:27     ` Roger Pau Monné
2022-01-13 13:38       ` Jan Beulich
2022-01-28 13:03         ` Oleksandr Andrushchenko
2021-12-15 11:56 ` [PATCH v5 00/14] PCI devices passthrough on Arm, part 3 Oleksandr Andrushchenko
2021-12-15 12:07   ` Jan Beulich
2021-12-15 12:22     ` Oleksandr Andrushchenko
2021-12-15 14:51       ` Roger Pau Monné
2021-12-15 15:02         ` Oleksandr Andrushchenko

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