* [PATCH v2 01/27] target/ppc: cpu_init: Remove not implemented comments
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 02/27] target/ppc: cpu_init: Remove G2LE init code Fabiano Rosas
` (26 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The /* XXX : not implemented */ comments all over cpu_init are
confusing and ambiguous.
Do they mean not implemented by QEMU, not implemented in a specific
access mode? Not implemented by the CPU? Do they apply to just the
register right after or to a whole block? Do they mean we have an
action to take in the future to implement these? Are they only
informative?
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 582 ++++++++++++++++++------------------------
1 file changed, 253 insertions(+), 329 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1d411b17ee..9bd5971c0c 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -466,95 +466,91 @@ static void register_G2_755_sprs(CPUPPCState *env)
static void register_7xx_sprs(CPUPPCState *env)
{
/* Breakpoints */
- /* XXX : not implemented */
spr_register_kvm(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DABR, 0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Cache management */
- /* XXX : not implemented */
spr_register(env, SPR_ICTC, "ICTC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Performance monitors */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC2, "PMC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC1, "UPMC1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC2, "UPMC2",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC3, "UPMC3",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC4, "UPMC4",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_USIAR, "USIAR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -609,17 +605,16 @@ static void register_iamr_sprs(CPUPPCState *env)
static void register_thrm_sprs(CPUPPCState *env)
{
/* Thermal management */
- /* XXX : not implemented */
spr_register(env, SPR_THRM1, "THRM1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_thrm, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_THRM2, "THRM2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_thrm, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_THRM3, "THRM3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_thrm, &spr_write_generic,
@@ -635,44 +630,41 @@ static void register_604_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_pir,
0x00000000);
/* Breakpoints */
- /* XXX : not implemented */
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register_kvm(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DABR, 0x00000000);
/* Performance counters */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC2, "PMC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_SDA, "SDA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -683,13 +675,11 @@ static void register_604_sprs(CPUPPCState *env)
static void register_603_sprs(CPUPPCState *env)
{
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Breakpoints */
- /* XXX : not implemented */
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -702,7 +692,6 @@ static void register_G2_sprs(CPUPPCState *env)
{
/* Memory base address */
/* MBAR */
- /* XXX : not implemented */
spr_register(env, SPR_MBAR, "MBAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -717,32 +706,31 @@ static void register_G2_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Breakpoints */
- /* XXX : not implemented */
spr_register(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_DABR2, "DABR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IABR2, "IABR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IBCR, "IBCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_DBCR, "DBCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -756,33 +744,32 @@ static void register_74xx_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_74XX_MMCR2, "MMCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX: not implemented */
+
spr_register(env, SPR_BAMR, "BAMR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MSSCR0, "MSSCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -792,7 +779,7 @@ static void register_74xx_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -802,19 +789,16 @@ static void register_74xx_sprs(CPUPPCState *env)
static void register_l3_ctrl(CPUPPCState *env)
{
/* L3CR */
- /* XXX : not implemented */
spr_register(env, SPR_L3CR, "L3CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR0 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR0, "L3ITCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3PM */
- /* XXX : not implemented */
spr_register(env, SPR_L3PM, "L3PM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -901,37 +885,36 @@ static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Debug */
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_IAC1, "IAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC2, "IAC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DAC1, "DAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DAC2, "DAC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_40x_dbcr0,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -944,7 +927,7 @@ static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DBSR, "DBSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_clear,
@@ -1053,7 +1036,6 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
int i;
/* TLB assist registers */
- /* XXX : not implemented */
for (i = 0; i < 8; i++) {
if (mas_mask & (1 << i)) {
spr_register(env, mas_sprn[i], mas_names[i],
@@ -1065,14 +1047,12 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
}
}
if (env->nb_pids > 1) {
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID1, "PID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_booke_pid,
0x00000000);
}
if (env->nb_pids > 2) {
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID2, "PID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_booke_pid,
@@ -1088,7 +1068,6 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
&spr_read_generic, &spr_write_epsc,
0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_MMUCFG, "MMUCFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
@@ -1131,123 +1110,121 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
static void register_440_sprs(CPUPPCState *env)
{
/* Cache control */
- /* XXX : not implemented */
spr_register(env, SPR_440_DNV0, "DNV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DNV1, "DNV1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DNV2, "DNV2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DNV3, "DNV3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DTV0, "DTV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DTV1, "DTV1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DTV2, "DTV2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DTV3, "DTV3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DVLIM, "DVLIM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_INV0, "INV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_INV1, "INV1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_INV2, "INV2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_INV3, "INV3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_ITV0, "ITV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_ITV1, "ITV1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_ITV2, "ITV2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_ITV3, "ITV3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_IVLIM, "IVLIM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Cache debug */
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DBDR, "DBDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1336,23 +1313,22 @@ static void register_405_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00700000);
/* Debug interface */
- /* XXX : not implemented */
spr_register(env, SPR_40x_DBCR0, "DBCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_40x_dbcr0,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_DBCR1, "DBCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_40x_DBSR, "DBSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_clear,
/* Last reset was system reset */
0x00000300);
- /* XXX : not implemented */
+
spr_register(env, SPR_40x_DAC1, "DAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1361,17 +1337,17 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_DVC1, "DVC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_DVC2, "DVC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_40x_IAC1, "IAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1380,18 +1356,17 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Storage control */
- /* XXX: TODO: not implemented */
spr_register(env, SPR_405_SLER, "SLER",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_40x_sler,
@@ -1400,7 +1375,7 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_SU0R, "SU0R",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1446,102 +1421,102 @@ static void register_5xx_8xx_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_decr, &spr_write_decr,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_EIE, "EIE",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_EID, "EID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_NRI, "NRI",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPA, "CMPA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPB, "CMPB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPC, "CMPC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPD, "CMPD",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_ECR, "ECR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DER, "DER",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_COUNTA, "COUNTA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_COUNTB, "COUNTB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPE, "CMPE",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPF, "CMPF",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPG, "CMPG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPH, "CMPH",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_BAR, "BAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DPDR, "DPDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_IMMR, "IMMR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1550,107 +1525,106 @@ static void register_5xx_8xx_sprs(CPUPPCState *env)
static void register_5xx_sprs(CPUPPCState *env)
{
- /* XXX : not implemented */
spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_FPECR, "FPECR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1659,127 +1633,127 @@ static void register_5xx_sprs(CPUPPCState *env)
static void register_8xx_sprs(CPUPPCState *env)
{
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_IC_CST, "IC_CST",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DC_CST, "DC_CST",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_AP, "MI_AP",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_AP, "MD_AP",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_TW, "MD_TW",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2397,27 +2371,27 @@ static void init_proc_440EP(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2430,7 +2404,7 @@ static void init_proc_440EP(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_CCR1, "CCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2539,22 +2513,22 @@ static void init_proc_440GP(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2622,27 +2596,27 @@ static void init_proc_440x5(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2655,7 +2629,7 @@ static void init_proc_440x5(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_CCR1, "CCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2847,23 +2821,21 @@ static void init_proc_G2(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation register */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2926,23 +2898,21 @@ static void init_proc_G2LE(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation register */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3004,84 +2974,84 @@ static void init_proc_e200(CPUPPCState *env)
/* Time base */
register_tbl(env);
register_BookE_sprs(env, 0x000000070000FFFFULL);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
&spr_read_spefscr, &spr_write_spefscr,
&spr_read_spefscr, &spr_write_spefscr,
0x00000000);
/* Memory management */
register_BookE206_sprs(env, 0x0000005D, NULL, 0);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3162,43 +3132,41 @@ static void init_proc_e300(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Breakpoints */
- /* XXX : not implemented */
spr_register(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_DABR2, "DABR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IABR2, "IABR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IBCR, "IBCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_DBCR, "DBCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3304,7 +3272,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
&spr_read_spefscr, &spr_write_spefscr,
&spr_read_spefscr, &spr_write_spefscr,
@@ -3364,47 +3332,47 @@ static void init_proc_e500(CPUPPCState *env, int version)
env->spr[SPR_PVR]);
}
register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_MCAR, "MCAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
@@ -3724,12 +3692,11 @@ static void init_proc_603(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3830,7 +3797,6 @@ static void init_proc_604(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3888,17 +3854,17 @@ static void init_proc_604E(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3906,12 +3872,11 @@ static void init_proc_604E(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3974,12 +3939,11 @@ static void init_proc_740(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4037,7 +4001,7 @@ static void init_proc_750(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4047,12 +4011,11 @@ static void init_proc_750(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4114,7 +4077,7 @@ static void init_proc_750cl(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4135,7 +4098,7 @@ static void init_proc_750cl(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX: not implemented */
+
spr_register(env, SPR_750_TDCL, "TDCL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4145,7 +4108,6 @@ static void init_proc_750cl(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* DMA */
- /* XXX : not implemented */
spr_register(env, SPR_750_WPAR, "WPAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4159,63 +4121,61 @@ static void init_proc_750cl(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750CL_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750CL_HID4, "HID4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Quantization registers */
- /* XXX : not implemented */
spr_register(env, SPR_750_GQR0, "GQR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR1, "GQR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR2, "GQR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR3, "GQR3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR4, "GQR4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR5, "GQR5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR6, "GQR6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR7, "GQR7",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4314,7 +4274,7 @@ static void init_proc_750cx(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4323,18 +4283,17 @@ static void init_proc_750cx(CPUPPCState *env)
register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
- /* This register is not implemented but is present for compatibility */
+
spr_register(env, SPR_SDA, "SDA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4394,7 +4353,7 @@ static void init_proc_750fx(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4403,23 +4362,22 @@ static void init_proc_750fx(CPUPPCState *env)
register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_THRM4, "THRM4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4479,7 +4437,7 @@ static void init_proc_750gx(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented (XXX: different from 750fx) */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4488,23 +4446,22 @@ static void init_proc_750gx(CPUPPCState *env)
register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_THRM4, "THRM4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented (XXX: different from 750fx) */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented (XXX: different from 750fx) */
+
spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4570,17 +4527,16 @@ static void init_proc_745(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4644,12 +4600,11 @@ static void init_proc_755(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* L2 cache control */
- /* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2PMCR, "L2PMCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4657,17 +4612,16 @@ static void init_proc_755(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4732,13 +4686,12 @@ static void init_proc_7400(CPUPPCState *env)
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX: this seems not implemented on all revisions. */
- /* XXX : not implemented */
+
spr_register(env, SPR_MSSCR1, "MSSCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4809,7 +4762,7 @@ static void init_proc_7410(CPUPPCState *env)
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -4817,13 +4770,13 @@ static void init_proc_7410(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* L2PMCR */
- /* XXX : not implemented */
+
spr_register(env, SPR_L2PMCR, "L2PMCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* LDSTDB */
- /* XXX : not implemented */
+
spr_register(env, SPR_LDSTDB, "LDSTDB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4892,46 +4845,42 @@ static void init_proc_7440(CPUPPCState *env)
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5003,69 +4952,61 @@ static void init_proc_7450(CPUPPCState *env)
/* Level 3 cache control */
register_l3_ctrl(env);
/* L3ITCR1 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR2 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR2, "L3ITCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR3 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR3, "L3ITCR3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3OHCR */
- /* XXX : not implemented */
spr_register(env, SPR_L3OHCR, "L3OHCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5135,40 +5076,36 @@ static void init_proc_7445(CPUPPCState *env)
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5274,40 +5211,36 @@ static void init_proc_7455(CPUPPCState *env)
/* Level 3 cache control */
register_l3_ctrl(env);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5413,64 +5346,56 @@ static void init_proc_7457(CPUPPCState *env)
/* Level 3 cache control */
register_l3_ctrl(env);
/* L3ITCR1 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR2 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR2, "L3ITCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR3 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR3, "L3ITCR3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3OHCR */
- /* XXX : not implemented */
spr_register(env, SPR_L3OHCR, "L3OHCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5573,42 +5498,42 @@ static void init_proc_e600(CPUPPCState *env)
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5721,7 +5646,6 @@ static int check_pow_970(CPUPPCState *env)
static void register_970_hid_sprs(CPUPPCState *env)
{
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_clear,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 02/27] target/ppc: cpu_init: Remove G2LE init code
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 01/27] target/ppc: cpu_init: Remove not implemented comments Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 03/27] target/ppc: cpu_init: Group registration of generic SPRs Fabiano Rosas
` (25 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The G2LE CPU initialization code is the same as the G2. Use the latter
for both.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 42 +-----------------------------------------
1 file changed, 1 insertion(+), 41 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 9bd5971c0c..7488001385 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2889,53 +2889,13 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-static void init_proc_G2LE(CPUPPCState *env)
-{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_G2_755_sprs(env);
- register_G2_sprs(env);
- /* Time base */
- register_tbl(env);
- /* External access control */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation register */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- /* Memory management */
- register_low_BATs(env);
- register_high_BATs(env);
- register_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_G2(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
dc->desc = "PowerPC G2LE";
- pcc->init_proc = init_proc_G2LE;
+ pcc->init_proc = init_proc_G2;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 03/27] target/ppc: cpu_init: Group registration of generic SPRs
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 01/27] target/ppc: cpu_init: Remove not implemented comments Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 02/27] target/ppc: cpu_init: Remove G2LE init code Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 04/27] target/ppc: cpu_init: Move Timebase registration into the common function Fabiano Rosas
` (24 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The top level init_proc calls register_generic_sprs but also registers
some other SPRs outside of that function. Let's group everything into
a single place.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 58 ++++++++++++++++++++++++-------------------
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 7488001385..5dc097f2fc 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -150,8 +150,11 @@ static void _spr_register(CPUPPCState *env, int num, const char *name,
oea_read, oea_write, 0, ival)
/* Generic PowerPC SPRs */
-static void register_generic_sprs(CPUPPCState *env)
+static void register_generic_sprs(PowerPCCPU *cpu)
{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+
/* Integer processing */
spr_register(env, SPR_XER, "XER",
&spr_read_xer, &spr_write_xer,
@@ -192,6 +195,32 @@ static void register_generic_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ spr_register(env, SPR_PVR, "PVR",
+ /* Linux permits userspace to read PVR */
+#if defined(CONFIG_LINUX_USER)
+ &spr_read_generic,
+#else
+ SPR_NOACCESS,
+#endif
+ SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->pvr);
+
+ /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
+ if (pcc->svr != POWERPC_SVR_NONE) {
+ if (pcc->svr & POWERPC_SVR_E500) {
+ spr_register(env, SPR_E500_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr & ~POWERPC_SVR_E500);
+ } else {
+ spr_register(env, SPR_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr);
+ }
+ }
}
/* SPR common to all non-embedded PowerPC, including 601 */
@@ -7241,31 +7270,8 @@ static void init_ppc_proc(PowerPCCPU *cpu)
env->tlb_type = TLB_NONE;
#endif
/* Register SPR common to all PowerPC implementations */
- register_generic_sprs(env);
- spr_register(env, SPR_PVR, "PVR",
- /* Linux permits userspace to read PVR */
-#if defined(CONFIG_LINUX_USER)
- &spr_read_generic,
-#else
- SPR_NOACCESS,
-#endif
- SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->pvr);
- /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
- if (pcc->svr != POWERPC_SVR_NONE) {
- if (pcc->svr & POWERPC_SVR_E500) {
- spr_register(env, SPR_E500_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr & ~POWERPC_SVR_E500);
- } else {
- spr_register(env, SPR_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr);
- }
- }
+ register_generic_sprs(cpu);
+
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
(*pcc->init_proc)(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 04/27] target/ppc: cpu_init: Move Timebase registration into the common function
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (2 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 03/27] target/ppc: cpu_init: Group registration of generic SPRs Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 05/27] target/ppc: cpu_init: Avoid nested SPR register functions Fabiano Rosas
` (23 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Now that the 601 was removed, all of our CPUs have a timebase, so that
can be moved into the common function.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 98 ++++++++-----------------------------------
1 file changed, 18 insertions(+), 80 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 5dc097f2fc..b7e460e12d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -221,6 +221,24 @@ static void register_generic_sprs(PowerPCCPU *cpu)
pcc->svr);
}
}
+
+ /* Time base */
+ spr_register(env, SPR_VTBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, &spr_write_tbl,
+ 0x00000000);
+ spr_register(env, SPR_VTBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, &spr_write_tbu,
+ 0x00000000);
}
/* SPR common to all non-embedded PowerPC, including 601 */
@@ -409,27 +427,6 @@ static void register_high_BATs(CPUPPCState *env)
#endif
}
-/* Generic PowerPC time base */
-static void register_tbl(CPUPPCState *env)
-{
- spr_register(env, SPR_VTBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, &spr_write_tbl,
- 0x00000000);
- spr_register(env, SPR_VTBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, &spr_write_tbu,
- 0x00000000);
-}
-
/* Softare table search registers */
static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
@@ -2323,8 +2320,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
static void init_proc_405(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_40x_sprs(env);
register_405_sprs(env);
/* Bus access control */
@@ -2390,8 +2385,6 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
static void init_proc_440EP(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
@@ -2532,8 +2525,6 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
static void init_proc_440GP(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
@@ -2615,8 +2606,6 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
static void init_proc_440x5(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
@@ -2754,8 +2743,6 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
static void init_proc_MPC5xx(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_5xx_8xx_sprs(env);
register_5xx_sprs(env);
init_excp_MPC5xx(env);
@@ -2798,8 +2785,6 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
static void init_proc_MPC8xx(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_5xx_8xx_sprs(env);
register_8xx_sprs(env);
init_excp_MPC8xx(env);
@@ -2847,8 +2832,6 @@ static void init_proc_G2(CPUPPCState *env)
register_sdr1_sprs(env);
register_G2_755_sprs(env);
register_G2_sprs(env);
- /* Time base */
- register_tbl(env);
/* External access control */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -2960,8 +2943,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
static void init_proc_e200(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_BookE_sprs(env, 0x000000070000FFFFULL);
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
@@ -3118,8 +3099,6 @@ static void init_proc_e300(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
- /* Time base */
- register_tbl(env);
/* hardware implementation registers */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3233,8 +3212,6 @@ static void init_proc_e500(CPUPPCState *env, int version)
int i;
#endif
- /* Time base */
- register_tbl(env);
/*
* XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
* complain when accessing them.
@@ -3678,8 +3655,6 @@ static void init_proc_603(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
- /* Time base */
- register_tbl(env);
/* hardware implementation registers */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3783,8 +3758,6 @@ static void init_proc_604(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
- /* Time base */
- register_tbl(env);
/* Hardware implementation registers */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3858,8 +3831,6 @@ static void init_proc_604E(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Hardware implementation registers */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3923,8 +3894,6 @@ static void init_proc_740(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
@@ -3995,8 +3964,6 @@ static void init_proc_750(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
@@ -4071,8 +4038,6 @@ static void init_proc_750cl(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
/* Those registers are fake on 750CL */
spr_register(env, SPR_THRM1, "THRM1",
@@ -4268,8 +4233,6 @@ static void init_proc_750cx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
@@ -4347,8 +4310,6 @@ static void init_proc_750fx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
@@ -4431,8 +4392,6 @@ static void init_proc_750gx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
@@ -4511,8 +4470,6 @@ static void init_proc_745(CPUPPCState *env)
register_sdr1_sprs(env);
register_7xx_sprs(env);
register_G2_755_sprs(env);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
@@ -4586,8 +4543,6 @@ static void init_proc_755(CPUPPCState *env)
register_sdr1_sprs(env);
register_7xx_sprs(env);
register_G2_755_sprs(env);
- /* Time base */
- register_tbl(env);
/* L2 cache control */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4670,8 +4625,6 @@ static void init_proc_7400(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4746,8 +4699,6 @@ static void init_proc_7410(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4829,8 +4780,6 @@ static void init_proc_7440(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4933,8 +4882,6 @@ static void init_proc_7450(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5059,8 +5006,6 @@ static void init_proc_7445(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5192,8 +5137,6 @@ static void init_proc_7455(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5327,8 +5270,6 @@ static void init_proc_7457(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5482,8 +5423,6 @@ static void init_proc_e600(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -6307,7 +6246,6 @@ static void init_tcg_pmu_power8(CPUPPCState *env)
static void init_proc_book3s_common(CPUPPCState *env)
{
register_ne_601_sprs(env);
- register_tbl(env);
register_usprg3_sprs(env);
register_book3s_altivec_sprs(env);
register_book3s_pmu_sup_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 05/27] target/ppc: cpu_init: Avoid nested SPR register functions
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (3 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 04/27] target/ppc: cpu_init: Move Timebase registration into the common function Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 06/27] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs Fabiano Rosas
` (22 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Make sure that every register_*_sprs function only has calls to
spr_register* to register individual SPRs. Do not allow nesting. This
makes the code easier to follow and a look at init_proc_* should
suffice to know what SPRs a CPU has.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index b7e460e12d..1eef006a04 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1128,8 +1128,6 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
break;
}
#endif
-
- register_usprgh_sprs(env);
}
/* SPR specific to PowerPC 440 implementation */
@@ -1427,7 +1425,6 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
- register_usprgh_sprs(env);
}
@@ -2322,6 +2319,7 @@ static void init_proc_405(CPUPPCState *env)
{
register_40x_sprs(env);
register_405_sprs(env);
+ register_usprgh_sprs(env);
/* Bus access control */
/* not emulated, as QEMU never does speculative access */
spr_register(env, SPR_40x_SGR, "SGR",
@@ -2951,6 +2949,7 @@ static void init_proc_e200(CPUPPCState *env)
0x00000000);
/* Memory management */
register_BookE206_sprs(env, 0x0000005D, NULL, 0);
+ register_usprgh_sprs(env);
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3298,6 +3297,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
env->spr[SPR_PVR]);
}
register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
+ register_usprgh_sprs(env);
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 06/27] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (4 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 05/27] target/ppc: cpu_init: Avoid nested SPR register functions Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 07/27] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs Fabiano Rosas
` (21 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1eef006a04..330b765ba9 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1425,6 +1425,18 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Bus access control */
+ /* not emulated, as QEMU never does speculative access */
+ spr_register(env, SPR_40x_SGR, "SGR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0xFFFFFFFF);
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_40x_DCWR, "DCWR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
@@ -2320,17 +2332,7 @@ static void init_proc_405(CPUPPCState *env)
register_40x_sprs(env);
register_405_sprs(env);
register_usprgh_sprs(env);
- /* Bus access control */
- /* not emulated, as QEMU never does speculative access */
- spr_register(env, SPR_40x_SGR, "SGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFFFFFFF);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCWR, "DCWR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 07/27] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (5 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 06/27] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 08/27] target/ppc: cpu_init: Decouple G2 SPR registration from 755 Fabiano Rosas
` (20 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 41 ++++++++++++++++++++++-------------------
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 330b765ba9..29f25e093f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -761,6 +761,28 @@ static void register_G2_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* External access control */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation register */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
}
static void register_74xx_sprs(CPUPPCState *env)
@@ -2832,26 +2854,7 @@ static void init_proc_G2(CPUPPCState *env)
register_sdr1_sprs(env);
register_G2_755_sprs(env);
register_G2_sprs(env);
- /* External access control */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation register */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 08/27] target/ppc: cpu_init: Decouple G2 SPR registration from 755
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (6 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 07/27] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 09/27] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx Fabiano Rosas
` (19 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
We're considering these two to be in different CPU families (6xx and
7xx), so keep their SPR registration separate.
The code was copied into register_G2_sprs and the common function was
renamed to apply only to the 755.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 25 ++++++++++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 29f25e093f..6a367f2bbc 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -466,8 +466,7 @@ static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways
#endif
}
-/* SPR common to MPC755 and G2 */
-static void register_G2_755_sprs(CPUPPCState *env)
+static void register_755_sprs(CPUPPCState *env)
{
/* SGPRs */
spr_register(env, SPR_SPRG4, "SPRG4",
@@ -783,6 +782,23 @@ static void register_G2_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* SGPRs */
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
static void register_74xx_sprs(CPUPPCState *env)
@@ -2852,7 +2868,6 @@ static void init_proc_G2(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_G2_755_sprs(env);
register_G2_sprs(env);
/* Memory management */
@@ -4474,7 +4489,7 @@ static void init_proc_745(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- register_G2_755_sprs(env);
+ register_755_sprs(env);
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
@@ -4547,7 +4562,7 @@ static void init_proc_755(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- register_G2_755_sprs(env);
+ register_755_sprs(env);
/* L2 cache control */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 09/27] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (7 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 08/27] target/ppc: cpu_init: Decouple G2 SPR registration from 755 Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 10/27] target/ppc: cpu_init: Deduplicate 440 SPR registration Fabiano Rosas
` (18 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
We're considering these two to be from different CPU families, so
duplicate some code to keep them separate.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 107 +++++++++++++++++++++++++++++++++++-------
1 file changed, 91 insertions(+), 16 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6a367f2bbc..79cd14d49c 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -803,6 +803,97 @@ static void register_G2_sprs(CPUPPCState *env)
static void register_74xx_sprs(CPUPPCState *env)
{
+ /* Breakpoints */
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
+
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Cache management */
+ spr_register(env, SPR_ICTC, "ICTC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Performance monitors */
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC1, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC2, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC1, "UPMC1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC2, "UPMC2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC3, "UPMC3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC4, "UPMC4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_USIAR, "USIAR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* External access control */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
/* Processor identification */
spr_register(env, SPR_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4644,8 +4735,6 @@ static void init_proc_7400(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4718,8 +4807,6 @@ static void init_proc_7410(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4799,8 +4886,6 @@ static void init_proc_7440(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4901,8 +4986,6 @@ static void init_proc_7450(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5025,8 +5108,6 @@ static void init_proc_7445(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* LDSTCR */
@@ -5156,8 +5237,6 @@ static void init_proc_7455(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5289,8 +5368,6 @@ static void init_proc_7457(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5442,8 +5519,6 @@ static void init_proc_e600(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 10/27] target/ppc: cpu_init: Deduplicate 440 SPR registration
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (8 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 09/27] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 11/27] target/ppc: cpu_init: Deduplicate 603 " Fabiano Rosas
` (17 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Move some of the 440 registers that are being repeated in the 440*
CPUs to register_440_sprs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 100 +++++++++++-------------------------------
1 file changed, 26 insertions(+), 74 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 79cd14d49c..711834a4c1 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1396,6 +1396,32 @@ static void register_440_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
/* SPR shared between PowerPC 40x implementations */
@@ -2517,31 +2543,6 @@ static void init_proc_440EP(CPUPPCState *env)
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -2657,31 +2658,7 @@ static void init_proc_440GP(CPUPPCState *env)
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
@@ -2738,31 +2715,6 @@ static void init_proc_440x5(CPUPPCState *env)
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 11/27] target/ppc: cpu_init: Deduplicate 603 SPR registration
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (9 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 10/27] target/ppc: cpu_init: Deduplicate 440 SPR registration Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 12/27] target/ppc: cpu_init: Deduplicate 604 " Fabiano Rosas
` (16 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 28 +++++++++-------------------
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 711834a4c1..cae4ab69fe 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -710,6 +710,15 @@ static void register_603_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
/* SPR specific to PowerPC G2 implementation */
@@ -3162,16 +3171,6 @@ static void init_proc_e300(CPUPPCState *env)
register_sdr1_sprs(env);
register_603_sprs(env);
/* hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3718,16 +3717,7 @@ static void init_proc_603(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
- /* hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_6xx_7xx_soft_tlb(env, 64, 2);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 12/27] target/ppc: cpu_init: Deduplicate 604 SPR registration
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (10 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 11/27] target/ppc: cpu_init: Deduplicate 603 " Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 13/27] target/ppc: cpu_init: Deduplicate 745/755 " Fabiano Rosas
` (15 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index cae4ab69fe..c54f10cb48 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -694,6 +694,12 @@ static void register_604_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Hardware implementation registers */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
/* SPR specific to PowerPC 603 implementation */
@@ -3811,11 +3817,7 @@ static void init_proc_604(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+
/* Memory management */
register_low_BATs(env);
init_excp_604(env);
@@ -3885,11 +3887,6 @@ static void init_proc_604E(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 13/27] target/ppc: cpu_init: Deduplicate 745/755 SPR registration
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (11 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 12/27] target/ppc: cpu_init: Deduplicate 604 " Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 14/27] target/ppc: cpu_init: Deduplicate 7xx " Fabiano Rosas
` (14 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The 745 and 755 can share the HID registration, so move it all into
register_755_sprs, which applies for both CPUs.
Also rename that function to register_745_sprs, since the 745 is the
earliest of the two. This will help with separating 755-specific
registers in a subsequent patch.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 50 ++++++++++++++++---------------------------
1 file changed, 19 insertions(+), 31 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c54f10cb48..131c2da4c2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -466,7 +466,7 @@ static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways
#endif
}
-static void register_755_sprs(CPUPPCState *env)
+static void register_745_sprs(CPUPPCState *env)
{
/* SGPRs */
spr_register(env, SPR_SPRG4, "SPRG4",
@@ -485,6 +485,22 @@ static void register_755_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Hardware implementation registers */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
/* SPR common to all 7xx PowerPC implementations */
@@ -4519,24 +4535,10 @@ static void init_proc_745(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- register_755_sprs(env);
+ register_745_sprs(env);
/* Thermal management */
register_thrm_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
@@ -4592,7 +4594,7 @@ static void init_proc_755(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- register_755_sprs(env);
+ register_745_sprs(env);
/* L2 cache control */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4605,21 +4607,7 @@ static void init_proc_755(CPUPPCState *env)
0x00000000);
/* Thermal management */
register_thrm_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 14/27] target/ppc: cpu_init: Deduplicate 7xx SPR registration
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (12 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 13/27] target/ppc: cpu_init: Deduplicate 745/755 " Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 15/27] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function Fabiano Rosas
` (13 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 68 +++++++------------------------------------
1 file changed, 11 insertions(+), 57 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 131c2da4c2..ea4ed19bde 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -596,6 +596,17 @@ static void register_7xx_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Hardware implementation registers */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
#ifdef TARGET_PPC64
@@ -3962,16 +3973,7 @@ static void init_proc_740(CPUPPCState *env)
register_7xx_sprs(env);
/* Thermal management */
register_thrm_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
init_excp_7x0(env);
@@ -4032,16 +4034,7 @@ static void init_proc_750(CPUPPCState *env)
0x00000000);
/* Thermal management */
register_thrm_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
/*
@@ -4141,16 +4134,6 @@ static void init_proc_750cl(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_750CL_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4306,16 +4289,7 @@ static void init_proc_750cx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
/* PowerPC 750cx has 8 DBATs and 8 IBATs */
@@ -4384,16 +4358,6 @@ static void init_proc_750fx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4466,16 +4430,6 @@ static void init_proc_750gx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 15/27] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (13 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 14/27] target/ppc: cpu_init: Deduplicate 7xx " Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 16/27] target/ppc: cpu_init: Move e300 SPR registration " Fabiano Rosas
` (12 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
This is just to have 755-specific registers contained into a function,
intead of leaving them open-coded in init_proc_755. It makes init_proc
easier to read and keeps later patches that touch this code a bit
cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ea4ed19bde..d6e19e9cf0 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -503,6 +503,20 @@ static void register_745_sprs(CPUPPCState *env)
0x00000000);
}
+static void register_755_sprs(CPUPPCState *env)
+{
+ /* L2 cache control */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+
+ spr_register(env, SPR_L2PMCR, "L2PMCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
/* SPR common to all 7xx PowerPC implementations */
static void register_7xx_sprs(CPUPPCState *env)
{
@@ -4549,16 +4563,8 @@ static void init_proc_755(CPUPPCState *env)
register_sdr1_sprs(env);
register_7xx_sprs(env);
register_745_sprs(env);
- /* L2 cache control */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
+ register_755_sprs(env);
- spr_register(env, SPR_L2PMCR, "L2PMCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Thermal management */
register_thrm_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 16/27] target/ppc: cpu_init: Move e300 SPR registration into a function
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (14 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 15/27] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 17/27] target/ppc: cpu_init: Move 604e " Fabiano Rosas
` (11 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 64 +++++++++++++++++++++++--------------------
1 file changed, 35 insertions(+), 29 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d6e19e9cf0..63ca83ee7d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -768,6 +768,40 @@ static void register_603_sprs(CPUPPCState *env)
0x00000000);
}
+static void register_e300_sprs(CPUPPCState *env)
+{
+ /* hardware implementation registers */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Breakpoints */
+ spr_register(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_DABR2, "DABR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_IABR2, "IABR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_IBCR, "IBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_DBCR, "DBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
/* SPR specific to PowerPC G2 implementation */
static void register_G2_sprs(CPUPPCState *env)
{
@@ -3217,36 +3251,8 @@ static void init_proc_e300(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
- /* hardware implementation registers */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Breakpoints */
- spr_register(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ register_e300_sprs(env);
- spr_register(env, SPR_DABR2, "DABR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_IABR2, "IABR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_IBCR, "IBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_DBCR, "DBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 17/27] target/ppc: cpu_init: Move 604e SPR registration into a function
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (15 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 16/27] target/ppc: cpu_init: Move e300 SPR registration " Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 18/27] target/ppc: cpu_init: Reuse init_proc_603 for the e300 Fabiano Rosas
` (10 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 43 ++++++++++++++++++++++++-------------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 63ca83ee7d..500db28ebd 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -743,6 +743,29 @@ static void register_604_sprs(CPUPPCState *env)
0x00000000);
}
+static void register_604e_sprs(CPUPPCState *env)
+{
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
/* SPR specific to PowerPC 603 implementation */
static void register_603_sprs(CPUPPCState *env)
{
@@ -3918,26 +3941,8 @@ static void init_proc_604E(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
+ register_604e_sprs(env);
- spr_register(env, SPR_7XX_MMCR1, "MMCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_7XX_PMC3, "PMC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_7XX_PMC4, "PMC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
init_excp_604(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 18/27] target/ppc: cpu_init: Reuse init_proc_603 for the e300
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (16 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 17/27] target/ppc: cpu_init: Move 604e " Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 19/27] target/ppc: cpu_init: Reuse init_proc_604 for the 604e Fabiano Rosas
` (9 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
init_proc_603 is defined after init_proc_e300, so I had to move some
code around to make it work.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 104 +++++++++++++++++++-----------------------
1 file changed, 46 insertions(+), 58 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 500db28ebd..975257c19b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -3269,64 +3269,6 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-static void init_proc_e300(CPUPPCState *env)
-{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_603_sprs(env);
- register_e300_sprs(env);
-
- /* Memory management */
- register_low_BATs(env);
- register_high_BATs(env);
- register_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_603(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e300 core";
- pcc->init_proc = init_proc_e300;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_TGPR) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_AL) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_6xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_603;
- pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
-}
-
enum fsl_e500_version {
fsl_e500v1,
fsl_e500v2,
@@ -3882,6 +3824,52 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
+static void init_proc_e300(CPUPPCState *env)
+{
+ init_proc_603(env);
+ register_e300_sprs(env);
+}
+
+POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e300 core";
+ pcc->init_proc = init_proc_e300;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_TGPR) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_AL) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_6xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_603;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
+}
+
static void init_proc_604(CPUPPCState *env)
{
register_ne_601_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 19/27] target/ppc: cpu_init: Reuse init_proc_604 for the 604e
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (17 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 18/27] target/ppc: cpu_init: Reuse init_proc_603 for the e300 Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 20/27] target/ppc: cpu_init: Reuse init_proc_745 for the 755 Fabiano Rosas
` (8 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 975257c19b..638e16c583 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -3926,18 +3926,8 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
static void init_proc_604E(CPUPPCState *env)
{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_604_sprs(env);
+ init_proc_604(env);
register_604e_sprs(env);
-
- /* Memory management */
- register_low_BATs(env);
- init_excp_604(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 20/27] target/ppc: cpu_init: Reuse init_proc_745 for the 755
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (18 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 19/27] target/ppc: cpu_init: Reuse init_proc_604 for the 604e Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 21/27] target/ppc: cpu_init: Rename register_ne_601_sprs Fabiano Rosas
` (7 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The init_proc_755 function is identical to the 745 one except for the
755-specific registers. I think it is worth it to make them share
code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 18 +-----------------
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 638e16c583..6827160278 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -4548,24 +4548,8 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
static void init_proc_755(CPUPPCState *env)
{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_7xx_sprs(env);
- register_745_sprs(env);
+ init_proc_745(env);
register_755_sprs(env);
-
- /* Thermal management */
- register_thrm_sprs(env);
-
- /* Memory management */
- register_low_BATs(env);
- register_high_BATs(env);
- register_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_7x5(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 21/27] target/ppc: cpu_init: Rename register_ne_601_sprs
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (19 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 20/27] target/ppc: cpu_init: Reuse init_proc_745 for the 755 Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 22/27] target/ppc: cpu_init: Remove register_usprg3_sprs Fabiano Rosas
` (6 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The important part of this function is that it applies to non-embedded
CPUs, not that it also applies to the 601. We removed support for the
601 anyway, so rename this function.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 41 ++++++++++++++++++++---------------------
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6827160278..f464ad64fd 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -241,8 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu)
0x00000000);
}
-/* SPR common to all non-embedded PowerPC, including 601 */
-static void register_ne_601_sprs(CPUPPCState *env)
+static void register_non_embedded_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -3022,7 +3021,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
static void init_proc_G2(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_G2_sprs(env);
@@ -3732,7 +3731,7 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
/* Non-embedded PowerPC */
static void init_proc_603(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
@@ -3872,7 +3871,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
static void init_proc_604(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
@@ -3971,7 +3970,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
static void init_proc_740(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
/* Thermal management */
@@ -4027,7 +4026,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
static void init_proc_750(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4092,7 +4091,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
static void init_proc_750cl(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4277,7 +4276,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
static void init_proc_750cx(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4345,7 +4344,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
static void init_proc_750fx(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4417,7 +4416,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
static void init_proc_750gx(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4489,7 +4488,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
static void init_proc_745(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
register_745_sprs(env);
@@ -4593,7 +4592,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
static void init_proc_7400(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4665,7 +4664,7 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
static void init_proc_7410(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4744,7 +4743,7 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
static void init_proc_7440(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4844,7 +4843,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
static void init_proc_7450(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4966,7 +4965,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
static void init_proc_7445(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5095,7 +5094,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
static void init_proc_7455(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5226,7 +5225,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
static void init_proc_7457(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5377,7 +5376,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
static void init_proc_e600(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -6200,7 +6199,7 @@ static void init_tcg_pmu_power8(CPUPPCState *env)
static void init_proc_book3s_common(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_usprg3_sprs(env);
register_book3s_altivec_sprs(env);
register_book3s_pmu_sup_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 22/27] target/ppc: cpu_init: Remove register_usprg3_sprs
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (20 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 21/27] target/ppc: cpu_init: Rename register_ne_601_sprs Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 23/27] target/ppc: Rename spr_tcg.h to spr_common.h Fabiano Rosas
` (5 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
This function registers just one SPR and has only two callers, so open
code it.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index f464ad64fd..adb23019ef 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1072,14 +1072,6 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-static void register_usprg3_sprs(CPUPPCState *env)
-{
- spr_register(env, SPR_USPRG3, "USPRG3",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
-}
-
static void register_usprgh_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
@@ -3310,7 +3302,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
break;
}
register_BookE_sprs(env, ivor_mask);
- register_usprg3_sprs(env);
+
+ spr_register(env, SPR_USPRG3, "USPRG3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6200,7 +6197,6 @@ static void init_tcg_pmu_power8(CPUPPCState *env)
static void init_proc_book3s_common(CPUPPCState *env)
{
register_non_embedded_sprs(env);
- register_usprg3_sprs(env);
register_book3s_altivec_sprs(env);
register_book3s_pmu_sup_sprs(env);
register_book3s_pmu_user_sprs(env);
@@ -6210,6 +6206,11 @@ static void init_proc_book3s_common(CPUPPCState *env)
* value is the one used by 74xx processors.
*/
vscr_init(env, 0x00010000);
+
+ spr_register(env, SPR_USPRG3, "USPRG3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
}
static void init_proc_970(CPUPPCState *env)
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 23/27] target/ppc: Rename spr_tcg.h to spr_common.h
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (21 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 22/27] target/ppc: cpu_init: Remove register_usprg3_sprs Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 23:34 ` David Gibson
2022-02-16 16:24 ` [PATCH v2 24/27] target/ppc: cpu_init: Expose some SPR registration helpers Fabiano Rosas
` (4 subsequent siblings)
27 siblings, 1 reply; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Initial intent for the spr_tcg header was to expose the spr_read|write
callbacks that are only used by TCG code. However, although these
routines are TCG-specific, the KVM code needs access to env->sprs
which creation is currently coupled to the callback registration.
We are probably not going to decouple SPR creation and TCG callback
registration any time soon, so let's rename the header to spr_common
to accomodate the register_*_sprs functions that will be moved out of
cpu_init.c in the following patches.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/cpu_init.c | 2 +-
target/ppc/{spr_tcg.h => spr_common.h} | 4 ++--
target/ppc/translate.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
rename target/ppc/{spr_tcg.h => spr_common.h} (99%)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index adb23019ef..17f12aceb6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -44,7 +44,7 @@
#include "helper_regs.h"
#include "internal.h"
-#include "spr_tcg.h"
+#include "spr_common.h"
#include "power8-pmu.h"
/* #define PPC_DEBUG_SPR */
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_common.h
similarity index 99%
rename from target/ppc/spr_tcg.h
rename to target/ppc/spr_common.h
index df2abacc64..5aec76ade4 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_common.h
@@ -16,8 +16,8 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef SPR_TCG_H
-#define SPR_TCG_H
+#ifndef SPR_COMMON_H
+#define SPR_COMMON_H
#define SPR_NOACCESS (&spr_noaccess)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2eaffd432a..ecc5a104e0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -35,7 +35,7 @@
#include "exec/translator.h"
#include "exec/log.h"
#include "qemu/atomic128.h"
-#include "spr_tcg.h"
+#include "spr_common.h"
#include "qemu/qemu-print.h"
#include "qapi/error.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v2 23/27] target/ppc: Rename spr_tcg.h to spr_common.h
2022-02-16 16:24 ` [PATCH v2 23/27] target/ppc: Rename spr_tcg.h to spr_common.h Fabiano Rosas
@ 2022-02-16 23:34 ` David Gibson
0 siblings, 0 replies; 31+ messages in thread
From: David Gibson @ 2022-02-16 23:34 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 2546 bytes --]
On Wed, Feb 16, 2022 at 01:24:22PM -0300, Fabiano Rosas wrote:
> Initial intent for the spr_tcg header was to expose the spr_read|write
> callbacks that are only used by TCG code. However, although these
> routines are TCG-specific, the KVM code needs access to env->sprs
> which creation is currently coupled to the callback registration.
>
> We are probably not going to decouple SPR creation and TCG callback
> registration any time soon, so let's rename the header to spr_common
> to accomodate the register_*_sprs functions that will be moved out of
> cpu_init.c in the following patches.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/cpu_init.c | 2 +-
> target/ppc/{spr_tcg.h => spr_common.h} | 4 ++--
> target/ppc/translate.c | 2 +-
> 3 files changed, 4 insertions(+), 4 deletions(-)
> rename target/ppc/{spr_tcg.h => spr_common.h} (99%)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index adb23019ef..17f12aceb6 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -44,7 +44,7 @@
>
> #include "helper_regs.h"
> #include "internal.h"
> -#include "spr_tcg.h"
> +#include "spr_common.h"
> #include "power8-pmu.h"
>
> /* #define PPC_DEBUG_SPR */
> diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_common.h
> similarity index 99%
> rename from target/ppc/spr_tcg.h
> rename to target/ppc/spr_common.h
> index df2abacc64..5aec76ade4 100644
> --- a/target/ppc/spr_tcg.h
> +++ b/target/ppc/spr_common.h
> @@ -16,8 +16,8 @@
> * You should have received a copy of the GNU Lesser General Public
> * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> */
> -#ifndef SPR_TCG_H
> -#define SPR_TCG_H
> +#ifndef SPR_COMMON_H
> +#define SPR_COMMON_H
>
> #define SPR_NOACCESS (&spr_noaccess)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 2eaffd432a..ecc5a104e0 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -35,7 +35,7 @@
> #include "exec/translator.h"
> #include "exec/log.h"
> #include "qemu/atomic128.h"
> -#include "spr_tcg.h"
> +#include "spr_common.h"
>
> #include "qemu/qemu-print.h"
> #include "qapi/error.h"
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2 24/27] target/ppc: cpu_init: Expose some SPR registration helpers
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (22 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 23/27] target/ppc: Rename spr_tcg.h to spr_common.h Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 25/27] target/ppc: cpu_init: Move SPR registration macros to a header Fabiano Rosas
` (3 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The following patches will move CPU-specific code into separate files,
so expose the most used SPR registration functions:
register_sdr1_sprs | 22 callers
register_low_BATs | 20 callers
register_non_embedded_sprs | 19 callers
register_high_BATs | 10 callers
register_thrm_sprs | 8 callers
register_usprgh_sprs | 6 callers
register_6xx_7xx_soft_tlb | only 3 callers, but it helps to
keep the soft TLB code consistent.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 14 +++++++-------
target/ppc/spr_common.h | 8 ++++++++
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 17f12aceb6..cfabf25040 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -241,7 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu)
0x00000000);
}
-static void register_non_embedded_sprs(CPUPPCState *env)
+void register_non_embedded_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -260,7 +260,7 @@ static void register_non_embedded_sprs(CPUPPCState *env)
}
/* Storage Description Register 1 */
-static void register_sdr1_sprs(CPUPPCState *env)
+void register_sdr1_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
if (env->has_hv_mode) {
@@ -283,7 +283,7 @@ static void register_sdr1_sprs(CPUPPCState *env)
}
/* BATs 0-3 */
-static void register_low_BATs(CPUPPCState *env)
+void register_low_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT0U, "IBAT0U",
@@ -355,7 +355,7 @@ static void register_low_BATs(CPUPPCState *env)
}
/* BATs 4-7 */
-static void register_high_BATs(CPUPPCState *env)
+void register_high_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT4U, "IBAT4U",
@@ -427,7 +427,7 @@ static void register_high_BATs(CPUPPCState *env)
}
/* Softare table search registers */
-static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
@@ -667,7 +667,7 @@ static void register_iamr_sprs(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-static void register_thrm_sprs(CPUPPCState *env)
+void register_thrm_sprs(CPUPPCState *env)
{
/* Thermal management */
spr_register(env, SPR_THRM1, "THRM1",
@@ -1072,7 +1072,7 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-static void register_usprgh_sprs(CPUPPCState *env)
+void register_usprgh_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
&spr_read_ureg, SPR_NOACCESS,
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 5aec76ade4..329b7e91a2 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -141,4 +141,12 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
#endif
+void register_low_BATs(CPUPPCState *env);
+void register_high_BATs(CPUPPCState *env);
+void register_sdr1_sprs(CPUPPCState *env);
+void register_thrm_sprs(CPUPPCState *env);
+void register_usprgh_sprs(CPUPPCState *env);
+void register_non_embedded_sprs(CPUPPCState *env);
+void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways);
+
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 25/27] target/ppc: cpu_init: Move SPR registration macros to a header
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (23 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 24/27] target/ppc: cpu_init: Expose some SPR registration helpers Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 16:24 ` [PATCH v2 26/27] target/ppc: cpu_init: Move check_pow and QOM " Fabiano Rosas
` (2 subsequent siblings)
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Put the SPR registration macros in a header that is accessible outside
of cpu_init.c. The following patches will move CPU-specific code to
separate files and will need to access it.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 65 ++++++-----------------------------------
target/ppc/spr_common.h | 56 +++++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 56 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index cfabf25040..4c6b462cad 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -67,35 +67,15 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
* may be compiled out, and the system kvm header may not be available
* for supplying the ID numbers. This is ugly, but the best we can do.
*/
-
-#ifdef CONFIG_TCG
-# define USR_ARG(X) X,
-# ifdef CONFIG_USER_ONLY
-# define SYS_ARG(X)
-# else
-# define SYS_ARG(X) X,
-# endif
-#else
-# define USR_ARG(X)
-# define SYS_ARG(X)
-#endif
-#ifdef CONFIG_KVM
-# define KVM_ARG(X) X,
-#else
-# define KVM_ARG(X)
-#endif
-
-typedef void spr_callback(DisasContext *, int, int);
-
-static void _spr_register(CPUPPCState *env, int num, const char *name,
- USR_ARG(spr_callback *uea_read)
- USR_ARG(spr_callback *uea_write)
- SYS_ARG(spr_callback *oea_read)
- SYS_ARG(spr_callback *oea_write)
- SYS_ARG(spr_callback *hea_read)
- SYS_ARG(spr_callback *hea_write)
- KVM_ARG(uint64_t one_reg_id)
- target_ulong initial_value)
+void _spr_register(CPUPPCState *env, int num, const char *name,
+ USR_ARG(spr_callback *uea_read)
+ USR_ARG(spr_callback *uea_write)
+ SYS_ARG(spr_callback *oea_read)
+ SYS_ARG(spr_callback *oea_write)
+ SYS_ARG(spr_callback *hea_read)
+ SYS_ARG(spr_callback *hea_write)
+ KVM_ARG(uint64_t one_reg_id)
+ target_ulong initial_value)
{
ppc_spr_t *spr = &env->spr_cb[num];
@@ -122,33 +102,6 @@ static void _spr_register(CPUPPCState *env, int num, const char *name,
#endif
}
-/* spr_register_kvm_hv passes all required arguments. */
-#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value) \
- _spr_register(env, num, name, \
- USR_ARG(uea_read) USR_ARG(uea_write) \
- SYS_ARG(oea_read) SYS_ARG(oea_write) \
- SYS_ARG(hea_read) SYS_ARG(hea_write) \
- KVM_ARG(one_reg_id) initial_value)
-
-/* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
-#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, ival) \
- spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
- oea_write, oea_read, oea_write, one_reg_id, ival)
-
-/* spr_register_hv and spr_register are similar, except there is no kvm id. */
-#define spr_register_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, ival) \
- spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
- oea_write, hea_read, hea_write, 0, ival)
-
-#define spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, ival) \
- spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, 0, ival)
-
/* Generic PowerPC SPRs */
static void register_generic_sprs(PowerPCCPU *cpu)
{
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 329b7e91a2..a243c14a11 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -21,6 +21,62 @@
#define SPR_NOACCESS (&spr_noaccess)
+#ifdef CONFIG_TCG
+# define USR_ARG(X) X,
+# ifdef CONFIG_USER_ONLY
+# define SYS_ARG(X)
+# else
+# define SYS_ARG(X) X,
+# endif
+#else
+# define USR_ARG(X)
+# define SYS_ARG(X)
+#endif
+#ifdef CONFIG_KVM
+# define KVM_ARG(X) X,
+#else
+# define KVM_ARG(X)
+#endif
+
+typedef void spr_callback(DisasContext *, int, int);
+
+void _spr_register(CPUPPCState *env, int num, const char *name,
+ USR_ARG(spr_callback *uea_read)
+ USR_ARG(spr_callback *uea_write)
+ SYS_ARG(spr_callback *oea_read)
+ SYS_ARG(spr_callback *oea_write)
+ SYS_ARG(spr_callback *hea_read)
+ SYS_ARG(spr_callback *hea_write)
+ KVM_ARG(uint64_t one_reg_id)
+ target_ulong initial_value);
+
+/* spr_register_kvm_hv passes all required arguments. */
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
+ _spr_register(env, num, name, \
+ USR_ARG(uea_read) USR_ARG(uea_write) \
+ SYS_ARG(oea_read) SYS_ARG(oea_write) \
+ SYS_ARG(hea_read) SYS_ARG(hea_write) \
+ KVM_ARG(one_reg_id) initial_value)
+
+/* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, ival) \
+ spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
+ oea_write, oea_read, oea_write, one_reg_id, ival)
+
+/* spr_register_hv and spr_register are similar, except there is no kvm id. */
+#define spr_register_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, ival) \
+ spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
+ oea_write, hea_read, hea_write, 0, ival)
+
+#define spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, ival) \
+ spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, 0, ival)
+
/* prototypes for readers and writers for SPRs */
void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (24 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 25/27] target/ppc: cpu_init: Move SPR registration macros to a header Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-16 23:35 ` David Gibson
2022-02-16 16:24 ` [PATCH v2 27/27] target/ppc: Move common SPR functions out of cpu_init Fabiano Rosas
2022-02-18 7:42 ` [PATCH v2 00/27] target/ppc: SPR registration cleanups Cédric Le Goater
27 siblings, 1 reply; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
These will need to be accessed from other files once we move the CPUs
code to separate files.
The check_pow_hid0 and check_pow_hid0_74xx are too specific to be
moved to a header so I'll deal with them later when splitting this
code between the multiple CPU families.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/cpu.h | 39 +++++++++++++++++++++++++++++++++++++++
target/ppc/cpu_init.c | 37 -------------------------------------
2 files changed, 39 insertions(+), 37 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 6a06a7f533..1d33e8afea 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2733,4 +2733,43 @@ void dump_mmu(CPUPPCState *env);
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
uint32_t ppc_get_vscr(CPUPPCState *env);
+
+/*****************************************************************************/
+/* Power management enable checks */
+static inline int check_pow_none(CPUPPCState *env)
+{
+ return 0;
+}
+
+static inline int check_pow_nocheck(CPUPPCState *env)
+{
+ return 1;
+}
+
+/*****************************************************************************/
+/* PowerPC implementations definitions */
+
+#define POWERPC_FAMILY(_name) \
+ static void \
+ glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
+ \
+ static const TypeInfo \
+ glue(glue(ppc_, _name), _cpu_family_type_info) = { \
+ .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
+ .parent = TYPE_POWERPC_CPU, \
+ .abstract = true, \
+ .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
+ }; \
+ \
+ static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
+ { \
+ type_register_static( \
+ &glue(glue(ppc_, _name), _cpu_family_type_info)); \
+ } \
+ \
+ type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
+ \
+ static void glue(glue(ppc_, _name), _cpu_family_class_init)
+
+
#endif /* PPC_CPU_H */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 4c6b462cad..5bbbcceb55 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2484,18 +2484,6 @@ static void init_excp_POWER10(CPUPPCState *env)
#endif
-/*****************************************************************************/
-/* Power management enable checks */
-static int check_pow_none(CPUPPCState *env)
-{
- return 0;
-}
-
-static int check_pow_nocheck(CPUPPCState *env)
-{
- return 1;
-}
-
static int check_pow_hid0(CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x00E00000) {
@@ -2514,31 +2502,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
return 0;
}
-/*****************************************************************************/
-/* PowerPC implementations definitions */
-
-#define POWERPC_FAMILY(_name) \
- static void \
- glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
- \
- static const TypeInfo \
- glue(glue(ppc_, _name), _cpu_family_type_info) = { \
- .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
- .parent = TYPE_POWERPC_CPU, \
- .abstract = true, \
- .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
- }; \
- \
- static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
- { \
- type_register_static( \
- &glue(glue(ppc_, _name), _cpu_family_type_info)); \
- } \
- \
- type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
- \
- static void glue(glue(ppc_, _name), _cpu_family_class_init)
-
static void init_proc_405(CPUPPCState *env)
{
register_40x_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v2 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header
2022-02-16 16:24 ` [PATCH v2 26/27] target/ppc: cpu_init: Move check_pow and QOM " Fabiano Rosas
@ 2022-02-16 23:35 ` David Gibson
0 siblings, 0 replies; 31+ messages in thread
From: David Gibson @ 2022-02-16 23:35 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 6304 bytes --]
On Wed, Feb 16, 2022 at 01:24:25PM -0300, Fabiano Rosas wrote:
> These will need to be accessed from other files once we move the CPUs
> code to separate files.
>
> The check_pow_hid0 and check_pow_hid0_74xx are too specific to be
> moved to a header so I'll deal with them later when splitting this
> code between the multiple CPU families.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/cpu.h | 39 +++++++++++++++++++++++++++++++++++++++
> target/ppc/cpu_init.c | 37 -------------------------------------
> 2 files changed, 39 insertions(+), 37 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 6a06a7f533..1d33e8afea 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2733,4 +2733,43 @@ void dump_mmu(CPUPPCState *env);
> void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
> void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
> uint32_t ppc_get_vscr(CPUPPCState *env);
> +
> +/*****************************************************************************/
> +/* Power management enable checks */
> +static inline int check_pow_none(CPUPPCState *env)
> +{
> + return 0;
> +}
> +
> +static inline int check_pow_nocheck(CPUPPCState *env)
> +{
> + return 1;
> +}
> +
> +/*****************************************************************************/
> +/* PowerPC implementations definitions */
> +
> +#define POWERPC_FAMILY(_name) \
> + static void \
> + glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
> + \
> + static const TypeInfo \
> + glue(glue(ppc_, _name), _cpu_family_type_info) = { \
> + .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
> + .parent = TYPE_POWERPC_CPU, \
> + .abstract = true, \
> + .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
> + }; \
> + \
> + static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
> + { \
> + type_register_static( \
> + &glue(glue(ppc_, _name), _cpu_family_type_info)); \
> + } \
> + \
> + type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
> + \
> + static void glue(glue(ppc_, _name), _cpu_family_class_init)
> +
> +
> #endif /* PPC_CPU_H */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 4c6b462cad..5bbbcceb55 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2484,18 +2484,6 @@ static void init_excp_POWER10(CPUPPCState *env)
>
> #endif
>
> -/*****************************************************************************/
> -/* Power management enable checks */
> -static int check_pow_none(CPUPPCState *env)
> -{
> - return 0;
> -}
> -
> -static int check_pow_nocheck(CPUPPCState *env)
> -{
> - return 1;
> -}
> -
> static int check_pow_hid0(CPUPPCState *env)
> {
> if (env->spr[SPR_HID0] & 0x00E00000) {
> @@ -2514,31 +2502,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
> return 0;
> }
>
> -/*****************************************************************************/
> -/* PowerPC implementations definitions */
> -
> -#define POWERPC_FAMILY(_name) \
> - static void \
> - glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
> - \
> - static const TypeInfo \
> - glue(glue(ppc_, _name), _cpu_family_type_info) = { \
> - .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
> - .parent = TYPE_POWERPC_CPU, \
> - .abstract = true, \
> - .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
> - }; \
> - \
> - static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
> - { \
> - type_register_static( \
> - &glue(glue(ppc_, _name), _cpu_family_type_info)); \
> - } \
> - \
> - type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
> - \
> - static void glue(glue(ppc_, _name), _cpu_family_class_init)
> -
> static void init_proc_405(CPUPPCState *env)
> {
> register_40x_sprs(env);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2 27/27] target/ppc: Move common SPR functions out of cpu_init
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (25 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 26/27] target/ppc: cpu_init: Move check_pow and QOM " Fabiano Rosas
@ 2022-02-16 16:24 ` Fabiano Rosas
2022-02-18 7:42 ` [PATCH v2 00/27] target/ppc: SPR registration cleanups Cédric Le Goater
27 siblings, 0 replies; 31+ messages in thread
From: Fabiano Rosas @ 2022-02-16 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Let's leave cpu_init with just generic CPU initialization and
QOM-related functions.
The rest of the SPR registration functions will be moved in the
following patches along with the code that uses them. These are only
the commonly used ones.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 400 --------------------------------------
target/ppc/helper_regs.c | 402 +++++++++++++++++++++++++++++++++++++++
target/ppc/spr_common.h | 1 +
3 files changed, 403 insertions(+), 400 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 5bbbcceb55..bbc88005d8 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -57,367 +57,6 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
ppc_store_vscr(env, val);
}
-/**
- * _spr_register
- *
- * Register an SPR with all the callbacks required for tcg,
- * and the ID number for KVM.
- *
- * The reason for the conditional compilation is that the tcg functions
- * may be compiled out, and the system kvm header may not be available
- * for supplying the ID numbers. This is ugly, but the best we can do.
- */
-void _spr_register(CPUPPCState *env, int num, const char *name,
- USR_ARG(spr_callback *uea_read)
- USR_ARG(spr_callback *uea_write)
- SYS_ARG(spr_callback *oea_read)
- SYS_ARG(spr_callback *oea_write)
- SYS_ARG(spr_callback *hea_read)
- SYS_ARG(spr_callback *hea_write)
- KVM_ARG(uint64_t one_reg_id)
- target_ulong initial_value)
-{
- ppc_spr_t *spr = &env->spr_cb[num];
-
- /* No SPR should be registered twice. */
- assert(spr->name == NULL);
- assert(name != NULL);
-
- spr->name = name;
- spr->default_value = initial_value;
- env->spr[num] = initial_value;
-
-#ifdef CONFIG_TCG
- spr->uea_read = uea_read;
- spr->uea_write = uea_write;
-# ifndef CONFIG_USER_ONLY
- spr->oea_read = oea_read;
- spr->oea_write = oea_write;
- spr->hea_read = hea_read;
- spr->hea_write = hea_write;
-# endif
-#endif
-#ifdef CONFIG_KVM
- spr->one_reg_id = one_reg_id;
-#endif
-}
-
-/* Generic PowerPC SPRs */
-static void register_generic_sprs(PowerPCCPU *cpu)
-{
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- CPUPPCState *env = &cpu->env;
-
- /* Integer processing */
- spr_register(env, SPR_XER, "XER",
- &spr_read_xer, &spr_write_xer,
- &spr_read_xer, &spr_write_xer,
- 0x00000000);
- /* Branch control */
- spr_register(env, SPR_LR, "LR",
- &spr_read_lr, &spr_write_lr,
- &spr_read_lr, &spr_write_lr,
- 0x00000000);
- spr_register(env, SPR_CTR, "CTR",
- &spr_read_ctr, &spr_write_ctr,
- &spr_read_ctr, &spr_write_ctr,
- 0x00000000);
- /* Interrupt processing */
- spr_register(env, SPR_SRR0, "SRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SRR1, "SRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Processor control */
- spr_register(env, SPR_SPRG0, "SPRG0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG1, "SPRG1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG2, "SPRG2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG3, "SPRG3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_PVR, "PVR",
- /* Linux permits userspace to read PVR */
-#if defined(CONFIG_LINUX_USER)
- &spr_read_generic,
-#else
- SPR_NOACCESS,
-#endif
- SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->pvr);
-
- /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
- if (pcc->svr != POWERPC_SVR_NONE) {
- if (pcc->svr & POWERPC_SVR_E500) {
- spr_register(env, SPR_E500_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr & ~POWERPC_SVR_E500);
- } else {
- spr_register(env, SPR_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr);
- }
- }
-
- /* Time base */
- spr_register(env, SPR_VTBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, &spr_write_tbl,
- 0x00000000);
- spr_register(env, SPR_VTBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, &spr_write_tbu,
- 0x00000000);
-}
-
-void register_non_embedded_sprs(CPUPPCState *env)
-{
- /* Exception processing */
- spr_register_kvm(env, SPR_DSISR, "DSISR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DSISR, 0x00000000);
- spr_register_kvm(env, SPR_DAR, "DAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DAR, 0x00000000);
- /* Timer */
- spr_register(env, SPR_DECR, "DECR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_decr, &spr_write_decr,
- 0x00000000);
-}
-
-/* Storage Description Register 1 */
-void register_sdr1_sprs(CPUPPCState *env)
-{
-#ifndef CONFIG_USER_ONLY
- if (env->has_hv_mode) {
- /*
- * SDR1 is a hypervisor resource on CPUs which have a
- * hypervisor mode
- */
- spr_register_hv(env, SPR_SDR1, "SDR1",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_sdr1,
- 0x00000000);
- } else {
- spr_register(env, SPR_SDR1, "SDR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_sdr1,
- 0x00000000);
- }
-#endif
-}
-
-/* BATs 0-3 */
-void register_low_BATs(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_IBAT0U, "IBAT0U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT0L, "IBAT0L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT1U, "IBAT1U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT1L, "IBAT1L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT2U, "IBAT2U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT2L, "IBAT2L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT3U, "IBAT3U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT3L, "IBAT3L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_DBAT0U, "DBAT0U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT0L, "DBAT0L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT1U, "DBAT1U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT1L, "DBAT1L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT2U, "DBAT2U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT2L, "DBAT2L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT3U, "DBAT3U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT3L, "DBAT3L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- env->nb_BATs += 4;
-#endif
-}
-
-/* BATs 4-7 */
-void register_high_BATs(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_IBAT4U, "IBAT4U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT4L, "IBAT4L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT5U, "IBAT5U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT5L, "IBAT5L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT6U, "IBAT6U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT6L, "IBAT6L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT7U, "IBAT7U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT7L, "IBAT7L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT4U, "DBAT4U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT4L, "DBAT4L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT5U, "DBAT5U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT5L, "DBAT5L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT6U, "DBAT6U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT6L, "DBAT6L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT7U, "DBAT7U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT7L, "DBAT7L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- env->nb_BATs += 4;
-#endif
-}
-
-/* Softare table search registers */
-void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = nb_tlbs;
- env->nb_ways = nb_ways;
- env->id_tlbs = 1;
- env->tlb_type = TLB_6XX;
- spr_register(env, SPR_DMISS, "DMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_DCMP, "DCMP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_HASH1, "HASH1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_HASH2, "HASH2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_IMISS, "IMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_ICMP, "ICMP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_RPA, "RPA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#endif
-}
-
static void register_745_sprs(CPUPPCState *env)
{
/* SGPRs */
@@ -620,25 +259,6 @@ static void register_iamr_sprs(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-void register_thrm_sprs(CPUPPCState *env)
-{
- /* Thermal management */
- spr_register(env, SPR_THRM1, "THRM1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_THRM2, "THRM2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_THRM3, "THRM3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
-}
-
/* SPR specific to PowerPC 604 implementation */
static void register_604_sprs(CPUPPCState *env)
{
@@ -1025,26 +645,6 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-void register_usprgh_sprs(CPUPPCState *env)
-{
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
-}
-
/* PowerPC BookE SPR */
static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
{
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 38fcb5fe50..9a691d6833 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -24,6 +24,8 @@
#include "sysemu/kvm.h"
#include "helper_regs.h"
#include "power8-pmu.h"
+#include "cpu-models.h"
+#include "spr_common.h"
/* Swap temporary saved registers with GPRs */
void hreg_swap_gpr_tgpr(CPUPPCState *env)
@@ -302,3 +304,403 @@ void check_tlb_flush(CPUPPCState *env, bool global)
}
}
#endif
+
+/**
+ * _spr_register
+ *
+ * Register an SPR with all the callbacks required for tcg,
+ * and the ID number for KVM.
+ *
+ * The reason for the conditional compilation is that the tcg functions
+ * may be compiled out, and the system kvm header may not be available
+ * for supplying the ID numbers. This is ugly, but the best we can do.
+ */
+void _spr_register(CPUPPCState *env, int num, const char *name,
+ USR_ARG(spr_callback *uea_read)
+ USR_ARG(spr_callback *uea_write)
+ SYS_ARG(spr_callback *oea_read)
+ SYS_ARG(spr_callback *oea_write)
+ SYS_ARG(spr_callback *hea_read)
+ SYS_ARG(spr_callback *hea_write)
+ KVM_ARG(uint64_t one_reg_id)
+ target_ulong initial_value)
+{
+ ppc_spr_t *spr = &env->spr_cb[num];
+
+ /* No SPR should be registered twice. */
+ assert(spr->name == NULL);
+ assert(name != NULL);
+
+ spr->name = name;
+ spr->default_value = initial_value;
+ env->spr[num] = initial_value;
+
+#ifdef CONFIG_TCG
+ spr->uea_read = uea_read;
+ spr->uea_write = uea_write;
+# ifndef CONFIG_USER_ONLY
+ spr->oea_read = oea_read;
+ spr->oea_write = oea_write;
+ spr->hea_read = hea_read;
+ spr->hea_write = hea_write;
+# endif
+#endif
+#ifdef CONFIG_KVM
+ spr->one_reg_id = one_reg_id;
+#endif
+}
+
+/* Generic PowerPC SPRs */
+void register_generic_sprs(PowerPCCPU *cpu)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+
+ /* Integer processing */
+ spr_register(env, SPR_XER, "XER",
+ &spr_read_xer, &spr_write_xer,
+ &spr_read_xer, &spr_write_xer,
+ 0x00000000);
+ /* Branch control */
+ spr_register(env, SPR_LR, "LR",
+ &spr_read_lr, &spr_write_lr,
+ &spr_read_lr, &spr_write_lr,
+ 0x00000000);
+ spr_register(env, SPR_CTR, "CTR",
+ &spr_read_ctr, &spr_write_ctr,
+ &spr_read_ctr, &spr_write_ctr,
+ 0x00000000);
+ /* Interrupt processing */
+ spr_register(env, SPR_SRR0, "SRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SRR1, "SRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Processor control */
+ spr_register(env, SPR_SPRG0, "SPRG0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG1, "SPRG1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG2, "SPRG2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG3, "SPRG3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_PVR, "PVR",
+ /* Linux permits userspace to read PVR */
+#if defined(CONFIG_LINUX_USER)
+ &spr_read_generic,
+#else
+ SPR_NOACCESS,
+#endif
+ SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->pvr);
+
+ /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
+ if (pcc->svr != POWERPC_SVR_NONE) {
+ if (pcc->svr & POWERPC_SVR_E500) {
+ spr_register(env, SPR_E500_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr & ~POWERPC_SVR_E500);
+ } else {
+ spr_register(env, SPR_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr);
+ }
+ }
+
+ /* Time base */
+ spr_register(env, SPR_VTBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, &spr_write_tbl,
+ 0x00000000);
+ spr_register(env, SPR_VTBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, &spr_write_tbu,
+ 0x00000000);
+}
+
+void register_non_embedded_sprs(CPUPPCState *env)
+{
+ /* Exception processing */
+ spr_register_kvm(env, SPR_DSISR, "DSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSISR, 0x00000000);
+ spr_register_kvm(env, SPR_DAR, "DAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAR, 0x00000000);
+ /* Timer */
+ spr_register(env, SPR_DECR, "DECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_decr, &spr_write_decr,
+ 0x00000000);
+}
+
+/* Storage Description Register 1 */
+void register_sdr1_sprs(CPUPPCState *env)
+{
+#ifndef CONFIG_USER_ONLY
+ if (env->has_hv_mode) {
+ /*
+ * SDR1 is a hypervisor resource on CPUs which have a
+ * hypervisor mode
+ */
+ spr_register_hv(env, SPR_SDR1, "SDR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_sdr1,
+ 0x00000000);
+ } else {
+ spr_register(env, SPR_SDR1, "SDR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_sdr1,
+ 0x00000000);
+ }
+#endif
+}
+
+/* BATs 0-3 */
+void register_low_BATs(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_IBAT0U, "IBAT0U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT0L, "IBAT0L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT1U, "IBAT1U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT1L, "IBAT1L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT2U, "IBAT2U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT2L, "IBAT2L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT3U, "IBAT3U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT3L, "IBAT3L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT0U, "DBAT0U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT0L, "DBAT0L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT1U, "DBAT1U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT1L, "DBAT1L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT2U, "DBAT2U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT2L, "DBAT2L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT3U, "DBAT3U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT3L, "DBAT3L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ env->nb_BATs += 4;
+#endif
+}
+
+/* BATs 4-7 */
+void register_high_BATs(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_IBAT4U, "IBAT4U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT4L, "IBAT4L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT5U, "IBAT5U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT5L, "IBAT5L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT6U, "IBAT6U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT6L, "IBAT6L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT7U, "IBAT7U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT7L, "IBAT7L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT4U, "DBAT4U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT4L, "DBAT4L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT5U, "DBAT5U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT5L, "DBAT5L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT6U, "DBAT6U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT6L, "DBAT6L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT7U, "DBAT7U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT7L, "DBAT7L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ env->nb_BATs += 4;
+#endif
+}
+
+/* Softare table search registers */
+void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = nb_tlbs;
+ env->nb_ways = nb_ways;
+ env->id_tlbs = 1;
+ env->tlb_type = TLB_6XX;
+ spr_register(env, SPR_DMISS, "DMISS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_DCMP, "DCMP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_HASH1, "HASH1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_HASH2, "HASH2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_IMISS, "IMISS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_ICMP, "ICMP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_RPA, "RPA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#endif
+}
+
+void register_thrm_sprs(CPUPPCState *env)
+{
+ /* Thermal management */
+ spr_register(env, SPR_THRM1, "THRM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_THRM2, "THRM2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_THRM3, "THRM3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+}
+
+void register_usprgh_sprs(CPUPPCState *env)
+{
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index a243c14a11..b5a5bc6895 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -204,5 +204,6 @@ void register_thrm_sprs(CPUPPCState *env);
void register_usprgh_sprs(CPUPPCState *env);
void register_non_embedded_sprs(CPUPPCState *env);
void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways);
+void register_generic_sprs(PowerPCCPU *cpu);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v2 00/27] target/ppc: SPR registration cleanups
2022-02-16 16:23 [PATCH v2 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
` (26 preceding siblings ...)
2022-02-16 16:24 ` [PATCH v2 27/27] target/ppc: Move common SPR functions out of cpu_init Fabiano Rosas
@ 2022-02-18 7:42 ` Cédric Le Goater
27 siblings, 0 replies; 31+ messages in thread
From: Cédric Le Goater @ 2022-02-18 7:42 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 2/16/22 17:23, Fabiano Rosas wrote:
> The goal of this series is to do some untangling of SPR registration
> code in cpu_init.c and prepare for moving the CPU initialization into
> separate files for each CPU family.
>
> After this series we'll have only cpu-specific SPR code in cpu_init.c,
> i.e. code that can be split and moved as a unit into other
> files. Common/generic SPR code will be in helper_regs.c, exposed via
> spr_common.h.
>
> Changes from v1:
>
> - Some commit message improvements suggested by David;
>
> - Removed the soft_tlb rename patch. Kept the old name;
>
> - Left the specific check_pow functions behind, they can be dealt with
> in the next series;
>
> - Added a new patch to rename spr_tcg to spr_common.
>
> Patches 23 and 26 still need review.
>
> This series is based on legoater/ppc7.0.
>
> v1:
> https://lists.nongnu.org/archive/html/qemu-ppc/2022-02/msg00313.html
>
> Fabiano Rosas (27):
> target/ppc: cpu_init: Remove not implemented comments
> target/ppc: cpu_init: Remove G2LE init code
> target/ppc: cpu_init: Group registration of generic SPRs
> target/ppc: cpu_init: Move Timebase registration into the common
> function
> target/ppc: cpu_init: Avoid nested SPR register functions
> target/ppc: cpu_init: Move 405 SPRs into register_405_sprs
> target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs
> target/ppc: cpu_init: Decouple G2 SPR registration from 755
> target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx
> target/ppc: cpu_init: Deduplicate 440 SPR registration
> target/ppc: cpu_init: Deduplicate 603 SPR registration
> target/ppc: cpu_init: Deduplicate 604 SPR registration
> target/ppc: cpu_init: Deduplicate 745/755 SPR registration
> target/ppc: cpu_init: Deduplicate 7xx SPR registration
> target/ppc: cpu_init: Move 755 L2 cache SPRs into a function
> target/ppc: cpu_init: Move e300 SPR registration into a function
> target/ppc: cpu_init: Move 604e SPR registration into a function
> target/ppc: cpu_init: Reuse init_proc_603 for the e300
> target/ppc: cpu_init: Reuse init_proc_604 for the 604e
> target/ppc: cpu_init: Reuse init_proc_745 for the 755
> target/ppc: cpu_init: Rename register_ne_601_sprs
> target/ppc: cpu_init: Remove register_usprg3_sprs
> target/ppc: Rename spr_tcg.h to spr_common.h
> target/ppc: cpu_init: Expose some SPR registration helpers
> target/ppc: cpu_init: Move SPR registration macros to a header
> target/ppc: cpu_init: Move check_pow and QOM macros to a header
> target/ppc: Move common SPR functions out of cpu_init
>
> target/ppc/cpu.h | 39 +
> target/ppc/cpu_init.c | 1879 ++++++++----------------
> target/ppc/helper_regs.c | 402 +++++
> target/ppc/{spr_tcg.h => spr_common.h} | 69 +-
> target/ppc/translate.c | 2 +-
> 5 files changed, 1098 insertions(+), 1293 deletions(-)
> rename target/ppc/{spr_tcg.h => spr_common.h} (72%)
>
Applied for ppc-7.0
Thanks,
C.
^ permalink raw reply [flat|nested] 31+ messages in thread