From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i195: Fix dbuf slice config lookup
Date: Mon, 7 Feb 2022 18:47:55 +0200 [thread overview]
Message-ID: <YgFNOzZDOWn7UryH@intel.com> (raw)
In-Reply-To: <20220207132700.481-1-ville.syrjala@linux.intel.com>
On Mon, Feb 07, 2022 at 03:26:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently I totally fumbled the loop condition when I
> removed the ARRAY_SIZE() stuff from the dbuf slice config
> lookup. Comparing the loop index with the active_pipes bitmask
> is utter nonsense, what we want to do is check to see if the
> mask is zero or not.
>
> Cc: stable@vger.kernel.org
> Fixes: 05e8155afe35 ("drm/i915: Use a sentinel to terminate the dbuf slice arrays")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 02084652fe3d..da721aea70ff 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4848,7 +4848,7 @@ static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus,
> {
> int i;
>
> - for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
> + for (i = 0; dbuf_slices[i].active_pipes != 0; i++) {
Actually looks like the tables just happened to be ordered
the right way that the code never did the wrong thing until
commit eef173954432 ("drm/i915: Allow !join_mbus cases for adlp+
dbuf configuration"). So this just needs backporting alongside
that commit (which I flagged for 5.14+), but no crucial need to
backport further than that.
--
Ville Syrjälä
Intel
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
Subject: Re: [PATCH 1/2] drm/i195: Fix dbuf slice config lookup
Date: Mon, 7 Feb 2022 18:47:55 +0200 [thread overview]
Message-ID: <YgFNOzZDOWn7UryH@intel.com> (raw)
In-Reply-To: <20220207132700.481-1-ville.syrjala@linux.intel.com>
On Mon, Feb 07, 2022 at 03:26:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently I totally fumbled the loop condition when I
> removed the ARRAY_SIZE() stuff from the dbuf slice config
> lookup. Comparing the loop index with the active_pipes bitmask
> is utter nonsense, what we want to do is check to see if the
> mask is zero or not.
>
> Cc: stable@vger.kernel.org
> Fixes: 05e8155afe35 ("drm/i915: Use a sentinel to terminate the dbuf slice arrays")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 02084652fe3d..da721aea70ff 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4848,7 +4848,7 @@ static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus,
> {
> int i;
>
> - for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
> + for (i = 0; dbuf_slices[i].active_pipes != 0; i++) {
Actually looks like the tables just happened to be ordered
the right way that the code never did the wrong thing until
commit eef173954432 ("drm/i915: Allow !join_mbus cases for adlp+
dbuf configuration"). So this just needs backporting alongside
that commit (which I flagged for 5.14+), but no crucial need to
backport further than that.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2022-02-07 16:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-07 13:26 [Intel-gfx] [PATCH 1/2] drm/i195: Fix dbuf slice config lookup Ville Syrjala
2022-02-07 13:26 ` Ville Syrjala
2022-02-07 13:27 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix mbus join " Ville Syrjala
2022-02-07 13:27 ` Ville Syrjala
2022-02-08 14:10 ` [Intel-gfx] " Jani Nikula
2022-02-07 15:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i195: Fix dbuf slice " Patchwork
2022-02-07 16:47 ` Ville Syrjälä [this message]
2022-02-07 16:47 ` [PATCH 1/2] " Ville Syrjälä
2022-02-07 18:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
2022-02-08 14:10 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
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