From: Abel Vesa <abel.vesa@nxp.com>
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc: sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com, linux-imx@nxp.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH 2/4] clk: imx: add i.MX93 composite clk
Date: Mon, 21 Feb 2022 14:09:48 +0200 [thread overview]
Message-ID: <YhOBDJDdL0Z2tk/j@abelvesa> (raw)
In-Reply-To: <20220215081835.790311-3-peng.fan@oss.nxp.com>
On 22-02-15 16:18:33, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here
> is to combine all these into one composite clk and simplify clk tree.
> i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/clk/imx/Makefile | 1 +
> drivers/clk/imx/clk-composite-93.c | 93 ++++++++++++++++++++++++++++++
> drivers/clk/imx/clk.h | 9 +++
> 3 files changed, 103 insertions(+)
> create mode 100644 drivers/clk/imx/clk-composite-93.c
>
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index b5e040026dfb..15549a1c332f 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -4,6 +4,7 @@ mxc-clk-objs += clk.o
> mxc-clk-objs += clk-busy.o
> mxc-clk-objs += clk-composite-7ulp.o
> mxc-clk-objs += clk-composite-8m.o
> +mxc-clk-objs += clk-composite-93.o
> mxc-clk-objs += clk-cpu.o
> mxc-clk-objs += clk-divider-gate.o
> mxc-clk-objs += clk-fixup-div.o
> diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c
> new file mode 100644
> index 000000000000..b44619aa5ca5
> --- /dev/null
> +++ b/drivers/clk/imx/clk-composite-93.c
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + *
> + * Peng Fan <peng.fan@nxp.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/errno.h>
> +#include <linux/export.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +
> +#include "clk.h"
> +
> +#define CCM_DIV_SHIFT 0
> +#define CCM_DIV_WIDTH 8
> +#define CCM_MUX_SHIFT 8
> +#define CCM_MUX_MASK 3
> +#define CCM_OFF_SHIFT 24
> +
> +#define AUTHEN_OFFSET 0x30
> +#define TZ_NS_SHIFT 9
> +#define TZ_NS_MASK BIT(9)
> +
> +struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names,
> + int num_parents, void __iomem *reg,
> + unsigned long flags)
> +{
> + struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
> + struct clk_hw *div_hw, *gate_hw;
> + struct clk_divider *div = NULL;
> + struct clk_gate *gate = NULL;
> + struct clk_mux *mux = NULL;
> + bool clk_ro = false;
> +
> + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> + if (!mux)
> + goto fail;
> +
> + mux_hw = &mux->hw;
> + mux->reg = reg;
> + mux->shift = CCM_MUX_SHIFT;
> + mux->mask = CCM_MUX_MASK;
> + mux->lock = &imx_ccm_lock;
> +
> + div = kzalloc(sizeof(*div), GFP_KERNEL);
> + if (!div)
> + goto fail;
> +
> + div_hw = &div->hw;
> + div->reg = reg;
> + div->shift = CCM_DIV_SHIFT;
> + div->width = CCM_DIV_WIDTH;
> + div->lock = &imx_ccm_lock;
> + div->flags = CLK_DIVIDER_ROUND_CLOSEST;
> +
> + if (!(readl(reg + AUTHEN_OFFSET) & TZ_NS_MASK))
> + clk_ro = true;
> +
> + if (clk_ro) {
> + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> + mux_hw, &clk_mux_ro_ops, div_hw,
> + &clk_divider_ro_ops, NULL, NULL, flags);
> + } else {
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + goto fail;
> +
> + gate_hw = &gate->hw;
> + gate->reg = reg;
> + gate->bit_idx = CCM_OFF_SHIFT;
> + gate->lock = &imx_ccm_lock;
> + gate->flags = CLK_GATE_SET_TO_DISABLE;
> +
> + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> + mux_hw, &clk_mux_ops, div_hw,
> + &clk_divider_ops, gate_hw,
> + &clk_gate_ops, flags | CLK_SET_RATE_NO_REPARENT);
Just a thought. Could we just extend the imx8m_composite to do this, instead
of adding this new one? I mean, just because it is a new SoC, doesn't
mean we can't reuse the imx8m composite.
> + }
> +
> + if (IS_ERR(hw))
> + goto fail;
> +
> + return hw;
> +
> +fail:
> + kfree(gate);
> + kfree(div);
> + kfree(mux);
> + return ERR_CAST(hw);
> +}
> +EXPORT_SYMBOL_GPL(imx93_clk_composite_flags);
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index 7d220a01de1f..63eb7c53b123 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -419,6 +419,15 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
> IMX_COMPOSITE_FW_MANAGED, \
> IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE)
>
> +struct clk_hw *imx93_clk_composite_flags(const char *name,
> + const char * const *parent_names,
> + int num_parents,
> + void __iomem *reg,
> + unsigned long flags);
> +#define imx93_clk_composite(name, parent_names, num_parents, reg) \
> + imx93_clk_composite_flags(name, parent_names, num_parents, reg, \
> + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
> +
> struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
> unsigned long flags, void __iomem *reg, u8 shift, u8 width,
> u8 clk_divider_flags, const struct clk_div_table *table,
> --
> 2.25.1
>
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@nxp.com>
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc: sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com, linux-imx@nxp.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH 2/4] clk: imx: add i.MX93 composite clk
Date: Mon, 21 Feb 2022 14:09:48 +0200 [thread overview]
Message-ID: <YhOBDJDdL0Z2tk/j@abelvesa> (raw)
In-Reply-To: <20220215081835.790311-3-peng.fan@oss.nxp.com>
On 22-02-15 16:18:33, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here
> is to combine all these into one composite clk and simplify clk tree.
> i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/clk/imx/Makefile | 1 +
> drivers/clk/imx/clk-composite-93.c | 93 ++++++++++++++++++++++++++++++
> drivers/clk/imx/clk.h | 9 +++
> 3 files changed, 103 insertions(+)
> create mode 100644 drivers/clk/imx/clk-composite-93.c
>
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index b5e040026dfb..15549a1c332f 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -4,6 +4,7 @@ mxc-clk-objs += clk.o
> mxc-clk-objs += clk-busy.o
> mxc-clk-objs += clk-composite-7ulp.o
> mxc-clk-objs += clk-composite-8m.o
> +mxc-clk-objs += clk-composite-93.o
> mxc-clk-objs += clk-cpu.o
> mxc-clk-objs += clk-divider-gate.o
> mxc-clk-objs += clk-fixup-div.o
> diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c
> new file mode 100644
> index 000000000000..b44619aa5ca5
> --- /dev/null
> +++ b/drivers/clk/imx/clk-composite-93.c
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + *
> + * Peng Fan <peng.fan@nxp.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/errno.h>
> +#include <linux/export.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +
> +#include "clk.h"
> +
> +#define CCM_DIV_SHIFT 0
> +#define CCM_DIV_WIDTH 8
> +#define CCM_MUX_SHIFT 8
> +#define CCM_MUX_MASK 3
> +#define CCM_OFF_SHIFT 24
> +
> +#define AUTHEN_OFFSET 0x30
> +#define TZ_NS_SHIFT 9
> +#define TZ_NS_MASK BIT(9)
> +
> +struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names,
> + int num_parents, void __iomem *reg,
> + unsigned long flags)
> +{
> + struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
> + struct clk_hw *div_hw, *gate_hw;
> + struct clk_divider *div = NULL;
> + struct clk_gate *gate = NULL;
> + struct clk_mux *mux = NULL;
> + bool clk_ro = false;
> +
> + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> + if (!mux)
> + goto fail;
> +
> + mux_hw = &mux->hw;
> + mux->reg = reg;
> + mux->shift = CCM_MUX_SHIFT;
> + mux->mask = CCM_MUX_MASK;
> + mux->lock = &imx_ccm_lock;
> +
> + div = kzalloc(sizeof(*div), GFP_KERNEL);
> + if (!div)
> + goto fail;
> +
> + div_hw = &div->hw;
> + div->reg = reg;
> + div->shift = CCM_DIV_SHIFT;
> + div->width = CCM_DIV_WIDTH;
> + div->lock = &imx_ccm_lock;
> + div->flags = CLK_DIVIDER_ROUND_CLOSEST;
> +
> + if (!(readl(reg + AUTHEN_OFFSET) & TZ_NS_MASK))
> + clk_ro = true;
> +
> + if (clk_ro) {
> + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> + mux_hw, &clk_mux_ro_ops, div_hw,
> + &clk_divider_ro_ops, NULL, NULL, flags);
> + } else {
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + goto fail;
> +
> + gate_hw = &gate->hw;
> + gate->reg = reg;
> + gate->bit_idx = CCM_OFF_SHIFT;
> + gate->lock = &imx_ccm_lock;
> + gate->flags = CLK_GATE_SET_TO_DISABLE;
> +
> + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> + mux_hw, &clk_mux_ops, div_hw,
> + &clk_divider_ops, gate_hw,
> + &clk_gate_ops, flags | CLK_SET_RATE_NO_REPARENT);
Just a thought. Could we just extend the imx8m_composite to do this, instead
of adding this new one? I mean, just because it is a new SoC, doesn't
mean we can't reuse the imx8m composite.
> + }
> +
> + if (IS_ERR(hw))
> + goto fail;
> +
> + return hw;
> +
> +fail:
> + kfree(gate);
> + kfree(div);
> + kfree(mux);
> + return ERR_CAST(hw);
> +}
> +EXPORT_SYMBOL_GPL(imx93_clk_composite_flags);
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index 7d220a01de1f..63eb7c53b123 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -419,6 +419,15 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
> IMX_COMPOSITE_FW_MANAGED, \
> IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE)
>
> +struct clk_hw *imx93_clk_composite_flags(const char *name,
> + const char * const *parent_names,
> + int num_parents,
> + void __iomem *reg,
> + unsigned long flags);
> +#define imx93_clk_composite(name, parent_names, num_parents, reg) \
> + imx93_clk_composite_flags(name, parent_names, num_parents, reg, \
> + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
> +
> struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
> unsigned long flags, void __iomem *reg, u8 shift, u8 width,
> u8 clk_divider_flags, const struct clk_div_table *table,
> --
> 2.25.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-02-21 12:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-15 8:18 [PATCH 0/4] imx: add i.MX93 clk bindings and driver Peng Fan (OSS)
2022-02-15 8:18 ` Peng Fan (OSS)
2022-02-15 8:18 ` [PATCH 1/4] dt-bindings: clock: Add imx93 clock support Peng Fan (OSS)
2022-02-15 8:18 ` Peng Fan (OSS)
2022-02-21 11:55 ` Abel Vesa
2022-02-21 11:55 ` Abel Vesa
2022-02-15 8:18 ` [PATCH 2/4] clk: imx: add i.MX93 composite clk Peng Fan (OSS)
2022-02-15 8:18 ` Peng Fan (OSS)
2022-02-21 12:09 ` Abel Vesa [this message]
2022-02-21 12:09 ` Abel Vesa
2022-02-15 8:18 ` [PATCH 3/4] clk: imx: support fracn gppll Peng Fan (OSS)
2022-02-15 8:18 ` Peng Fan (OSS)
2022-02-15 11:44 ` kernel test robot
2022-02-15 11:44 ` kernel test robot
2022-02-15 11:44 ` kernel test robot
2022-02-15 14:07 ` kernel test robot
2022-02-15 14:07 ` kernel test robot
2022-02-15 14:07 ` kernel test robot
2022-02-15 8:18 ` [PATCH 4/4] clk: imx: add i.MX93 clk Peng Fan (OSS)
2022-02-15 8:18 ` Peng Fan (OSS)
2022-02-21 12:45 ` Abel Vesa
2022-02-21 12:45 ` Abel Vesa
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YhOBDJDdL0Z2tk/j@abelvesa \
--to=abel.vesa@nxp.com \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=kernel@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=peng.fan@nxp.com \
--cc=peng.fan@oss.nxp.com \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=sboyd@kernel.org \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.