From: Rob Herring <robh@kernel.org>
To: Sui Jingfeng <15330273260@189.cn>
Cc: Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Roland Scheidegger <sroland@vmware.com>,
Zack Rusin <zackr@vmware.com>,
Christian Gmeiner <christian.gmeiner@gmail.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Dan Carpenter <dan.carpenter@oracle.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>,
Sam Ravnborg <sam@ravnborg.org>,
"David S . Miller" <davem@davemloft.net>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Lucas Stach <l.stach@pengutronix.de>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Ilia Mirkin <imirkin@alum.mit.edu>,
Qing Zhang <zhangqing@loongson.cn>,
suijingfeng <suijingfeng@loongson.cn>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
kernel test robot <lkp@intel.com>
Subject: Re: [PATCH v11 7/7] drm/lsdc: add drm driver for loongson display controller
Date: Thu, 24 Mar 2022 08:42:47 -0500 [thread overview]
Message-ID: <Yjx1V1Lx0bAtgsCp@robh.at.kernel.org> (raw)
In-Reply-To: <33766d08-bd88-2234-0f85-5926e4256dfb@189.cn>
On Thu, Mar 24, 2022 at 09:39:49AM +0800, Sui Jingfeng wrote:
>
> On 2022/3/23 04:49, Rob Herring wrote:
> > On Tue, Mar 22, 2022 at 12:29:16AM +0800, Sui Jingfeng wrote:
> > > From: suijingfeng <suijingfeng@loongson.cn>
> > >
> > > There is a display controller in loongson's LS2K1000 SoC and LS7A1000
> > > bridge chip, the display controller is a PCI device in those chips. It
> > > has two display pipes but with only one hardware cursor. Each way has
> > > a DVO interface which provide RGB888 signals, vertical & horizontal
> > > synchronisations, data enable and the pixel clock. Each CRTC is able to
> > > scanout from 1920x1080 resolution at 60Hz, the maxmium resolution is
> > > 2048x2048 according to the hardware spec. Loongson display controllers
> > > are simple which require scanout buffers to be physically contiguous.
[...]
> > > + val |= mask;
> > > + else
> > > + val &= ~mask;
> > > + writeb(val, li2c->dat_reg);
> > Shouldn't you set the data register low first and then change the
> > direction? Otherwise, you may be driving high for a moment. However, if
> > high is always done by setting the direction as input, why write the
> > data register each time? I'm assuming whatever is written to the dat_reg
> > is maintained regardless of pin state.
> >
> When the pin is input, i am not sure value written to it will be preserved.
>
> I'm worry about it get flushed by the external input value.
>
> Because the output data register is same with the input data register(
> offset is 0x1650).
>
> The hardware designer do not provided a separation.
Usually for GPIO data registers the read value is current pin state
regardless of direction and the written value is what to drive as an
output. But your h/w could be different.
> > > +
> > > + /* Optional properties which made the driver more flexible */
> > > + of_property_read_u32(i2c_np, "udelay", &udelay);
> > > + of_property_read_u32(i2c_np, "timeout", &timeout);
> > These aren't documented. Do you really need them in DT?
>
> Yes, in very rare case:
>
> When debugging, sometimes one way I2C works, another way I2C not on specific
> board.
This is not specific to you, so why do you solve it in a way that only
works for you? If you want to add tuning parameters to the i2c bit
algorithm, why don't you do so in a way that works for all users? I'm
sure the I2C maintainer and others have some opinion on this, but
they'll never see it hidden away in some display driver.
> and you want to see what will happen if you change it from 5 to 2.
>
> modify device tree is enough, have to recompile the kernel and driver
> modules every time.
Modifying the DT is not the easiest way to debug either.
> It is optional through.
Lots of properties are optional, what's your point?
> Please do not ask me to document such a easy thing,
Everything must be documented. There's nothing more to discuss.
> DT itself is a documention, human readable, it already speak for itself.
It is machine readable too. Undocumented properties generate warnings
now.
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Sui Jingfeng <15330273260@189.cn>
Cc: Qing Zhang <zhangqing@loongson.cn>,
David Airlie <airlied@linux.ie>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
linux-kernel@vger.kernel.org, Sam Ravnborg <sam@ravnborg.org>,
kernel test robot <lkp@intel.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Dan Carpenter <dan.carpenter@oracle.com>,
devicetree@vger.kernel.org, suijingfeng <suijingfeng@loongson.cn>,
Thomas Zimmermann <tzimmermann@suse.de>,
Roland Scheidegger <sroland@vmware.com>,
Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>,
dri-devel@lists.freedesktop.org,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
linux-mips@vger.kernel.org,
"David S . Miller" <davem@davemloft.net>
Subject: Re: [PATCH v11 7/7] drm/lsdc: add drm driver for loongson display controller
Date: Thu, 24 Mar 2022 08:42:47 -0500 [thread overview]
Message-ID: <Yjx1V1Lx0bAtgsCp@robh.at.kernel.org> (raw)
In-Reply-To: <33766d08-bd88-2234-0f85-5926e4256dfb@189.cn>
On Thu, Mar 24, 2022 at 09:39:49AM +0800, Sui Jingfeng wrote:
>
> On 2022/3/23 04:49, Rob Herring wrote:
> > On Tue, Mar 22, 2022 at 12:29:16AM +0800, Sui Jingfeng wrote:
> > > From: suijingfeng <suijingfeng@loongson.cn>
> > >
> > > There is a display controller in loongson's LS2K1000 SoC and LS7A1000
> > > bridge chip, the display controller is a PCI device in those chips. It
> > > has two display pipes but with only one hardware cursor. Each way has
> > > a DVO interface which provide RGB888 signals, vertical & horizontal
> > > synchronisations, data enable and the pixel clock. Each CRTC is able to
> > > scanout from 1920x1080 resolution at 60Hz, the maxmium resolution is
> > > 2048x2048 according to the hardware spec. Loongson display controllers
> > > are simple which require scanout buffers to be physically contiguous.
[...]
> > > + val |= mask;
> > > + else
> > > + val &= ~mask;
> > > + writeb(val, li2c->dat_reg);
> > Shouldn't you set the data register low first and then change the
> > direction? Otherwise, you may be driving high for a moment. However, if
> > high is always done by setting the direction as input, why write the
> > data register each time? I'm assuming whatever is written to the dat_reg
> > is maintained regardless of pin state.
> >
> When the pin is input, i am not sure value written to it will be preserved.
>
> I'm worry about it get flushed by the external input value.
>
> Because the output data register is same with the input data register(
> offset is 0x1650).
>
> The hardware designer do not provided a separation.
Usually for GPIO data registers the read value is current pin state
regardless of direction and the written value is what to drive as an
output. But your h/w could be different.
> > > +
> > > + /* Optional properties which made the driver more flexible */
> > > + of_property_read_u32(i2c_np, "udelay", &udelay);
> > > + of_property_read_u32(i2c_np, "timeout", &timeout);
> > These aren't documented. Do you really need them in DT?
>
> Yes, in very rare case:
>
> When debugging, sometimes one way I2C works, another way I2C not on specific
> board.
This is not specific to you, so why do you solve it in a way that only
works for you? If you want to add tuning parameters to the i2c bit
algorithm, why don't you do so in a way that works for all users? I'm
sure the I2C maintainer and others have some opinion on this, but
they'll never see it hidden away in some display driver.
> and you want to see what will happen if you change it from 5 to 2.
>
> modify device tree is enough, have to recompile the kernel and driver
> modules every time.
Modifying the DT is not the easiest way to debug either.
> It is optional through.
Lots of properties are optional, what's your point?
> Please do not ask me to document such a easy thing,
Everything must be documented. There's nothing more to discuss.
> DT itself is a documention, human readable, it already speak for itself.
It is machine readable too. Undocumented properties generate warnings
now.
Rob
next prev parent reply other threads:[~2022-03-24 13:42 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-21 16:29 [PATCH v11 0/7] drm/lsdc: add drm driver for loongson display controller Sui Jingfeng
2022-03-21 16:29 ` Sui Jingfeng
2022-03-21 16:29 ` [PATCH v11 1/7] MIPS: Loongson64: dts: update the display controller device node Sui Jingfeng
2022-03-21 16:29 ` Sui Jingfeng
2022-03-21 16:29 ` [PATCH v11 2/7] MIPS: Loongson64: dts: introduce ls3A4000 evaluation board Sui Jingfeng
2022-03-21 16:29 ` Sui Jingfeng
2022-03-22 13:05 ` Jiaxun Yang
2022-03-22 13:05 ` Jiaxun Yang
2022-03-22 13:38 ` Sui Jingfeng
2022-03-22 13:38 ` Sui Jingfeng
2022-03-22 16:06 ` Jiaxun Yang
2022-03-22 16:06 ` Jiaxun Yang
2022-03-23 1:53 ` Sui Jingfeng
2022-03-23 1:53 ` Sui Jingfeng
2022-03-23 2:29 ` Jiaxun Yang
2022-03-23 2:29 ` Jiaxun Yang
2022-03-23 3:07 ` Sui Jingfeng
2022-03-23 3:07 ` Sui Jingfeng
2022-03-23 3:14 ` Jiaxun Yang
2022-03-23 3:14 ` Jiaxun Yang
2022-03-23 7:07 ` Sui Jingfeng
2022-03-23 7:07 ` Sui Jingfeng
2022-03-23 12:29 ` Jiaxun Yang
2022-03-23 12:29 ` Jiaxun Yang
2022-03-23 12:53 ` Rob Herring
2022-03-23 12:53 ` Rob Herring
2022-03-24 1:51 ` Sui Jingfeng
2022-03-24 1:51 ` Sui Jingfeng
2022-03-21 16:29 ` [PATCH v11 3/7] MIPS: Loongson64: dts: introduce lemote A1901 motherboard Sui Jingfeng
2022-03-21 16:29 ` Sui Jingfeng
2022-03-21 16:29 ` [PATCH v11 4/7] MIPS: Loongson64: dts: introduce ls2k1000 pai evaluation board Sui Jingfeng
2022-03-21 16:29 ` Sui Jingfeng
2022-03-21 16:29 ` [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller Sui Jingfeng
2022-03-21 16:29 ` Sui Jingfeng
2022-03-21 23:20 ` Rob Herring
2022-03-21 23:20 ` Rob Herring
2022-03-22 2:33 ` Sui Jingfeng
2022-03-22 2:33 ` Sui Jingfeng
2022-03-22 13:08 ` Jiaxun Yang
2022-03-22 13:08 ` Jiaxun Yang
2022-03-22 13:54 ` Sui Jingfeng
2022-03-22 13:54 ` Sui Jingfeng
2022-03-22 16:08 ` Jiaxun Yang
2022-03-22 16:08 ` Jiaxun Yang
2022-03-22 20:03 ` Rob Herring
2022-03-22 20:03 ` Rob Herring
2022-03-22 20:55 ` Rob Herring
2022-03-22 20:55 ` Rob Herring
2022-03-23 3:38 ` Sui Jingfeng
2022-03-23 3:38 ` Sui Jingfeng
2022-03-23 13:03 ` Rob Herring
2022-03-23 13:03 ` Rob Herring
2022-03-24 1:48 ` Sui Jingfeng
2022-03-24 1:48 ` Sui Jingfeng
2022-03-24 13:26 ` Rob Herring
2022-03-24 13:26 ` Rob Herring
2022-03-26 10:04 ` Sui Jingfeng
2022-03-26 10:04 ` Sui Jingfeng
2022-03-28 14:04 ` Rob Herring
2022-03-28 14:04 ` Rob Herring
2022-03-29 2:02 ` Sui Jingfeng
2022-03-29 2:02 ` Sui Jingfeng
2022-03-29 13:24 ` Rob Herring
2022-03-29 13:24 ` Rob Herring
2022-03-21 16:29 ` [PATCH v11 6/7] MIPS: Loongson64: defconfig: enable display bridge drivers on Loongson64 Sui Jingfeng
2022-03-21 16:29 ` Sui Jingfeng
2022-03-21 16:29 ` [PATCH v11 7/7] drm/lsdc: add drm driver for loongson display controller Sui Jingfeng
2022-03-21 16:29 ` Sui Jingfeng
2022-03-22 20:49 ` Rob Herring
2022-03-22 20:49 ` Rob Herring
2022-03-23 4:12 ` Sui Jingfeng
2022-03-23 4:12 ` Sui Jingfeng
2022-03-23 13:11 ` Rob Herring
2022-03-23 13:11 ` Rob Herring
2022-03-24 4:05 ` Sui Jingfeng
2022-03-24 4:05 ` Sui Jingfeng
2022-04-08 2:09 ` Sui Jingfeng
2022-04-08 2:09 ` Sui Jingfeng
2022-03-23 4:19 ` Sui Jingfeng
2022-03-23 4:19 ` Sui Jingfeng
2022-03-23 8:49 ` Sui Jingfeng
2022-03-23 8:49 ` Sui Jingfeng
2022-03-23 9:31 ` Sui Jingfeng
2022-03-23 9:31 ` Sui Jingfeng
2022-03-24 1:39 ` Sui Jingfeng
2022-03-24 1:39 ` Sui Jingfeng
2022-03-24 13:42 ` Rob Herring [this message]
2022-03-24 13:42 ` Rob Herring
2022-03-24 7:32 ` Sui Jingfeng
2022-03-24 7:32 ` Sui Jingfeng
2022-03-24 13:56 ` Rob Herring
2022-03-24 13:56 ` Rob Herring
2023-01-17 3:08 ` Sui jingfeng
2023-02-03 2:48 ` suijingfeng
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