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From: Rob Herring <robh@kernel.org>
To: linux-aspeed@lists.ozlabs.org
Subject: [PATCH v6 03/11] spi: spi-mem: Convert Aspeed SMC driver to spi-mem
Date: Tue, 3 May 2022 12:55:04 -0500	[thread overview]
Message-ID: <YnFseFBfe5eaIqg0@robh.at.kernel.org> (raw)
In-Reply-To: <20220503060634.122722-4-clg@kaod.org>

On Tue, May 03, 2022 at 08:06:26AM +0200, C?dric Le Goater wrote:
> This SPI driver adds support for the Aspeed static memory controllers
> of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
> 
>  * AST2600 Firmware SPI Memory Controller (FMC)
>    . BMC firmware
>    . 3 chip select pins (CE0 ~ CE2)
>    . Only supports SPI type flash memory
>    . different segment register interface
>    . single, dual and quad mode.
> 
>  * AST2600 SPI Flash Controller (SPI1 and SPI2)
>    . host firmware
>    . 2 chip select pins (CE0 ~ CE1)
>    . different segment register interface
>    . single, dual and quad mode.
> 
>  * AST2500 Firmware SPI Memory Controller (FMC)
>    . BMC firmware
>    . 3 chip select pins (CE0 ~ CE2)
>    . supports SPI type flash memory (CE0-CE1)
>    . CE2 can be of NOR type flash but this is not supported by the driver
>    . single, dual mode.
> 
>  * AST2500 SPI Flash Controller (SPI1 and SPI2)
>    . host firmware
>    . 2 chip select pins (CE0 ~ CE1)
>    . single, dual mode.
> 
>  * AST2400 New Static Memory Controller (also referred as FMC)
>    . BMC firmware
>    . New register set
>    . 5 chip select pins (CE0 ? CE4)
>    . supports NOR flash, NAND flash and SPI flash memory.
>    . single, dual and quad mode.
> 
> Each controller has a memory range on which flash devices contents are
> mapped. Each device is assigned a window that can be changed at bootime
> with the Segment Address Registers.
> 
> Each SPI flash device can then be accessed in two modes: Command and
> User. When in User mode, SPI transfers are initiated with accesses to
> the memory segment of a device. When in Command mode, memory
> operations on the memory segment of a device generate SPI commands
> automatically using a Control Register for the settings.
> 
> This initial patch adds support for User mode. Command mode needs a little
> more work to check that the memory window on the AHB bus fits the device
> size. It will come later when support for direct mapping is added.
> 
> Single and dual mode RX transfers are supported. Other types than SPI
> are not supported.
> 
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Tested-by: Joel Stanley <joel@jms.id.au>
> Tested-by: Tao Ren <rentao.bupt@gmail.com>
> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: C?dric Le Goater <clg@kaod.org>
> ---
>  drivers/mtd/spi-nor/controllers/aspeed-smc.c  | 921 ------------------
>  drivers/spi/spi-aspeed-smc.c                  | 717 ++++++++++++++
>  .../devicetree/bindings/mtd/aspeed-smc.txt    |  51 -

This belongs with the binding patch. But then it is converting rather 
than adding a binding. You should be converting the binding and then 
adding to it (like adding 2600 support).

>  MAINTAINERS                                   |   1 +
>  drivers/mtd/spi-nor/controllers/Kconfig       |  10 -
>  drivers/mtd/spi-nor/controllers/Makefile      |   1 -
>  drivers/spi/Kconfig                           |  11 +
>  drivers/spi/Makefile                          |   1 +
>  8 files changed, 730 insertions(+), 983 deletions(-)
>  delete mode 100644 drivers/mtd/spi-nor/controllers/aspeed-smc.c
>  create mode 100644 drivers/spi/spi-aspeed-smc.c
>  delete mode 100644 Documentation/devicetree/bindings/mtd/aspeed-smc.txt

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org,
	Mark Brown <broonie@kernel.org>,
	Tudor Ambarus <tudor.ambarus@microchip.com>,
	Pratyush Yadav <p.yadav@ti.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	linux-aspeed@lists.ozlabs.org, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@aj.id.au>,
	Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Tao Ren <rentao.bupt@gmail.com>,
	Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Subject: Re: [PATCH v6 03/11] spi: spi-mem: Convert Aspeed SMC driver to spi-mem
Date: Tue, 3 May 2022 12:55:04 -0500	[thread overview]
Message-ID: <YnFseFBfe5eaIqg0@robh.at.kernel.org> (raw)
In-Reply-To: <20220503060634.122722-4-clg@kaod.org>

On Tue, May 03, 2022 at 08:06:26AM +0200, Cédric Le Goater wrote:
> This SPI driver adds support for the Aspeed static memory controllers
> of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
> 
>  * AST2600 Firmware SPI Memory Controller (FMC)
>    . BMC firmware
>    . 3 chip select pins (CE0 ~ CE2)
>    . Only supports SPI type flash memory
>    . different segment register interface
>    . single, dual and quad mode.
> 
>  * AST2600 SPI Flash Controller (SPI1 and SPI2)
>    . host firmware
>    . 2 chip select pins (CE0 ~ CE1)
>    . different segment register interface
>    . single, dual and quad mode.
> 
>  * AST2500 Firmware SPI Memory Controller (FMC)
>    . BMC firmware
>    . 3 chip select pins (CE0 ~ CE2)
>    . supports SPI type flash memory (CE0-CE1)
>    . CE2 can be of NOR type flash but this is not supported by the driver
>    . single, dual mode.
> 
>  * AST2500 SPI Flash Controller (SPI1 and SPI2)
>    . host firmware
>    . 2 chip select pins (CE0 ~ CE1)
>    . single, dual mode.
> 
>  * AST2400 New Static Memory Controller (also referred as FMC)
>    . BMC firmware
>    . New register set
>    . 5 chip select pins (CE0 ∼ CE4)
>    . supports NOR flash, NAND flash and SPI flash memory.
>    . single, dual and quad mode.
> 
> Each controller has a memory range on which flash devices contents are
> mapped. Each device is assigned a window that can be changed at bootime
> with the Segment Address Registers.
> 
> Each SPI flash device can then be accessed in two modes: Command and
> User. When in User mode, SPI transfers are initiated with accesses to
> the memory segment of a device. When in Command mode, memory
> operations on the memory segment of a device generate SPI commands
> automatically using a Control Register for the settings.
> 
> This initial patch adds support for User mode. Command mode needs a little
> more work to check that the memory window on the AHB bus fits the device
> size. It will come later when support for direct mapping is added.
> 
> Single and dual mode RX transfers are supported. Other types than SPI
> are not supported.
> 
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Tested-by: Joel Stanley <joel@jms.id.au>
> Tested-by: Tao Ren <rentao.bupt@gmail.com>
> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  drivers/mtd/spi-nor/controllers/aspeed-smc.c  | 921 ------------------
>  drivers/spi/spi-aspeed-smc.c                  | 717 ++++++++++++++
>  .../devicetree/bindings/mtd/aspeed-smc.txt    |  51 -

This belongs with the binding patch. But then it is converting rather 
than adding a binding. You should be converting the binding and then 
adding to it (like adding 2600 support).

>  MAINTAINERS                                   |   1 +
>  drivers/mtd/spi-nor/controllers/Kconfig       |  10 -
>  drivers/mtd/spi-nor/controllers/Makefile      |   1 -
>  drivers/spi/Kconfig                           |  11 +
>  drivers/spi/Makefile                          |   1 +
>  8 files changed, 730 insertions(+), 983 deletions(-)
>  delete mode 100644 drivers/mtd/spi-nor/controllers/aspeed-smc.c
>  create mode 100644 drivers/spi/spi-aspeed-smc.c
>  delete mode 100644 Documentation/devicetree/bindings/mtd/aspeed-smc.txt

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org,
	Mark Brown <broonie@kernel.org>,
	Tudor Ambarus <tudor.ambarus@microchip.com>,
	Pratyush Yadav <p.yadav@ti.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	linux-aspeed@lists.ozlabs.org, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@aj.id.au>,
	Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Tao Ren <rentao.bupt@gmail.com>,
	Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Subject: Re: [PATCH v6 03/11] spi: spi-mem: Convert Aspeed SMC driver to spi-mem
Date: Tue, 3 May 2022 12:55:04 -0500	[thread overview]
Message-ID: <YnFseFBfe5eaIqg0@robh.at.kernel.org> (raw)
In-Reply-To: <20220503060634.122722-4-clg@kaod.org>

On Tue, May 03, 2022 at 08:06:26AM +0200, Cédric Le Goater wrote:
> This SPI driver adds support for the Aspeed static memory controllers
> of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
> 
>  * AST2600 Firmware SPI Memory Controller (FMC)
>    . BMC firmware
>    . 3 chip select pins (CE0 ~ CE2)
>    . Only supports SPI type flash memory
>    . different segment register interface
>    . single, dual and quad mode.
> 
>  * AST2600 SPI Flash Controller (SPI1 and SPI2)
>    . host firmware
>    . 2 chip select pins (CE0 ~ CE1)
>    . different segment register interface
>    . single, dual and quad mode.
> 
>  * AST2500 Firmware SPI Memory Controller (FMC)
>    . BMC firmware
>    . 3 chip select pins (CE0 ~ CE2)
>    . supports SPI type flash memory (CE0-CE1)
>    . CE2 can be of NOR type flash but this is not supported by the driver
>    . single, dual mode.
> 
>  * AST2500 SPI Flash Controller (SPI1 and SPI2)
>    . host firmware
>    . 2 chip select pins (CE0 ~ CE1)
>    . single, dual mode.
> 
>  * AST2400 New Static Memory Controller (also referred as FMC)
>    . BMC firmware
>    . New register set
>    . 5 chip select pins (CE0 ∼ CE4)
>    . supports NOR flash, NAND flash and SPI flash memory.
>    . single, dual and quad mode.
> 
> Each controller has a memory range on which flash devices contents are
> mapped. Each device is assigned a window that can be changed at bootime
> with the Segment Address Registers.
> 
> Each SPI flash device can then be accessed in two modes: Command and
> User. When in User mode, SPI transfers are initiated with accesses to
> the memory segment of a device. When in Command mode, memory
> operations on the memory segment of a device generate SPI commands
> automatically using a Control Register for the settings.
> 
> This initial patch adds support for User mode. Command mode needs a little
> more work to check that the memory window on the AHB bus fits the device
> size. It will come later when support for direct mapping is added.
> 
> Single and dual mode RX transfers are supported. Other types than SPI
> are not supported.
> 
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Tested-by: Joel Stanley <joel@jms.id.au>
> Tested-by: Tao Ren <rentao.bupt@gmail.com>
> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  drivers/mtd/spi-nor/controllers/aspeed-smc.c  | 921 ------------------
>  drivers/spi/spi-aspeed-smc.c                  | 717 ++++++++++++++
>  .../devicetree/bindings/mtd/aspeed-smc.txt    |  51 -

This belongs with the binding patch. But then it is converting rather 
than adding a binding. You should be converting the binding and then 
adding to it (like adding 2600 support).

>  MAINTAINERS                                   |   1 +
>  drivers/mtd/spi-nor/controllers/Kconfig       |  10 -
>  drivers/mtd/spi-nor/controllers/Makefile      |   1 -
>  drivers/spi/Kconfig                           |  11 +
>  drivers/spi/Makefile                          |   1 +
>  8 files changed, 730 insertions(+), 983 deletions(-)
>  delete mode 100644 drivers/mtd/spi-nor/controllers/aspeed-smc.c
>  create mode 100644 drivers/spi/spi-aspeed-smc.c
>  delete mode 100644 Documentation/devicetree/bindings/mtd/aspeed-smc.txt

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org,
	Mark Brown <broonie@kernel.org>,
	Tudor Ambarus <tudor.ambarus@microchip.com>,
	Pratyush Yadav <p.yadav@ti.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	linux-aspeed@lists.ozlabs.org, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@aj.id.au>,
	Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Tao Ren <rentao.bupt@gmail.com>,
	Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Subject: Re: [PATCH v6 03/11] spi: spi-mem: Convert Aspeed SMC driver to spi-mem
Date: Tue, 3 May 2022 12:55:04 -0500	[thread overview]
Message-ID: <YnFseFBfe5eaIqg0@robh.at.kernel.org> (raw)
In-Reply-To: <20220503060634.122722-4-clg@kaod.org>

On Tue, May 03, 2022 at 08:06:26AM +0200, Cédric Le Goater wrote:
> This SPI driver adds support for the Aspeed static memory controllers
> of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
> 
>  * AST2600 Firmware SPI Memory Controller (FMC)
>    . BMC firmware
>    . 3 chip select pins (CE0 ~ CE2)
>    . Only supports SPI type flash memory
>    . different segment register interface
>    . single, dual and quad mode.
> 
>  * AST2600 SPI Flash Controller (SPI1 and SPI2)
>    . host firmware
>    . 2 chip select pins (CE0 ~ CE1)
>    . different segment register interface
>    . single, dual and quad mode.
> 
>  * AST2500 Firmware SPI Memory Controller (FMC)
>    . BMC firmware
>    . 3 chip select pins (CE0 ~ CE2)
>    . supports SPI type flash memory (CE0-CE1)
>    . CE2 can be of NOR type flash but this is not supported by the driver
>    . single, dual mode.
> 
>  * AST2500 SPI Flash Controller (SPI1 and SPI2)
>    . host firmware
>    . 2 chip select pins (CE0 ~ CE1)
>    . single, dual mode.
> 
>  * AST2400 New Static Memory Controller (also referred as FMC)
>    . BMC firmware
>    . New register set
>    . 5 chip select pins (CE0 ∼ CE4)
>    . supports NOR flash, NAND flash and SPI flash memory.
>    . single, dual and quad mode.
> 
> Each controller has a memory range on which flash devices contents are
> mapped. Each device is assigned a window that can be changed at bootime
> with the Segment Address Registers.
> 
> Each SPI flash device can then be accessed in two modes: Command and
> User. When in User mode, SPI transfers are initiated with accesses to
> the memory segment of a device. When in Command mode, memory
> operations on the memory segment of a device generate SPI commands
> automatically using a Control Register for the settings.
> 
> This initial patch adds support for User mode. Command mode needs a little
> more work to check that the memory window on the AHB bus fits the device
> size. It will come later when support for direct mapping is added.
> 
> Single and dual mode RX transfers are supported. Other types than SPI
> are not supported.
> 
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Tested-by: Joel Stanley <joel@jms.id.au>
> Tested-by: Tao Ren <rentao.bupt@gmail.com>
> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  drivers/mtd/spi-nor/controllers/aspeed-smc.c  | 921 ------------------
>  drivers/spi/spi-aspeed-smc.c                  | 717 ++++++++++++++
>  .../devicetree/bindings/mtd/aspeed-smc.txt    |  51 -

This belongs with the binding patch. But then it is converting rather 
than adding a binding. You should be converting the binding and then 
adding to it (like adding 2600 support).

>  MAINTAINERS                                   |   1 +
>  drivers/mtd/spi-nor/controllers/Kconfig       |  10 -
>  drivers/mtd/spi-nor/controllers/Makefile      |   1 -
>  drivers/spi/Kconfig                           |  11 +
>  drivers/spi/Makefile                          |   1 +
>  8 files changed, 730 insertions(+), 983 deletions(-)
>  delete mode 100644 drivers/mtd/spi-nor/controllers/aspeed-smc.c
>  create mode 100644 drivers/spi/spi-aspeed-smc.c
>  delete mode 100644 Documentation/devicetree/bindings/mtd/aspeed-smc.txt

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-05-03 17:55 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03  6:06 [PATCH v6 00/11] spi: spi-mem: Convert Aspeed SMC driver to spi-mem Cédric Le Goater
2022-05-03  6:06 ` Cédric Le Goater
2022-05-03  6:06 ` Cédric Le Goater
2022-05-03  6:06 ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 01/11] ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 02/11] dt-bindings: spi: Add Aspeed SMC controllers device tree binding Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 03/11] spi: spi-mem: Convert Aspeed SMC driver to spi-mem Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03 17:55   ` Rob Herring [this message]
2022-05-03 17:55     ` Rob Herring
2022-05-03 17:55     ` Rob Herring
2022-05-03 17:55     ` Rob Herring
2022-05-08  7:14     ` Cédric Le Goater
2022-05-08  7:14       ` Cédric Le Goater
2022-05-08  7:14       ` Cédric Le Goater
2022-05-08  7:14       ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 04/11] spi: aspeed: Add support for direct mapping Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 05/11] spi: aspeed: Adjust direct mapping to device size Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 06/11] spi: aspeed: Workaround AST2500 limitations Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 07/11] spi: aspeed: Add support for the AST2400 SPI controller Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 08/11] spi: aspeed: Calibrate read timings Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 09/11] ARM: dts: aspeed: Enable Dual SPI RX transfers Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 10/11] ARM: dts: aspeed-g4: Set spi-max-frequency for all flashes Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06 ` [PATCH v6 11/11] mtd: spi-nor: aspeed: set the decoding size to at least 2MB for AST2600 Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:06   ` Cédric Le Goater
2022-05-03  6:43 ` [PATCH v6 00/11] spi: spi-mem: Convert Aspeed SMC driver to spi-mem Joel Stanley
2022-05-03  7:08   ` Cédric Le Goater

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