From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [PATCH v2] hw/openrisc: use right OMPIC size variable
Date: Wed, 4 May 2022 05:22:38 +0900 [thread overview]
Message-ID: <YnGPDumfp1+6DUQG@antec> (raw)
In-Reply-To: <20220503094533.402157-1-Jason@zx2c4.com>
On Tue, May 03, 2022 at 11:45:33AM +0200, Jason A. Donenfeld wrote:
> This appears to be a copy and paste error. The UART size was used
> instead of the much smaller OMPIC size. But actually that smaller OMPIC
> size is wrong too and doesn't allow the IPI to work in Linux. So set it
> to the old value.
>
> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
> ---
> hw/openrisc/openrisc_sim.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
> index 99b14940f4..3218db6656 100644
> --- a/hw/openrisc/openrisc_sim.c
> +++ b/hw/openrisc/openrisc_sim.c
> @@ -78,7 +78,7 @@ static const struct MemmapEntry {
> [OR1KSIM_DRAM] = { 0x00000000, 0 },
> [OR1KSIM_UART] = { 0x90000000, 0x100 },
> [OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
> - [OR1KSIM_OMPIC] = { 0x98000000, 16 },
> + [OR1KSIM_OMPIC] = { 0x98000000, 0x100 },
Right, I missed this as part of my series. OMPIC will allocate 2 32-bit
registers per CPU. I documented this here:
- https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/irqchip/irq-ompic.c
I think what we will want here is something like:
[OR1KSIM_OMPIC] = { 0x98000000, 8 * OR1KSIM_CPUS_MAX },
> };
>
> static struct openrisc_boot_info {
> @@ -410,7 +410,7 @@ static void openrisc_sim_init(MachineState *machine)
>
> if (smp_cpus > 1) {
> openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
> - or1ksim_memmap[OR1KSIM_UART].size,
> + or1ksim_memmap[OR1KSIM_OMPIC].size,
> smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
> }
>
> --
> 2.35.1
>
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com>
To: "Jason A. Donenfeld" <Jason@zx2c4.com>
Cc: qemu-devel@nongnu.org, openrisc@lists.librecores.org,
richard.henderson@linaro.org
Subject: Re: [PATCH v2] hw/openrisc: use right OMPIC size variable
Date: Wed, 4 May 2022 05:22:38 +0900 [thread overview]
Message-ID: <YnGPDumfp1+6DUQG@antec> (raw)
In-Reply-To: <20220503094533.402157-1-Jason@zx2c4.com>
On Tue, May 03, 2022 at 11:45:33AM +0200, Jason A. Donenfeld wrote:
> This appears to be a copy and paste error. The UART size was used
> instead of the much smaller OMPIC size. But actually that smaller OMPIC
> size is wrong too and doesn't allow the IPI to work in Linux. So set it
> to the old value.
>
> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
> ---
> hw/openrisc/openrisc_sim.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
> index 99b14940f4..3218db6656 100644
> --- a/hw/openrisc/openrisc_sim.c
> +++ b/hw/openrisc/openrisc_sim.c
> @@ -78,7 +78,7 @@ static const struct MemmapEntry {
> [OR1KSIM_DRAM] = { 0x00000000, 0 },
> [OR1KSIM_UART] = { 0x90000000, 0x100 },
> [OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
> - [OR1KSIM_OMPIC] = { 0x98000000, 16 },
> + [OR1KSIM_OMPIC] = { 0x98000000, 0x100 },
Right, I missed this as part of my series. OMPIC will allocate 2 32-bit
registers per CPU. I documented this here:
- https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/irqchip/irq-ompic.c
I think what we will want here is something like:
[OR1KSIM_OMPIC] = { 0x98000000, 8 * OR1KSIM_CPUS_MAX },
> };
>
> static struct openrisc_boot_info {
> @@ -410,7 +410,7 @@ static void openrisc_sim_init(MachineState *machine)
>
> if (smp_cpus > 1) {
> openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
> - or1ksim_memmap[OR1KSIM_UART].size,
> + or1ksim_memmap[OR1KSIM_OMPIC].size,
> smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
> }
>
> --
> 2.35.1
>
next prev parent reply other threads:[~2022-05-03 20:22 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-02 23:28 [OpenRISC] [PATCH] hw/openrisc: use right OMPIC size variable Jason A. Donenfeld
2022-05-02 23:28 ` Jason A. Donenfeld
2022-05-02 23:59 ` [OpenRISC] " Richard Henderson
2022-05-02 23:59 ` Richard Henderson
2022-05-03 9:19 ` [OpenRISC] " Stafford Horne
2022-05-03 9:19 ` Stafford Horne
2022-05-03 9:59 ` [OpenRISC] " Jason A. Donenfeld
2022-05-03 9:59 ` Jason A. Donenfeld
2022-05-03 9:45 ` [OpenRISC] [PATCH v2] " Jason A. Donenfeld
2022-05-03 9:45 ` Jason A. Donenfeld
2022-05-03 20:22 ` Stafford Horne [this message]
2022-05-03 20:22 ` Stafford Horne
2022-05-04 11:10 ` Jason A. Donenfeld
2022-05-04 11:10 ` Jason A. Donenfeld
2022-05-04 22:23 ` Stafford Horne
2022-05-04 22:23 ` Stafford Horne
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