From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx
Date: Fri, 20 May 2022 16:10:15 +0100 [thread overview]
Message-ID: <YoevV9qftSi5nN6j@FVFF77S0Q05N> (raw)
In-Reply-To: <20220517182219.2171814-5-broonie@kernel.org>
On Tue, May 17, 2022 at 07:22:14PM +0100, Mark Brown wrote:
> Convert the CPACR system register definitions to be automatically generated
> using the definitions in DDI0487H.a. The kernel does have some additional
> definitions for subfields of SMEN, FPEN and ZEN which are not identified as
> distinct subfields in the architecture so the definitions are not updated
> as part of this patch.
Maybe we should covert those over to an enumeration style?
>
> No functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 2 --
> arch/arm64/tools/sysreg | 16 ++++++++++++++++
> 2 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 5a5d6bdaa806..c30f5aafde34 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -209,7 +209,6 @@
> #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
>
> #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
> -#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
> #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
> #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
>
> @@ -613,7 +612,6 @@
>
> /* VHE encodings for architectural EL0/1 system registers */
> #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
> -#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
The corresponding addition to the sysreg file got caught in the prior patch
(bad rebase?).
> #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
> #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
> #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index e938d1117d36..21d5c140fde3 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -185,6 +185,22 @@ Field 1 A
> Field 0 M
> EndSysreg
>
> +SysregFields CPACR_ELx
> +Res0 63:29
> +Field 28 TTA
> +Res0 27:26
> +Field 25:24 SMEN
> +Res0 23:22
> +Field 21:20 FPEN
> +Res0 19:18
> +Field 17:16 ZEN
> +Res0 15:0
> +EndSysregFields
> +
> +Sysreg CPACR_EL1 3 0 1 0 2
> +Fields CPACR_ELx
> +EndSysreg
These all look right to me for CPACR_EL1.
Thanks,
Mark.
> +
> Sysreg SMPRI_EL1 3 0 1 2 4
> Res0 63:4
> Field 3:0 PRIORITY
> --
> 2.30.2
>
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next prev parent reply other threads:[~2022-05-20 15:11 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
2022-05-17 18:22 ` [PATCH v1 1/9] arm64/sysreg: Generate definitions for CCSIDR2_EL1 Mark Brown
2022-05-20 14:53 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 2/9] arm64/sysreg: Generate definitions for CLIDR_EL1 Mark Brown
2022-05-20 14:56 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 3/9] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx Mark Brown
2022-05-20 15:01 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx Mark Brown
2022-05-20 15:10 ` Mark Rutland [this message]
2022-05-20 15:29 ` Mark Brown
2022-05-17 18:22 ` [PATCH v1 5/9] arm64/sysreg: Generate definitions for CSSELR_EL1 Mark Brown
2022-05-20 15:12 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0 Mark Brown
2022-05-20 15:20 ` Mark Rutland
2022-05-20 15:29 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 7/9] arm64/sysreg: Generate definitions for DACR32_EL2 Mark Brown
2022-05-20 15:22 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0 Mark Brown
2022-05-20 15:26 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 9/9] arm64/sysreg: Generate definitions for FAR_ELx Mark Brown
2022-05-20 15:32 ` Mark Rutland
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