From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0
Date: Fri, 20 May 2022 16:20:25 +0100 [thread overview]
Message-ID: <YoexubSOmEpZSZRO@FVFF77S0Q05N> (raw)
In-Reply-To: <20220517182219.2171814-7-broonie@kernel.org>
On Tue, May 17, 2022 at 07:22:16PM +0100, Mark Brown wrote:
> Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no
> functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 15 +++++++++++++++
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6240149f9818..c77e2310d189 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -461,7 +461,6 @@
> #define SMIDR_EL1_SMPS_SHIFT 15
> #define SMIDR_EL1_AFFINITY_SHIFT 0
>
> -#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
> #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
>
> #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 47c4c45d5dc3..3971e1fb6af4 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -277,6 +277,21 @@ Field 3:1 Level
> Field 0 InD
> EndSysreg
>
> +Sysreg CTR_EL0 3 3 0 0 1
> +Res0 63:38
> +Field 37:32 TminLine
> +Res1 31
> +Res0 30
> +Field 29 DIC
> +Field 28 IDC
> +Field 27:24 CWG
> +Field 23:20 ERG
> +Field 19:16 DminLine
> +Field 15:14 L1Ip
> +Res0 13:4
> +Field 3:0 IminLine
> +EndSysreg
The values all look right to me.
The L1Ip field is an enumeration where:
* 0b00 means VPIPT
* 0b01 means AIVIVT // reserved in ARMv8
* 0b10 means VIPT
* 0b11 means PIPT
So I reckon we want to describe that as:
Enum 15:14 L1Ip
0b00 VPIPT
0b01 AIVIVT # or RESERVED
0b10 VIPT
0b11 PIPT
EndEnum
We have some existing definitions that could be removed (and their users
converted over):
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VPIPT 0
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_RESERVED 1
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VIPT 2
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_PIPT 3
Thanks,
Mark.
> +
> Sysreg SVCR 3 3 4 2 2
> Res0 63:2
> Field 1 ZA
> --
> 2.30.2
>
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next prev parent reply other threads:[~2022-05-20 15:21 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
2022-05-17 18:22 ` [PATCH v1 1/9] arm64/sysreg: Generate definitions for CCSIDR2_EL1 Mark Brown
2022-05-20 14:53 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 2/9] arm64/sysreg: Generate definitions for CLIDR_EL1 Mark Brown
2022-05-20 14:56 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 3/9] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx Mark Brown
2022-05-20 15:01 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx Mark Brown
2022-05-20 15:10 ` Mark Rutland
2022-05-20 15:29 ` Mark Brown
2022-05-17 18:22 ` [PATCH v1 5/9] arm64/sysreg: Generate definitions for CSSELR_EL1 Mark Brown
2022-05-20 15:12 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0 Mark Brown
2022-05-20 15:20 ` Mark Rutland [this message]
2022-05-20 15:29 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 7/9] arm64/sysreg: Generate definitions for DACR32_EL2 Mark Brown
2022-05-20 15:22 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0 Mark Brown
2022-05-20 15:26 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 9/9] arm64/sysreg: Generate definitions for FAR_ELx Mark Brown
2022-05-20 15:32 ` Mark Rutland
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