From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Andrew Cooper <Andrew.Cooper3@citrix.com>
Cc: Jan Beulich <jbeulich@suse.com>, Wei Liu <wl@xen.org>,
"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH 3/5] x86/perf: expose LBR format in PERF_CAPABILITIES
Date: Mon, 23 May 2022 10:04:19 +0200 [thread overview]
Message-ID: <YotAA6ChNKWwSsCg@Air-de-Roger> (raw)
In-Reply-To: <e4d202f7-f4db-71e6-46a1-ee62ef41f2dd@citrix.com>
On Fri, May 20, 2022 at 02:58:01PM +0000, Andrew Cooper wrote:
> On 20/05/2022 15:19, Jan Beulich wrote:
> > On 20.05.2022 16:10, Andrew Cooper wrote:
> >> On 20/05/2022 14:37, Roger Pau Monne wrote:
> >>> --- a/xen/include/public/arch-x86/cpufeatureset.h
> >>> +++ b/xen/include/public/arch-x86/cpufeatureset.h
> >>> @@ -135,7 +135,7 @@ XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensio
> >>> XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */
> >>> XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */
> >>> XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */
> >>> -XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */
> >>> +XEN_CPUFEATURE(PDCM, 1*32+15) /*S Perf/Debug Capability MSR */
> >> This is the bit which requires more toolstack logic to safely enable.
> >> Using 's' for off-by-default is fine if we want to get the series in now.
> >>
> >> But before we expose the MSR generally, we need to:
> >>
> >> 1) Put the configuration in msr_policy so the toolstack can reason about it
> >> 2) Reject migration attempts to destinations where the LBR format changes
> > Since this could be quite restrictive, and since people needing to know
> > they need to hide this feature for migration to work, I guess this would
> > further want qualifying by "did the guest actually use LBRs so far"?
>
> In practice, it's every major generation ("tock" on Intel's old model),
> so isn't actually limiting the kinds of heterogeneous setups used in
> production. (Migration gets steadily less stable the further apart the
> two CPUs are.)
>
> As to dynamic, no - that would be a security bug in a cloud scenario,
> because there must not be anything the guest can do to interfere with
> the manageability.
>
> Use of LBR is rare, as demonstrated by the fact that noone has
> complained about the fact that migrating such a VM will malfunction.
>
> As we now have a way of reporting "no model-specific LBR", I'm tempted
> to suggest that VMs get no LBR by default, and someone wanting LBR has
> to opt in, which is also an explicit agreement to the migration limitation.
I did also consider exposing "no model-specific LBR" in
PERF_CAPABILITIES unconditionally, but I was worried whether that
would break existing setups.
If we think that providing an option to expose the native LBR format
in PERF_CAPABILITIES is fine that could be a sensible solution IMO.
Thanks, Roger.
next prev parent reply other threads:[~2022-05-23 8:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-20 13:37 [PATCH 0/5] x86/lbr: handle lack of model-specific LBRs Roger Pau Monne
2022-05-20 13:37 ` [PATCH 1/5] x86/ler: use feature flag to check if option is enabled Roger Pau Monne
2022-05-30 15:00 ` Jan Beulich
2022-05-20 13:37 ` [PATCH 2/5] x86/lbr: enable hypervisor LER with arch LBR Roger Pau Monne
2022-05-30 15:31 ` Jan Beulich
2022-07-01 15:39 ` Roger Pau Monné
2022-07-04 6:15 ` Jan Beulich
2022-07-04 8:23 ` Roger Pau Monné
2022-05-20 13:37 ` [PATCH 3/5] x86/perf: expose LBR format in PERF_CAPABILITIES Roger Pau Monne
2022-05-20 14:10 ` Andrew Cooper
2022-05-20 14:19 ` Jan Beulich
2022-05-20 14:58 ` Andrew Cooper
2022-05-23 8:04 ` Roger Pau Monné [this message]
2022-05-23 8:12 ` Jan Beulich
2022-05-23 9:53 ` Roger Pau Monné
2022-05-20 14:52 ` Roger Pau Monné
2022-05-20 13:37 ` [PATCH 4/5] x86/vmx: handle no model-specific LBR presence Roger Pau Monne
2022-05-30 16:02 ` Jan Beulich
2022-05-20 13:37 ` [PATCH 5/5] x86/vmx: fix indentation of LBR Roger Pau Monne
2022-06-29 6:40 ` Tian, Kevin
2022-06-17 3:24 ` [PATCH 0/5] x86/lbr: handle lack of model-specific LBRs Henry Wang
2022-07-06 7:30 ` Henry Wang
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